Microprocessor Multiple Choice Questions & Answers (MCQs) “Machine Language Instruction Formats
1. Operation code field is present in :
a) programming language instruction
b) assembly language instruction
c) machine language instruction
d) none of the mentioned
Explanation: Machine language instruction format has one or more fields. The first one is the operation code field.
2. A machine language instruction format consists of
a) Operand field
b) Operation code field
c) Operation code field & operand field
d) none of the mentioned
Explanation: Machine language instruction format has both the fields.
3. The length of the one-byte instruction is
a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes
Explanation: This format is only one byte long.
4. The instruction format ‘register to register’ has a length of
a) 2 bytes
b) 1 byte
c) 3 bytes
d) 4 bytes
Explanation: This format is 2 bytes long.
5. The R/M field in a machine instruction format specifies
a) another register
b) another memory location
c) other operands
d) all of the mentioned
Explanation: The LSBs(least significant bits) from 0 to 3 represent R/M field that specifies another register or memory location i.e. the other operand.
6. In a machine instruction format, S-bit is the
a) status bit
b) sign bit
c) sign extension bit
d) none of the mentioned
Explanation: The S-bit known as sign extension bit is used along with W-bit to show the type of operation.
7. The bit which is used by the ‘REP’ instruction is
a) W-bit
b) S-bit
c) V-bit
d) Z-bit
Explanation: The Z-bit is used by the REP instruction to control the loop.
8. If a W-bit value is ‘1’ then the operand is of
a) 8 bits
b) 4 bits
c) 16 bits
d) 2 bits
Explanation: If W-bit is ‘1’ then the operand is of 16-bits, and if it is ‘0’ then the operand is of 8-bits.
9. The instructions which after execution transfer control to the next instruction in the sequence are called
a) Sequential control flow instructions
b) control transfer instructions
c) Sequential control flow & control transfer instructions
d) none of the mentioned
Explanation: The sequential control flow instructions follow sequence order in their execution.
10. The instructions that transfer the control to some predefined
address or the address specified in the instruction are called as
a) sequential control flow instructions
b) control transfer instructions
c) sequential control flow & control transfer instructions
d) none of the mentioned
Explanation: The control transfer instructions transfer control to the specified address.
11. The instruction “JUMP” belongs to
a) sequential control flow instructions
b) control transfer instructions
c) branch instructions
d) control transfer & branch instructions
Explanation: The JUMP instruction transfers the control to the address located in the instruction.
This set of Microprocessors Interview Questions and Answers focuses on “Instruction Set of 8086/8088 – 2”.
1. The instruction, “INC” increases the contents of the specified register or memory location by
a) 2
b) 0
c) 1
d) 3
Explanation: This instruction adds 1 to the contents of the operand and so increments by 1.
2. The instruction that subtracts 1 from the contents of the specified register/memory location is
a) INC
b) SUBB
c) SUB
d) DEC
Explanation: The DEC instruction decrements the contents of a specified register/memory location by 1.
3. The instruction that enables subtraction with borrow is
a) DEC
b) SUB
c) SBB
d) None of the mentioned
Explanation: The SBB instruction subtracts the source operand and the borrow flag from the destination operand.
4. The flag that acts as Borrow flag in the instruction, SBB is
a) direction flag
b) carry flag
c) parity flag
d) trap flag
Explanation: If borrow exists in the subtraction operation performed then carry flag is set.
5. In general, the source operand of an instruction can be
a) memory location
b) register
c) immediate data
d) all of the mentioned
Explanation: The source operand is the element which is data or data stored memory location on which operation is performed.
6. In general, the destination operand of an instruction can be
a) memory location
b) register
c) immediate data
d) memory location and register
Explanation: Since the destination should be able to store the data, immediate data cannot be considered as a destination operand.
7. The instruction, CMP to compare source and destination operands it performs
a) addition
b) subtraction
c) division
d) multiplication
Explanation: For comparison, the instruction CMP subtracts source operand from destination operand.
8. During comparison operation, the result of comparing or subtraction is stored in
a) memory
b) registers
c) stack
d) no where
Explanation: The result of subtraction operation is not stored anywhere during a comparison.
9. The instruction that converts the result in an unpacked decimal digits is
a) AAA
b) AAS
c) AAM
d) All of the mentioned
Explanation: All the ASCII adjust instructions give result in unpacked decimal form and so are called as “Unpacked BCD arithmetic instructions”.
10. Which of the following is a mnemonic?
a) ADD
b) ADC
c) AAA
d) ADD & ADC
Explanation: AAA is a mnemonic. It doesn’t have either a source or destination operand.
11. The instruction in which adjustment is made before performing the operation is
a) AAA
b) AAS
c) AAM
d) AAD
Explanation: The AAD instruction converts two unpacked BCD digits in AH and AL to the equivalent binary number in AL. This adjustment must be made before dividing the two unpacked BCD digits.
Explanation: This instruction performs conversion operation.
13. The instruction that is used to convert the result of the addition of two packed BCD numbers to a valid BCD number is
a) DAA
b) DAS
c) AAA
d) AAS
Explanation: In this conversion, the result has to be only in AL.
14. The ROR instruction rotates the contents of the destination operand to
a) left
b) right
c) left and then right
d) right and then left
Explanation: ROR stands for Rotate Right without carry. so, the instruction rotates right.
This set of Microprocessors Technical Interview Questions & Answers focuses on “Do’s and Don’ts While Using Instructions”.
1. The logic required for implementing a program can be expressed in terms of
a) flowchart
b) algorithm
c) flowchart & algorithm
d) none of the mentioned
Explanation: The logic required for implementing a program must be visualized clearly which is possible by flowchart and algorithm.
2. The operands, source and destination in an instruction cannot be
a) register, register
b) memory location, memory location
c) memory location, register
d) immediate data, register
Explanation: Only one memory operand can be specified in one instruction.
3. The instruction that is not possible among the following is
a) MOV AX, BX
b) MOV AX, [BX].
c) MOV 55H, BL
d) MOV AL, 55H
Explanation: 8-bit or 16-bit operand cannot be used as a destination operand.
4. The instruction that is not possible among the following is
a) MOV AX, [BX].
b) MOV AX, 5555H
c) MOV AX, [SI].
d) MOV [SI], [DI].
Explanation: Both the operands cannot be memory operands.
5. Both the operands source and destination of an instruction cannot be
a) register, register
b) immediate data, register
c) register, immediate data
d) immediate data, memory location
Explanation: Since destination operand should not be immediate data.
6. The registers that cannot be used as operands for arithmetic and logical instructions are
a) general purpose registers
b) pointers
c) index registers
d) segment registers
Explanation: Segment registers are not allowed as operands for arithmetic and logical instructions.
7. The operands of an instruction cannot be
a) registers
b) memory operands and immediate operands
c) immediate operands
d) memory operands
Explanation: Both the operands should not be immediate operands and memory operands.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Interrupt Cycle of 8086/8088”.
1. If an interrupt is generated from outside the processor then it is an
a) internal interrupt
b) external interrupt
c) interrupt
d) none of the mentioned
Explanation: If an external device or a signal interrupts the processor from outside then it is an external interrupt.
2. If the interrupt is generated by the execution of an interrupt instruction then it is
a) internal interrupt
b) external interrupt
c) interrupt-in-interrupt
d) none of the mentioned
Explanation: The internal interrupt is generated internally by the processor circuit or by the execution of an interrupt instruction.
3. Example of an external interrupt is
a) divide by zero interrupt
b) keyboard interrupt
c) overflow interrupt
d) type2 interrupt
Explanation: Since the keyboard is external to the processor, it is an external interrupt.
4. Example of an internal interrupt is
a) divide by zero interrupt
b) overflow interrupt
c) interrupt due to INT
d) all of the mentioned
Explanation: Since the interrupts occur within the processor itself, they are called internal interrupts.
5. The interrupt request that is independent of IF flag is
a) NMI
b) TRAP
c) Divide by zero
d) All of the mentioned
Explanation: These requests are independent of IF flag.
6. The type of the interrupt may be passed to the interrupt structure of CPU from
a) interrupt service routine
b) stack
c) interrupt controller
d) none of the mentioned
Explanation: After an interrupt is acknowledged, the CPU computes the vector address from the type of the interrupt that may be passed to the internal structure of the CPU from an interrupt controller in case of external interrupts.
7. During the execution of an interrupt, the data pushed into the stack is the content of
a) IP
b) CS
c) PSW
d) All of the mentioned
Explanation: The contents of IP, CS and PSW are pushed into the stack during the execution.
8. After every response to the single step interrupt the flag that is cleared is
a) IF (Interrupt Flag)
b) TF (Trap Flag)
c) OF (Overflow Flag)
d) None of the mentioned
Explanation: If the trap flag is set then the processor enters the single step execution mode. After the execution, the trap flag is cleared.
9. At the end of ISR, the instruction should be
a) END
b) ENDS
c) IRET
d) INTR
Explanation: After the execution of the ISR, the control must go to the previous program (maybe main program) which was being executed. To execute it, IRET is placed at the end of ISR.
10. When the CPU executes IRET,
a) contents of IP and CS are retrieved
b) the control transfers from ISR to main program
c) clears the trap flag
d) clears the interrupt flag
Explanation: When the instruction IRET is executed, the contents of flags, IP and CS which were saved at the stack by the CALL instruction are retrieved to the respective registers.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Semiconductor Memory Interfacing”.
1. The semiconductor memories are organised as __________ dimension(s) of array of memory locations.
a) one dimensional
b) two dimensional
c) three dimensional
d) none
Explanation: The semiconductor memories are organised as two dimensions of an array which consists of rows and columns.
2. If a location is selected, then all the bits in it are accessible using a group of conductors called
a) control bus
b) address bus
c) data bus
d) either address bus or data bus
Explanation: The bits in a selected location are accessible using data bus.
3. To address a memory location out of N memory locations, the number of address lines required is
a) log N (to the base 2)
b) log N (to the base 10)
c) log N (to the base e)
d) log (2N) (to the base e)
Explanation: For n memory locations, log n(to the base of 2) address lines are required. For addressing 4K bytes of memory, 12 address lines are required since log(4KB) =log(4*1024)=log(212)=12.
4. If the microprocessor has 10 address lines, then the number of memory locations it is able to address is
a) 512
b) 1024
c) 2048
d) none
Explanation: Since for n address lines, the number of memory locations able to address is 2^n.
5. In static memory, the upper 8-bit bank of an available 16-bit memory chip is called
a) upper address memory bank
b) even address memory bank
c) static upper memory
d) odd address memory bank
Explanation: In static memory, the upper 8-bit bank is called odd address memory bank.
6. In static memory, the lower 8-bit bank of an available 16-bit memory chip is called
a) lower address memory bank
b) even address memory bank
c) static lower memory bank
d) odd address memory bank
Explanation: In static memory, the lower 8-bit bank is called even address memory bank.
7. In most of the cases, the method used for decoding that may be used to minimise the required hardware is
a) absolute decoding
b) non-linear decoding
c) linear decoding
d) none
Explanation: In general, linear decoding is used to minimise the required hardware.
8. To obtain 16-bit data bus width, the two 4K*8 chips of RAM and ROM are arranged in
a) parallel
b) serial
c) both serial and parallel
d) neither serial nor parallel
Explanation: The two 4K*8 chips of RAM and ROM are arranged in parallel.
9. If (address line) Ao=0 then, the status of address and memory are
a) address is even and memory is in ROM
b) address is odd and memory is in ROM
c) address is even and memory is in RAM
d) address is odd and memory is in RAM
Explanation: If Ao=0 then address is even and is in RAM. If Ao=1 then, address is odd and is in RAM.
10. If at a time Ao and BHE(active low) both are zero then, the chip(s) selected will be
a) RAM
b) ROM
c) RAM and ROM
d) ONLY RAM
Explanation: If at a time Ao and BHE(active low) both are zero, then both RAM and ROM are selected.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Modes of Operation of 8255”.
1. In the I/O mode, the 8255 ports work as
a) reset pins
b) set pins
c) programmable I/O ports
d) only output ports
Explanation: In the I/O mode, the 8255 ports work as programmable I/O ports.
2. In BSR mode, only port C can be used to
a) set individual ports
b) reset individual ports
c) set and reset individual ports
d) programmable I/O ports
Explanation: In BSR (Bit Set-Reset) Mode, port C can be used to set and reset its individual port bits.
3. The feature of mode 0 is
a) any port can be used as input or output
b) output ports are latched
c) maximum of 4 ports are available
d) all of the mentioned
Explanation: In mode 0, any port can be used as input or output and output ports are latched.
4. The strobed input/output mode is another name of
a) mode 0
b) mode 1
c) mode 2
d) none
Explanation: In this mode, the handshaking signals control the input or output action of the specified port.
5. If the value of the pin STB (Strobe Input) falls to low level, then
a) input port is loaded into input latches
b) input port is loaded into output latches
c) output port is loaded into input latches
d) output port is loaded into output latches
Explanation: If the value of the pin STB (Strobe Input) falls to low level, the input port is loaded into input latches.
6. The signal, SLCT in the direction of signal flow, OUT, indicates the selection of
a) Control word register
b) CPU
c) Printer
d) Ports
Explanation: This signal indicates that the printer is selected.
7. The pulse width of the signal INIT at the receiving terminal must be more than
a) 10 microseconds
b) 20 microseconds
c) 40 microseconds
d) 50 microseconds
Explanation: The pulse width of the signal must be more than 50microseconds at the receiving terminal.
8. The level of the signal ERROR(active low) becomes ‘low’ when the printer is in
a) Paper end state
b) Offline state
c) Error state
d) All of the mentioned
Explanation: The level of the signal ERROR(active low) becomes ‘low’ when the printer is in the Paper end state, Offline state and Error state.
9. The signals that are provided to maintain proper data flow and synchronization between the data transmitter and receiver are
a) handshaking signals
b) control signals
c) input signals
d) none
Explanation: Handshaking signals maintain proper data flow and synchronization.
10. The feature of mode 2 of 8255 is
a) single 8-bit port is available
b) both inputs and outputs are latched
c) port C is used for generating handshake signals
d) all of the mentioned
Explanation: In mode 2 of 8255, a single 8-bit port is available i.e group A.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Programmable Interval Timer 8254”.
1. The number of counters that are present in the programmable timer device 8254 is
a) 1
b) 2
c) 3
d) 4
Explanation: There are three counters that can be used as either counters or delay generators.
2. The operation that can be performed on control word register is
a) read operation
b) write operation
c) read and write operations
d) none
Explanation: The control word register can only be written and cannot be read.
3. The mode that is used to interrupt the processor by setting a suitable terminal count is
a) mode 0
b) mode 1
c) mode 2
d) mode 3
Explanation: Mode 0 is also called as an interrupt on the terminal count.
4. In mode 2, if N is loaded as the count value, then after (N-1) cycles, the output becomes low for
a) 1 clockcycle
b) 2 clockcycles
c) 3 clockcycles
d) 4 clockcycles
Explanation: After (N-1) cycles, the output becomes low for only 1 clockcycle. If the count N is reloaded and again the output becomes high and remains so for (N-1) clock pulses.
5. The generation of a square wave is possible in the mode
a) mode 1
b) mode 2
c) mode 3
d) mode 4
Explanation: When the count N loaded is even, then for half of the count, the output remains high and for the remaining half it remains low. If the count loaded is odd, the first clock pulse decrements it by 1 resulting in an even count value.
6. In control word register, if SC1=0 and SC0=1, then the counter selected is
a) counter 0
b) counter 1
c) counter 2
d) none
Explanation: SC denotes select counter.
7. In control word format, if RL1=1, RL0=1 then the operation performed is
a) read/load least significant byte only
b) read/load most significant byte only
c) read/load LSB first and then MSB
d) read/load MSB first and then LSB
Explanation: To access 16 bit, first LSB is loaded first, and then MSB.
8. If BCD=0, then the operation is
a) decimal count
b) hexadecimal count
c) binary count
d) octal count
Explanation: If BCD=0 then hexadecimal count. If BCD=1, then the operation is BCD count.
9. The counter starts counting only if
a) GATE signal is low
b) GATE signal is high
c) CLK signal is low
d) CLK signal is high
Explanation: If the GATE signal is enabled, then the counter starts counting.
10. The control word register contents are used for
a) initializing the operating modes
b) selection of counters
c) choosing binary/BCD counters
d) all of the mentioned
Explanation: The control word register contents are used for
i) initializing the operating modes (mode 0-mode 4)
ii) selection of counters (counter0-counter2)
iii) choosing binary or BCD counters
iv) loading of the counter registers.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “the Keyboard/Display Controller 8279”.
1. The registers that store the keyboard and display modes and operations programmed by CPU are
a) I/O control and data buffers
b) Control and timing registers
c) Return buffers
d) Display address registers
Explanation: The control and timing register to store the keyboard and display modes and other operations programmed by CPU.
2. The sensor RAM acts as 8-byte first-in-first-out RAM in
a) keyboard mode
b) strobed input mode
c) keyboard and strobed input mode
d) scanned sensor matrix mode
Explanation: In this mode, each key code of the pressed key is entered in the order of the entry, and in the meantime, read by the CPU, till the RAM becomes empty.
3. The registers that hold the address of the word currently being written by the CPU from the display RAM are
a) control and timing register
b) control and timing register and timing control
c) display RAM
d) display address registers
Explanation: The display address registers holds the address of the word currently being written or read by the CPU to or from the display RAM.
4. When a key is pressed, a debounce logic comes into operation in
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
Explanation: In scanned keyboard mode with 2 key lockout mode of operation, when a key is pressed, a debounce logic comes into operation. During the next two scans, other keys are checked for closure and if no other key is pressed then the first pressed key is identified.
5. The mode that is programmed using “end interrupt/error mode set command” is
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
Explanation: The scanned keyboard special error mode is programmed using end interrupt/error mode set command. This mode is valid only under the N-key rollover mode.
6. When a key is pressed, the debounce circuit waits for 2 keyboard scans and then checks whether the key is still depressed in
a) scanned keyboard special error mode
b) scanned keyboard with N-key rollover
c) scanned keyboard mode with 2 key lockout
d) sensor matrix mode
Explanation: In this mode, When a key is pressed, the debounce circuit waits for 2 keyboard scans and then checks whether the key is still depressed. If it is still depressed, the code is entered in FIFO RAM.
7. The data that is entered from the left side of the display unit is of
a) left entry mode
b) right entry mode
c) left and right entry modes
d) none
Explanation: The data that is entered from the left side of the display unit is of left entry mode, as in a type-writer the first character typed appears at the left-most position, while the subsequent characters appear successively to the right of the first one.
8. The FIFO status word is used to indicate the error in
a) keyboard mode
b) strobed input mode
c) keyboard and strobed input mode
d) scanned sensor matrix mode
Explanation: Overrun error occurs when an already full FIFO has attempted an entry. Underrun error occurs when an empty FIFO read is attempted.
9. The flag that increments automatically after each read or write operation to the display RAM is
a) IF
b) RF
c) AI
d) WF
Explanation: AI refers to auto increment flag.
10. If any change in sensor value is detected at the end of a sensor matrix scan, then the IRQ line
a) goes low
b) goes high
c) remains unchanged
d) none
Explanation: In sensor matrix mode, the IRQ line goes high, if any change in sensor value is detected at the end of a sensor matrix scan or the sensor RAM has a previous entry to be read by the CPU.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “DMA Controller 8257”.
1. In direct memory access mode, the data transfer takes place
a) directly
b) indirectly
c) directly and indirectly
d) none of the mentioned
Explanation: In direct memory access mode, the data may transfer directly without the interference from the CPU.
2. In 8257 (DMA), each of the four channels has
a) a pair of two 8-bit registers
b) a pair of two 16-bit registers
c) one 16-bit register
d) one 8-bit register
Explanation: The DMA supports four channels, and each of the channels has a pair of two 16-bit registers, namely DMA address register and a terminal count register.
3. The common register(s) for all the four channels of 8257 is
a) DMA address register
b) Terminal count register
c) Mode set register and status register
d) None of the mentioned
Explanation: The two common registers for all the four channels of DMA are mode set register and status register.
4. In 8257 register format, the selected channel is disabled after the terminal count condition is reached when
a) Auto load is set
b) Auto load is reset
c) TC STOP bit is reset
d) TC STOP bit is set
Explanation: If the TC STOP bit is set, the selected channel is disabled after the terminal count condition is reached, and it further prevents any DMA cycle on the channel.
5. The IOR (active low) input line acts as output in
a) slave mode
b) master mode
c) master and slave mode
d) none of the mentioned
Explanation: The IOR (active low) is an active low bidirectional tristate input line, that acts as input in the slave mode, and acts as output in the master mode. In master mode, this signal is used to read data from a peripheral during a memory write cycle.
6. The IOW (active low) in its slave mode loads the contents of a data bus to
a) 8-bit mode register
b) upper/lower byte of 16-bit DMA address register
c) terminal count register
d) all of the mentioned
Explanation: In its slave mode, the IOW (active low) loads the contents of a data bus to 8-bit mode register, upper/lower byte of 16-bit DMA address register or terminal count register.
7. The pin that disables all the DMA channels by clearing the mode registers is
a) MARK
b) CLEAR
c) RESET
d) READY
Explanation: The RESET pin which is asynchronous input disables all the DMA channels by clearing the mode registers, and tristate all the control lines.
8. The pin that requests the access of the system bus is
a) HLDA
b) HRQ
c) ADSTB
d) None of the mentioned
Explanation: The hold request output requests the access of the system bus.
9. The pin that is used to write data to the addressed memory location, during DMA write operation is
a) MEMR (active low)
b) AEN
c) MEMW (active low)
d) IOW (active low)
Explanation: The MEMW (active low) is used to write data to the addressed memory location, during DMA write operation.
10. The pin that strobes the higher byte of the memory address, generated by the DMA controller into the latches is
a) AEN
b) ADSTB
c) TC
d) None of the mentioned
Explanation: The pin ADSTB strobes the higher byte of the memory address, generated by the DMA controller into the latches.
This set of Microprocessors Question Paper focuses on “Programmable DMA Interface 8237 -2”.
1. Each bit in the request register is cleared by
a) under program control
b) generation of TC
c) generation of an external EOP
d) all of the mentioned
Explanation: In the request register, each bit is set or reset under program control or is cleared upon generation of a TC or an external EOP.
2. The register that holds the data during memory to memory data transfer is
a) mode register
b) temporary register
c) command register
d) mask register
Explanation: The temporary register holds the data during memory to memory data transfers. After the completion of the transfer operation, the last word transferred remains in the temporary register, until it is cleared by a reset operation.
3. The register that keeps track of all the DMA channel pending requests and status of their terminal counts is
a) mask register
b) request register
c) status register
d) count register
Explanation: The status register keeps track of all the DMA channel pending requests, and status of their terminal counts. These are cleared upon reset.
4. The pin that clears the command, request and temporary registers, and internal first/last flipflop when it is set is
a) CLEAR
b) SET
c) HLDA
d) RESET
Explanation: A high on the reset pin clears the command, status, request and temporary registers, and also clears the internal first/last flipflop.
5. The DMA request input pin that has the highest priority is
a) DREQ0
b) DREQ1
c) DREQ2
d) DREQ3
Explanation: DREQ0 has the highest priority while DREQ3 has the lowest one. The priorities of the DREQ lines is programmable.
6. When interface 8237 does not have any valid pending DMA request then it is said to be in
a) active state
b) passive state
c) idle state
d) none of the mentioned
Explanation: If 8237 is in idle state, then CPU may program it in this state.
7. To complete a DMA transfer, a memory to memory transfer requires
a) a read from memory cycle
b) a write to memory cycle
c) a read-from and write-to memory cycle
d) none of the mentioned
Explanation: A memory to memory transfer is a two cycle operation and requires a read from and write-to memory cycle, to complete each DMA transfer.
8. In demand transfer mode of 8237, the device stops data transfer when
a) a TC (terminal count) is reached
b) an external EOP (active low) is detected
c) the DREQ signal goes inactive
d) all of the mentioned
Explanation: In demand transfer mode, the device continues transfers till a TC is reached or an external EOP is detected or the DREQ signal goes inactive.
9. The mode of 8237 in which the device transfers only one byte per request is
a) block transfer mode
b) single transfer mode
c) demand transfer mode
d) cascade mode
Explanation: In single mode, the device transfers only one byte per request. For each transfer, the DREQ must be active until the DACK is activated.
10. The transfer of a block of data from one set of memory address to another takes place in
a) block transfer mode
b) demand transfer mode
c) memory to memory transfer mode
d) cascade mode
Explanation: To perform the transfer of a block of data from one set of a memory address to another one, this transfer mode is used.
11. Which of the following command is used to make all the internal registers of 8237 clear?
a) clear first/last flipflop
b) master clear command
c) clear mask register
d) none of the mentioned
Explanation: Using master clear command, all the internal registers of 8237 are cleared, while all the bits of the mask register are set.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Interconnection Topologies”.
1. The memory of a microprocessor serves as
a) storage of individual instructions
b) temporary storage for the data
c) storing common instructions or data for all processors
d) all of the mentioned
Explanation: The memory serves the microprocessor in the same way, whether it is a single microprocessor or a multi microprocessor.
2. In shared bus architecture, the required processor(s) to perform a bus cycle, for fetching data or instructions is
a) one processor
b) two processors
c) more than two processors
d) none of the mentioned
Explanation: In a shared bus architecture, only one processor performs bus cycle to fetch instructions or data from the memory.
3. In multiport memory configuration, the processor(s) that address the multiport memory is(are)
a) 1
b) 2
c) 3
d) many
Explanation: The processors P1 and P2 address a multiport memory, which can be accessed at a time by both the processors.
4. The memory space of a processor that is mapped to other processor/processors and vice-versa is known as
a) multi microprocessor system
b) memory technique
c) bus window technique
d) mapping technique
Explanation: The bus window technique is the correct method of interconnection between the processors.
5. The disadvantage of the bus window technique is
a) both processors must know about bus window
b) both processors must know the address map
c) loss of effective local memory space
d) all of the mentioned
Explanation: The disadvantage of bus window technique is that both processors must know implicitly about the existence of a bus window, its size and the address map. It also results in loss of effective local memory space.
6. Bus switches are present in
a) bus window technique
b) crossbar switching
c) linked input/output
d) shared bus
Explanation: In crossbar switching type of interconnection topology, several parallel data paths are possible. Each node of the crossbar represents a bus switch.
7. Which of the following is not a type of configuration that is based on physical interconnections between the processors?
a) star configuration
b) loop configuration
c) regular topologies
d) incomplete interconnection
Explanation: Based on the physical interconnections between the processors, the configurations are
i) star configuration
ii) loop or ring configuration
iii) complete interconnection
iv) regular topologies
v) irregular topologies.
8. The configuration, in which all the processing elements are
connected to a central switching element, that may be independent
processor via dedicated paths is
a) star
b) loop
c) complete
d) irregular
Explanation: The switching element controls the interconnections between the processing elements.
9. The configuration that is not suitable for a large number of processors is
a) star
b) loop
c) complete
d) regular
Explanation: For a large number of processors, the complete interconnection is impractical due to a large number of interconnection paths.
10. The array processor architecture is an example of
a) star
b) loop
c) complete
d) regular
Explanation: In array processor architecture, the processing elements are arranged in a regular fashion.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “I/O Processor 8089”.
1. The 8089 shares the system bus and memory with the host CPU in
a) tightly coupled configuration
b) loosely coupled configuration
c) tightly and loosely coupled configurations
d) none of the mentioned
Explanation: In a tightly coupled configuration, the 8089 shares the system bus and memory with the host CPU using its RQ (active low) or GT (active low) pins.
2. The 8089 communicates with the host CPU using bus arbiter and controller in
a) tightly coupled configuration
b) loosely coupled configuration
c) tightly and loosely coupled configurations
d) none of the mentioned
Explanation: In a loosely coupled configuration, the 8089 has its own local bus and communicates with the host CPU using bus arbiter and controller.
3. The number of address lines used by the I/O processor in 8089 is
a) 20
b) 12
c) 16
d) 8
Explanation: The 8089 I/O processor uses only 16 address lines, and thus it can address only 64KB of IO space.
4. The IO device that can be interfaced with 8089 is
a) 16-bit IO
b) 8-bit IO
c) 64-bit IO
d) 16-bit and 8-bit IO
Explanation: The 8089 handled IO devices need not have the same data bus width as that of 8089. This enables even 8-bit IO devices to be interfaced easily with 8089.
5. In the 8089 architecture, the address of memory table for channel-2 is calculated by
a) adding 16 to the contents of CCP
b) adding 8 to the contents of CCP
c) adding memory table address of channel-1
d) none of the mentioned
Explanation: The address of the memory table for channel-2 is calculated by adding 8 to the contents of CCP or by adding memory table address for channel-1 to the contents of CCP.
6. Which of the following is not a general purpose register of 8089?
a) GA
b) BC
c) CX
d) MC
Explanation: The registers GA, GB, GC, BC, IX and MC can be used as general purpose registers.
7. The registers that are used as source and destination pointers during DMA operations are
a) GB, GC
b) GC, BC
c) GC, GA
d) GA, GB
Explanation: GA register is used as source and GB as destination pointers during DMA operations.
8. The pin that is used for data transfer control and operation termination signals is
a) SINTR
b) EXT
c) DRQ and EXT
d) RQ (active low) or GT (active low)
Explanation: The DRQ and EXT are used for data transfer control and operation termination signals during DMA operations.
9. The pin that is used to inform the CPU that the previous operation is completed is
a) RQ (active low)
b) GT (active low)
c) DRQ
d) SINTR
Explanation: The SINTR pins are used by the channels either to inform the CPU that the previous operation is over or to ask for its attention or interference if required, before the completion of the task.
10. The current channel status of program status word contains
a) source and destination address widths
b) bus load limit
c) interrupt control and servicing
d) all of the mentioned
Explanation: The program status word contains the current channel status, which contains source and destination address widths, channel activity, interrupt control and servicing, bus load limit and priority information.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Salient Features of 80286”.
1. The 80286 is able to address the physical memory of
a) 8 MB
b) 16 MB
c) 24 MB
d) 64 MB
Explanation: The 80286 with its 24-bit address bus is able to address 16 Mbytes of physical memory.
2. The 80286 is able to operate with the clock frequency of
a) 12.5 MHz
b) 10 MHz
c) 8 MHz
d) all of the mentioned
Explanation: Various versions of 80286 are available that run on 12.5 MHz, 10 MHz and 8 MHz clock frequencies.
3. The management of the memory system required to ensure the smooth execution of the running process is done by
a) control unit
b) memory
c) memory management unit
d) bus interface unit
Explanation: The memory management which is an important task of the operating system is now supported by a hardware unit called a memory management unit.
4. The fetching of the program from secondary memory to place it in physical memory, during the execution of CPU is called
a) mapping
b) swapping in
c) swapping out
d) pipelining
Explanation: Whenever the portion of a program is required for execution by the CPU, it is fetched from the secondary memory and placed in the physical memory. This is called swapping in of the program.
5. The process of making the physical memory free by storing the
portion of program and partial results in the secondary storage called
a) mapping
b) swapping in
c) swapping out
d) pipelining
Explanation: In swapping out, a portion of the program or important partial results required for further execution, may be saved back on secondary storage to make the physical memory free, for further execution of another required portion of the program.
6. The memory that is considered as a large logical memory space, that is not available physically is
a) logical memory
b) auxiliary memory
c) imaginary memory
d) virtual memory
Explanation: To the user, there exists a very large logical memory space, which is actually not available called virtual memory. This does not exist physically in a system. It is however, possible to map a large virtual memory space onto the real physical memory.
7. Memory management deals with
a) data protection
b) unauthorized access prevention
c) segmented memory
d) all of the mentioned
Explanation: The important aspects of memory management are data protection, unauthorized access prevention, and segmented memory.
8. The memory management and protection mechanisms are disabled when the 80286 is operated in
a) normal mode
b) real address mode
c) virtual address mode
d) all of the mentioned
Explanation: In real address mode of 80286, all the memory management and protection mechanisms are disabled.
9. The memory management and protection mechanisms are enabled with advanced instruction set when 80286 is operated in
a) normal mode
b) real address mode
c) virtual address mode
d) all of the mentioned
Explanation: In virtual address mode, 80286 works with all of its memory management and protection capabilities, with the advanced instruction set.
10. The 80286 is an upward object code compatible with 8086 or 8088 when operated in
a) normal mode
b) real address mode
c) virtual address mode
d) real and virtual address mode
Explanation: The 80286 is operated in two modes, namely real address mode and virtual address mode. In both the modes, the 80286 is compatible with 8086/8088.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Protection”.
1. The mechanism to provide protection, that is accomplished with the help of read/write privileges is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions
d) privileged operations
Explanation: The restricted use of segments is accomplished with the help of read/write privileges.
2. The Local descriptor table (LDT) and Global descriptor table (GDT) are present in
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
Explanation: In restricted use of segments i.e. segment load check, the segment usages are restricted by classifying the corresponding descriptors, under LDT and GDT.
3. The mechanism that is accomplished using descriptor usages limitations and rules of privilege check is
a) privileged instruction check
b) operation reference check
c) segment load check
d) none of the mentioned
Explanation: Restricted accesses to segment, also called, operation reference check, is accomplished using descriptor usages limitations, and rules of privilege check.
4. The mechanism that is executed at certain privilege levels,
determined by CPL (Current Privilege Level) and I/O privilege level
(IOPL) is
a) restricted use of segments
b) restricted accesses to segments
c) privileged instructions or operations
d) none of the mentioned
Explanation: The privileged instructions or operations, also called, privileged instruction check, is executed at certain privilege levels, determined by CPL and I/O privilege level(IOPL), as defined by the flag register.
5. If CPL is not of the required privilege level, then the instructions that get affected is
a) IRET
b) POPF
c) IRET and POPF
d) None of the mentioned
Explanation: The IRET and POPF instructions do not perform any of their functions, if CPL is not of the required privilege level.
6. If CPL is greater than zero, then the instruction that remains unaffected is
a) IRET
b) POPF
c) IF
d) IRET and POPF
Explanation: IF remains unaffected if CPL is greater than zero. No exception is generated for this condition.
7. The condition, “CPL not equals to zero” satisfies when executing the instruction
a) LIDT
b) LGDT
c) LTR
d) All of the mentioned
Explanation: The condition, “CPL not equals to zero” satisfies, when executing the instructions, LIDT, LGDT, LTR, LMSW, CTS and HLT.
8. While executing the instruction IN/OUT, the condition of CPL is
a) CPL = 0
b) CPL < IOPL
c) CPL > IOPL
d) All of the mentioned
Explanation: The condition CPL>IOPL exists, when executing the instructions, INs, IN, OUTS, OUT, STI, CLI and LOCK.
9. The instruction at which the exception is generated, but the
processor extension registers contain the address of failing instruction
is
a) LTR
b) INS
c) CTS
d) ESC
Explanation: At the ESC instruction, the exception is generated, but the processor extension registers contain the address of failing instruction.
10. The exception that has no error code on a stack is
a) double exception detected
b) processor extension segment overrun
c) invalid task state segment
d) stack segment overrun
Explanation: The processor extension segment overrun has no error code on the stack.
11. Which of the following is protected mode exception?
a) double exception detected
b) invalid task state segment
c) stack segment overrun
d) all of the mentioned
Explanation: Double exception detected, invalid task state segment, stack segment overrun, processor extension segment overrun, are the protected mode exceptions.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Salient Features of 80386DX”.
1. The 80386DX is a processor that supports
a) 8-bit data operand
b) 16-bit data operand
c) 32-bit data operand
d) all of the mentioned
Explanation: The 80386DX is a 32-bit processor that supports, 8-bit/16-bit/32-bit data operands.
2. The 80386DX has an address bus of
a) 8 address lines
b) 16 address lines
c) 32 address lines
d) 64 address lines
Explanation: The 80386, with its 32-bit address bus, can address up to 4 GB of physical memory.
3. The number of debug registers that are available in 80386, for hardware debugging and control is
a) 2
b) 4
c) 8
d) 16
Explanation: The 80386 offers a set of total eight debug registers DR0-DR7, for hardware debugging and control.
4. The memory management of 80386 supports
a) virtual memory
b) paging
c) four levels of protection
d) all of the mentioned
Explanation: The memory management section of 80386 supports the virtual memory, paging and four levels of protection, maintaining full compatibility with 80286.
5. The 80386 enables itself to organize the available physical memory into pages, which is known as
a) segmentation
b) paging
c) memory division
d) none of the mentioned
Explanation: The concept of paging which is introduced in 80386, enables it to organize the available physical memory into pages of size 4 KB each, under the segmented memory.
6. The 80386 consists of
a) on-chip address translation cache
b) instruction set of predecessors with upward compatibility
c) virtual memory space of 64TB
d) all of the mentioned
Explanation: The 80386 has on-chip address translation cache, and the instruction set is upward compatible with all its predecessors.
7. 80386DX is available in a grid array package of
a) 64 pin
b) 128 pin
c) 132 pin
d) 142 pin
Explanation: The 80386DX is available in a 132-pin grid array package.
8. The operating frequency of 80386DX is
a) 12 MHz and 20 MHz
b) 20 MHz and 33 MHz
c) 32 MHz and 12 MHz
d) all of the mentioned
Explanation: The operating frequency of 80386DX is 20MHz and 33 MHz.
9. The 80386 in its protected mode, in its virtual mode of operation, can run the applications of
a) 8086
b) 80286
c) 80287
d) 80387
Explanation: The 80386 can run the applications under protected mode, in its virtual 8086 mode of operation.
10. The 80386 in protected mode, supports all software written for
a) 8086 and 80287
b) 80286 and 80287
c) 80287 and 80387
d) 80286 and 8086
Explanation: The 80386 in protected mode, supports all software written for 8086 and 80286 (to be executed under the control of memory management and protection abilities of 80386).
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Segmentation”.
1. The bit that indicates whether the segment has been accessed by the CPU or not is
a) base address
b) attribute bit
c) present bit
d) granular bit
Explanation: The accessed bit or attribute bit (A) indicates whether the segment has been accessed by the CPU or not.
2. The TYPE field of a descriptor is used to find the
a) descriptor type
b) segment type
c) descriptor and segment type
d) none
Explanation: The type field decides the descriptor type and hence the segment type.
3. If the segment descriptor bit, S=0, then the descriptor is
a) data segment descriptor
b) code segment descriptor
c) system descriptor
d) all of the mentioned
Explanation: If S=0, then system descriptor. If S=1, then code or data segment descriptor.
4. The bit that indicates whether the segment is page addressable is
a) base address
b) attribute bit
c) present bit
d) granularity bit
Explanation: The granularity bit indicates whether the segment is page addressable.
5. If the Default operation size bit, D=1, the code segment operation size selected is
a) 8-bit
b) 16-bit
c) 32-bit
d) 64-bit
Explanation: If D=1, the segment selected is 32-bit operand segment, else, it is a 16-bit operand segment.
6. The segment descriptor contains
a) access rights
b) limit
c) base address
d) all of the mentioned
Explanation: The segment descriptors are 8-byte quantities containing access right or attribute bits along with the base and limit of the segments.
7. Which of the following is not a type of segment descriptor?
a) system descriptors
b) local descriptors
c) gate descriptors
d) none
Explanation: The five types of segment descriptors of 80386 are:
1. Code or data segment descriptors
2. System descriptors
3. Local descriptors
4. TSS(task state segment) descriptors
5. Gate descriptors.
8. The limit field of the descriptor is of
a) 10 bits
b) 8 bits
c) 16 bits
d) 20 bits
Explanation: The limit field of the descriptor is of 20 bits.
9. The starting address of the segment in physical memory is decided by
a) physical memory
b) segment descriptors
c) operating system
d) base address
Explanation: The base address that marks the starting address of the segment in physical memory is decided by the operating system and is of 32 bits.
10. The total descriptors that the 80386 can handle is
a) 2K
b) 8K
c) 4K
d) 16K
Explanation: 80386 can handle total 16K descriptors and hence segments.
This set of Microprocessors online test focuses on “Features of 80586 (Pentium), Concepts of Computer Architecture, Branch Prediction”.
1. The salient feature of Pentium is
a) superscalar architecture
b) superpipelined architecture
c) superscalar and superpipelined architecture
d) none of the mentioned
Explanation: The salient feature of Pentium is its superscalar, superpipelined architecture.
2. The number of stages of the integer pipeline, U, of Pentium is
a) 2
b) 4
c) 3
d) 6
Explanation: The Pentium has two integer pipelines, U and V, where each one is a 4-stage pipeline.
3. Which of the following is a cache of Pentium?
a) data cache
b) data cache and instruction cache
c) instruction cache
d) none of the mentioned
Explanation: The Pentium has two separate caches. They are data cache and instruction cache.
4. The speed of integer arithmetic of Pentium is increased to a large extent by
a) on-chip floating point unit
b) superscalar architecture
c) 4-stage pipelines
d) all of the mentioned
Explanation: The Pentium has two integer pipelines, U and V, where each one is a 4-stage pipeline. This enhances the speed of integer arithmetic of Pentium to a large extent.
5. For enhancement of processor performance, beyond one instruction per cycle, the computer architects employ the technique of
a) super pipelined technique
b) multiple instruction issue
c) super pipelined technique and multiple instruction issue
d) none of the mentioned
Explanation: For enhancement of processor performance, beyond one instruction per cycle, the computer architects employ the technique of multiple instruction issue.
6. Which of the following is a class of architecture of MII (multiple instruction issue)?
a) super pipelined architecture
b) multiple instruction issue
c) very small instruction word architecture
d) super scalar architecture
Explanation: The MII architecture may again be classified into two categories:
1. Very long instruction word architecture
2. Superscalar architecture.
7. The compiler reorders the sequential stream of code that is coming from memory into a fixed size instruction group in
a) super pipelined architecture
b) multiple instruction issue
c) very long instruction word architecture
d) super scalar architecture
Explanation: In VLIW processors, the compiler reorders the sequential stream of code that is coming from memory into a fixed size instruction group, and issues them in parallel for execution.
8. The architecture in which the hardware decides which instructions are to be issued concurrently at run time is
a) super pipelined architecture
b) multiple instruction issue
c) very long instruction word architecture
d) superscalar architecture
Explanation: In the superscalar architecture, the hardware decides which instructions are to be issued concurrently at run time.
9. The CPU has to wait until the execution stage to determine whether the condition is met in
a) unconditional branch
b) conditional branch
c) pipelined execution branch
d) none of the mentioned
Explanation: In conditional branch, the CPU has to wait until the execution stage to determine whether the condition is met or not. When the condition satisfies, a branch is to be taken.
10. The memory device that holds branch target addresses for previously executed branches is
a) Tristate buffer
b) RAM
c) ROM
d) Branch target buffer
Explanation: The branch target buffer in Pentium CPU holds branch target addresses for previously executed branches.
11. The branch target buffer is
a) four-way set-associative memory
b) has branch instruction address
c) has destination address
d) all of the mentioned
Explanation: The branch target buffer is a four-way set-associative memory. Whenever a branch is taken, the CPU enters the branch instruction address, and also the destination address in the branch target buffer.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “MMX Instruction Set”.
1. The additional instructions that are designed especially for performing multimedia tasks are known as
a) additional MMX instructions
b) multimedia MMX instructions
c) enhanced MMX instructions
d) none of the mentioned
Explanation: The MMX technology adds 57 new instructions to the instruction set of processors. These instructions are known as enhanced MMX instructions and are designed specifically for performing multimedia tasks.
2. The MMX instruction, EMMS consists of __________ on which it operates.
a) source operand
b) destination operand
c) source and destination operand
d) none of the mentioned
Explanation: The instruction, EMMS, does not have any operand.
3. In all the MMX instructions, the destination operand resides in
a) Memory
b) RAM
c) Either in an MMX register or in memory
d) MMX register
Explanation: In all the MMX instructions, the source operand is found either in an MMX register or in memory, and the destination operand resides in MMX register.
4. For the MMX instructions, the prefix, P, is used to represent the mode of
a) real addressing mode
b) virtual mode
c) packed mode
d) programmable mode
Explanation: In the MMX instructions, if the operands are in the packed mode, the prefix, P, is used to indicate packed data.
5. For the MMX instructions, the suffix, S, is used to represent
a) status
b) saturation
c) signed saturation
d) unsigned saturation
Explanation: For the MMX instructions, the suffix “S” indicates signed saturation, and “US” indicates unsigned saturation, while executing arithmetic computation in saturation mode.
6. The instruction that is used for quadword is
a) PADD
b) PCMPEQ
c) PAND
d) None of the mentioned
Explanation: The instructions, PADD, PCMPEQ and PAND are used for packed byte, word and double word.
7. The instruction, PSUBB, performs subtraction in
a) packed word
b) packed byte
c) packed double word
d) unpacked word
Explanation: The instruction, PSUBB, performs subtraction in a packed byte.
8. The instruction, PCMPGT, is used to compare two data types and check
a) equal to condition
b) less than condition
c) greater than condition
d) equal to and greater than condition
Explanation: The instruction, PCMPGT, compares to check the greater than condition in packed bytes, packed words and packed double words.
9. The instruction that is not operated on quad word is
a) MOV
b) PSLL
c) PSRA
d) All of the mentioned
Explanation: The instruction, PSRA, performs arithmetic shift, right in a single cycle. It supports only the shifting of packed word and double word data types.
10. When the instruction, PMULLW, is performed, then the lower order 16-bits of the 32 bit products are stored in
a) source operand
b) destination operand
c) no storage of lower order
d) either source or destination
Explanation: In the instruction, PMULLW, four 16 X 16 multiplications are performed, and the lower order 16 bits of the 32-bit products are stored in destination.
11. When the instruction, PMULHW, is performed, then the higher order 16-bits of the 32 bit products are stored in
a) source operand
b) destination operand
c) no storage of lower order
d) either source or destination
Explanation: In the instruction, PMULHW, four 16 X 16 multiplications are performed, and the higher order 16 bits of the 32-bit products are stored in destination.
Explanation: PMADDWD is an important multimedia instruction, which multiplies the four signed words of the destination operand, with four signed words of source operand. This results in 32-bit double words which are added, and the result is stored in the higher double word of the destination operand.
13. If the result of PCMPEQ, which is a comparison of two packed data types, is a success, then the mask generated is
a) mask 0s
b) mask 1s
c) mask 2s
d) mask 3s
Explanation: If the result of PCMPEQ, which is a comparison of two packed data types is a success, then the mask 1s is generated, otherwise a mask of 0s is generated, in the destination operand.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Features of Pentium 4, Netburst Microarchitecture For Pentium4 – 1”.
1. The feature of Pentium 4 is
a) works based on NetBurst microarchitecture
b) clock speed ranges from 1.4GHz to 1.7GHz
c) has hyper-pipelined technology
d) all of the mentioned
Explanation: Pentium 4 is based on NetBurst microarchitecture. Clock speed varies from 1.4GHz to 1.7GHz. It has hyper-pipelined technology.
2. Which of the following is not a module of Pentium 4 architecture?
a) front end module
b) execution module
c) control module
d) none
Explanation: Pentium 4 architecture may be viewed having four basic modules.
1. Front end module
2. Out of order execution engine
3. Execution module
4. Memory subsystem module.
3. The front module of Pentium 4 consists of
a) trace cache
b) microcode ROM
c) front end branch predictor
d) all of the mentioned
Explanation: The front module of Pentium 4 contains
1. IA 32 Instruction decoder
2. Trace cache
3. Microcode ROM
4. Front end branch predictor.
4. The unit that decodes the instructions concurrently and translate them into micro-operations is
a) trace cache
b) instruction decoder
c) execution module
d) front end branch predictor
Explanation: The role of instruction decoder is to decode the instructions concurrently and translate them into micro-operations known as micro-ops.
5. In complex instructions, when the instruction needs to be
translated into more than 4 micro-operations, then the decoder transfers
the task to
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
Explanation: In case of complex instructions, when the instruction needs to be translated into more than 4 micro-operations, then the decoder transfers the task to microcode ROM.
6. The unit that does not store the instructions, but the decoded stream of instructions is
a) trace cache
b) front end branch predictor
c) microcode ROM
d) none
Explanation: The trace cache is a special instruction cache because it does not store the instructions, but the decoded stream of instructions.
7. Trace cache can store the micro-ops upto a range of
a) 6 K decoded micro-ops
b) 8 K decoded micro-ops
c) 10 K decoded micro-ops
d) 12 K decoded micro-ops
Explanation: Trace cache can store upto 12K micro-ops. The cache assembles the decoded micro-ops into ordered sequence of micro-ops called traces.
8. The unit that predicts the locations from where the next instruction bytes are fetched is
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
Explanation: The front end branch predictor predicts the locations from where the next instruction bytes are fetched.
9. If complex instructions like interrupt handling, string manipulation appear, then the control from trace cache transfers to
a) microcode ROM
b) front end branch predictor
c) execution module
d) instruction decoder
Explanation: When some complex instructions like interrupt handling, string manipulation appear, then the control from trace cache transfers to microcode ROM.
10. After the micro-ops are issued by the microcode ROM, the control goes to
a) trace cache
b) front end branch predictor
c) execution module
d) instruction decoder
Explanation: After the micro-ops are issued by the microcode ROM, the control goes to Trace cache once again. The micro-ops delivered by the trace cache and the microcode ROM are buffered in a queue in an orderly fashion.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Hyperthreading In Pentium”.
1. Which of the following is a resource sharing strategy that had been investigated by the developers?
a) partitioned resources
b) threshold sharing
c) full sharing
d) all of the mentioned
Explanation: Several resource sharing strategies have been investigated by the developers. Some of these are
1. Partitioned resources
2. Threshold sharing
3. Full sharing.
2. The feature of hyperthreading is
a) simultaneous multithreading
b) switching is not required
c) effective use of processor resources
d) all of the mentioned
Explanation: Hyperthreading used the concept of simultaneous multithreading, where multiple threads can be executed on a single processor without switching.
3. Each logical processor maintains a set of architecture state which consists of
a) general purpose registers
b) machine state register
c) advanced programmed interrupt controller
d) all of the mentioned
Explanation: Each logical processor maintains a set of architecture state which consists of
1. Registers including the general purpose registers
2. The control register
3. Advanced programmed interrupt controller
4. Machine state register.
4. A logical processor may be temporarily stalled for
a) including servicing cache misses
b) handling branch mispredictions
c) waiting for results of previous instructions
d) all of the mentioned
Explanation: A logical processor may be temporarily stalled for a variety of reasons like including servicing cache misses, handling branch mispredictions and waiting for results of previous instructions.
5. The hyperthreading technology automatically involves the
a) decrease of die area
b) increase of die area
c) decrease of die area to half
d) none
Explanation: The hyperthreading technology automatically involves the increase of die area.
6. The instruction that is used when either of the logical processors is idle is
a) HOLD
b) HLDA
c) HALT
d) NONE
Explanation: An optimization may require the use of HALT instruction, when either of the two logical processors is idle.
7. The mode that is available when there is only one software thread to execute is
a) single task mode
b) multi task mode
c) single task and multi task mode
d) dual task mode
Explanation: When there is only one software thread to execute, there are two modes namely single task mode and multi task mode.
8. The HALT instruction is a privileged instruction that can be only used by
a) execution unit
b) operating system
c) control unit
d) memory unit
Explanation: The HALT instruction is a privileged instruction that can be only used by operating system.
9. When the operating system uses HALT instruction on a processor which supports multithreading, the operation moves from
a) Single task to multi task mode
b) ST1 to ST0
c) Multi task to single task mode
d) None
Explanation: When the operating system uses HALT instruction on a processor which supports multithreading, the operation moves from multi tasking mode to single tasking mode.
10. The Xeon TM processor on which hyperthreading technology was first implemented consists of
a) one logical processor per physical processor
b) two logical processor per physical processor
c) three logical processor per physical processor
d) zero logical processor per physical processor
Explanation: The Xeon TM processor on which hyperthreading technology was first implemented consists of two logical processor per physical processor.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Hybrid Architecture -RISC and CISC Convergence, Advantages of RISC, Design Issues of RISC Processors -1”.
1. The disadvantage of CISC design processors is
a) low burden on compiler developers
b) wide availability of existing software
c) complex in nature
d) none
Explanation: Some computers are used in preference to CISC design due to its low burden on compiler developers and wide availability of existing software. But they are complex in nature.
2. The RISC architecture is preferred to CISC because RISC architecture has
a) simplicity
b) efficiency
c) high speed
d) all of the mentioned
Explanation: The RISC architecture is preferred to CISC because RISC architecture is simple, highly efficient and the processors using RISC architecture have high speed.
3. The feature of RISC that is not present in CISC is
a) branch prediction
b) pipelining
c) branch prediction and pipelining
d) none
Explanation: A RISC core allows performance enhancing features, such as branch prediction and pipelining. Traditionally, these have only been possible in RISC designs.
4. The feature of hybrid CISC-RISC architecture is
a) consume a lot of power
b) not applicable to mobile applications
c) processed by RISC core
d) all of the mentioned
Explanation: The CISC-RISC hybrids continue to consume a lot of power and are not best candidates for mobile and embedded applications.
5. Which of the following is an application of RISC architecture by adding more instructions?
a) multimedia applications
b) telecommunication encoding
c) image conversion
d) all of the mentioned
Explanation: By adding more instructions to the RISC architecture, some applications can be run much faster like multimedia applications, telecommunication encoding/decoding, image conversion and video processing.
6. Which of the following processor belongs to hybrid RISC-CISC architecture?
a) Intel Pentium III
b) Intel Itanium 64
c) AMD’s X86-64
d) All of the mentioned
Explanation: The processors, Intel Pentium III, Intel Itanium 64 and AMD’s X86-64 consists of hybrid RISC-CISC architecture.
7. In order to implement complex instructions, CISC architectures use
a) macroprogramming
b) hardwire
c) microprogramming
d) none
Explanation: In order to implement complex instructions, CISC architectures use microprogramming.
8. The advantage of RISC processors is
a) can operate at high clock frequency
b) shorter design cycle
c) simple and fast
d) all of the mentioned
Explanation: The advantages of RISC processors are that they can work at high clock frequency, can be designed, developed and tested more quickly with a high speed.
9. The additional functionality that can be placed on the same chip of RISC is
a) Memory management units
b) Floating point units
c) Memory management and floating point arithmetic units
d) RAM, ROM
Explanation: Several extra functionalities, such as memory management units or floating point arithmetic units, can also be placed on the same chip of RISC.
10. The number of clockcycles that take to wait until the length of the instruction is known in order to start decoding is
a) 0
b) 1
c) 2
d) 3
Explanation: The loading and decoding the instructions in a RISC processor is simple and fast. It is not needed to wait until the length of the instruction is known in order to start the decoding.
This set of Microprocessor Multiple Choice Questions & Answers (MCQs) focuses on “Architecture of 8051”.
1. The register that may be used as an operand register is
a) Accumulator
b) B register
c) Data register
d) Accumulator and B register
Explanation: In some instructions, the Accumulator and B register are used to store the operands.
2. The register that can be used as a scratch pad is
a) Accumulator
b) B register
c) Data register
d) Accumulator and B register
Explanation: B register is used to store one of the operands for multiply and divide instructions. In other instructions, it may just be used as a scratch pad.
3. The registers that contain the status information is
a) control registers
b) instruction registers
c) program status word
d) all of the mentioned
Explanation: The set of flags of program status word contains the status information and is considered as one of the special function registers.
4. Which of the processor’s stack does not contain the top-down data structure?
a) 8086
b) 80286
c) 8051
d) 80386
Explanation: The 8051 stack is not a top-down data structure, like other Intel processors.
5. The architecture of 8051 consists of
a) 4 latches
b) 2 timer registers
c) 4 on-chip I/O ports
d) all of the mentioned
Explanation: The architecture of 8051 consists of 4 latches and driver pairs are allotted to each of the four on-chip I/O ports. It contains two 16-bit timer registers.
6. The transmit buffer of serial data buffer is a
a) serial-in parallel-out register
b) parallel-in serial-out register
c) serial-in serial-out register
d) parallel-in parallel-out register
Explanation: The transmit buffer of serial data buffer is a parallel-in serial-out register.
7. The receive buffer of serial data buffer is a
a) serial-in parallel-out register
b) parallel-in serial-out register
c) serial-in serial-out register
d) parallel-in parallel-out register
Explanation: The serial data register has two buffers. The transmit buffer is a parallel-in serial-out register and receive buffer is a parallel-in serial-out register.
8. The register that provides control and status information about counters is
a) IP
b) TMOD
c) TSCON
d) PCON
Explanation: The registers, TMOD and TCON contain control and status information about timers/counters.
9. The register that provides control and status information about serial port is
a) IP
b) IE
c) TSCON
d) PCON and SCON
Explanation: The registers, PCON and SCON contain control and status information about serial port.
10. The device that generates the basic timing clock signal for the operation of the circuit using crystal oscillator is
a) timing unit
b) timing and control unit
c) oscillator
d) clock generator
Explanation: The oscillator circuit generates the basic timing clock signal for the operation of the circuit using crystal oscillator.
11. The registers that are not accessible by the user are
a) Accumulator and B register
b) IP and IE
c) Instruction registers
d) TMP1 and TMP2
Explanation: The arithmetic operations are performed over the operands held by the temporary registers, TMP1 and TMP2. Users cannot access these temporary registers.
This set of Microprocessors Questions and Answers for Aptitude test focuses on “8051 Instruction Set -2”.
1. If the most significant bit of relative address byte is 1, then the short jump instruction is
a) forward jump
b) back jump
c) either forward or back jump
d) none
Explanation: If the most significant bit of relative address byte is 1, then the short jump instruction is back jump, else it is considered as forward jump.
2. The first byte of an absolute jump instruction consists of
a) 3 LSBs of opcode and 5 MSBs of 11-bit address
b) 5 MSBs of opcode and 3 LSBs of 11-bit address
c) 6 MSBs of opcode and 1 LSB of 11-bit address
d) 5 LSBs of opcode and 3 MSBs of 11-bit address
Explanation: The first byte of an absolute jump instruction consists of 5 LSBs of opcode and 3 MSBs of 11-bit address. The next byte carries the least significant 8 bits of the 11-bit address.
3. The third byte of the long jump instruction is
a) opcode
b) 5 LSBs of opcode
c) higher byte of jump location or subroutine
d) lower byte of jump location or subroutine
Explanation: The third byte of the long jump instruction is a higher byte of jump location or subroutine.
4. The absolute jump instruction is intended mainly for a jump within a memory space of
a) 2 bytes
b) 2 Kbytes
c) 2 Mbytes
d) none
Explanation: The absolute jump instruction is intended mainly for a jump within a memory space of 2 Kbytes.
5. The LJMP instruction is very useful in programming in the external code memory space of
a) 32 MB
b) 64 MB
c) 32 KB
d) 64 KB
Explanation: The LJMP instruction is very useful in programming in the external code memory space of 64 KB.
6. Which of the following is not an unconditional control transfer instruction?
a) JMP
b) RET
c) JNC
d) CALL
Explanation: The instructions, JMP, RET, RETI, CALL are the unconditional control transfer instructions.
7. The conditional control transfer instructions use
a) status flags
b) bits of bit addressable RAM
c) SFRs termed bit
d) all of the mentioned
Explanation: The conditional control transfer instructions use status flags or bits of bit addressable RAM or SFRs termed bit.
8. Which of the following is not a conditional control transfer instruction?
a) JC
b) JBC
c) JNC
d) NONE
Explanation: The instructions, JC, JBC, JNC, JB and JNB are the conditional control transfer instructions.
9. The mnemonic used to perform a subtraction of source with an 8-bit
data and jumps to specified relative address if subtraction is non-zero
is
a) DJNZ
b) CJNE
c) JZ
d) JNC
Explanation: The CJNE instruction perform a subtraction of source with an 8-bit data and jumps to specified relative address only if the result of the subtraction is non-zero, else continues to the next instruction.
10. The mnemonic, JNB is used to jump to the specified relative address only if
a) specified bit=1
b) specified bit=0
c) specified bit is non-recursive
d) none
Explanation: The mnemonic, JNB is used to jump to the specified relative address only if specified bit=1, else continues to the next instruction.
11. The type of operand that is not allowed to use in boolean instructions of 8051 is
a) direct register operands
b) indirect register operands
c) immediate bit
d) none
Explanation: In boolean instructions, the immediate bit is not allowed as an operand.
Explanation: Carry flag(C) is the only allowed destination operand for two operand instructions in boolean instructions.
