VHDL Pune University MCQs
VHDL Pune University MCQs
This set of VHDL Multiple Choice Questions & Answers focuses on “EDA Tools”.
1. What is the full form of VHDL?
a) Verilog Hardware Description Language
b) Very High speed Description Language
c) Variable Hardware Description Language
d) Very high speed Hardware Description Language
Answer: d
Explanation: Most people confuse Verilog Hardware Description Language with VHDL but, VHDL means VHSIC Hardware Description Language where VHSIC is the acronym for Very High Speed Integrated Circuits.
2. What is the basic use of EDA tools?
a) Communication of Electronic devices
b) Fabrication of Electronics hardware
c) Electronic circuits simulation and synthesis
d) Industrial automation
Answer: c
Explanation: EDA expands to Electronic Design Automation and these tools are used for synthesis, implementation and simulation of Electronic circuits on the software itself.
3. After compiling VHDL code with any EDA tool, we get __________
a) Final device
b) FPGA
c) Optimized netlist
d) Netlist
Answer: d
Explanation: After entering the code into any EDA tool, we need to compile the code. When the compilation is complete, then we get the complete netlist of the system designed by using VHDL. After which optimization process is used to optimize the netlist and then by placement and routing we get final Physical device.
4. Which of the following is not an EDA tool?
a) Visual C++
b) Quartus II
c) Xilinx ISE
d) MaxPlus II
Answer: a
Explanation: Quartus II EDA tool is used for Altera CPLD and FPGA devices. Similarly, Xilinx ISE is used for Xilinx CPLD/FPGA devices. MaxPlus is also an advanced EDA tool for Altera CPLDs. Visual C++ is the compiler for C and C++ languages.
5. The process of transforming a design entry information of the circuit into a set of logic equations in any EDA tool is known as _________
a) Simulation
b) Synthesis
c) Optimization
d) Verification
Answer: b
Explanation: Synthesis means to generate netlist, i.e. describing the circuit by the relation between inputs and outputs by using logic equations. Simulation is whereas to check the correctness of VHDL code and Optimization is to optimize the netlist; optimization is performed after the synthesis. Verification similarly uses different EDA tool to perform gate level verification.
6. Place and Route EDA tools are used to take the design netlist and implement the design in the device.
a) True
b) False
Answer: a
Explanation: Place and Route tools are used to take the netlist and implement it on the target device by taking various factors into consideration like Timing constraints and some device information.
7. An Antifuse programming technology is associated with _________
a) CPLDs
b) FPGAs
c) SPLDs
d) ASICs
Answer: b
Explanation: Antifuse technology is used to burn the information, from place and route tools, into appropriate fuses in the FPGAs.
8. Which of the following is not a back end EDA tool?
a) Floor planning tools
b) Placement tools
c) Routing tools
d) Simulators
Answer: d
Explanation: Simulators are the tools which are used at the front end and all other tools are used at the back end.
9. What are the differences between simulation tools and synthesis tool?
a) Simulators are used to check the performance of circuit and Synthesis tools are for the fabrication of circuits
b) Simulators and Synthesis tools works exactly same
c) Simulators are used just to check basic functionality of the circuit and Synthesis tools includes timing constraints and other factors along with simulation
d) Simulation finds the error in the code and Synthesis tool corrects the code
Answer: c
Explanation: Simulators test basic logic and working of the circuit described in the code and Synthesis allows to take timing factor and other factors into consideration while simulation.
10. What is the extension of the netlist file; input to the place and route EDA tools?
a) EIDF
b) SDF
c) TXT
d) CPP
Answer: a
Explanation: EDIF and XNF are the netlist files; whereas SDF is the file of timing information.TXT is the extension of a simple text file and CPP is the C++ source file.
This set of VHDL Questions & Answers for Exams focuses on “Need of HDLs”.
1. In what aspect, HDLs differ from other computer programming languages?
a) No aspect; both are same
b) HDLs describe hardware rather than executing a program on a computer
c) HDLs describe software and not hardware
d) Other computer programming languages have more complexity
Answer: b
Explanation: HDLs are used to describe hardware for any electronic circuit or system; whereas other computer programming languages execute a program on the computer itself.
2. Which of the following HDLs are IEEE standards?
a) VHDL and Verilog
b) C and C++
c) Altera and Xilinx
d) Quartus II and MaxPlus II
Answer: a
Explanation: VHDL and Verilog are the only two HDLs endorsed by IEEE. C andC++ are not HDLs. Altera and Xilinx are devices on which these HDLs can be used. Quartus II and MaxPlus II are the platforms for simulation of hardware described by HDLs.
3. Why we needed HDLs while having many traditional Programming languages?
a) Traditional programming languages are complex
b) HDLs are complementary to traditional programming languages to complete the design process
c) Some characteristics of digital hardware couldn’t be captured by traditional languages
d) HDLs offer more complexity than traditional programming languages.
Answer: c
Explanation: Digital systems are very complex and this complexity is increasing day by day. Some characteristics like propagation delay, concurrent processing and interconnection of parts can’t be captured with traditional languages.
4. An HDL can’t describe Hardware at Gate level as well as switch level?
a) True
b) False
Answer: b
Explanation: An HDL supports the hierarchical design process. It can describe the circuit or hardware at every possible level, whether it is gate level or switch level or RTL level.
5. Why do we need concurrent processing for describing digital systems in HDLs?
a) Faster processing than conventional programming languages
b) Concurrent processing is easier than sequential processing
c) It allows taking timing constraints into consideration
d) Complexity of digital systems needs concurrent processing
Answer: d
Explanation: Due to the complexity of digital circuits, we need to process all the instructions at the same time. For example, current can flow in the two branches at the same time which can affect the output of the system, if sequentially processed.
6. An ASIC can be correctly designed by using programming languages like C or Assembly.
a) True
b) False
Answer: b
Explanation: By using HDL, we specify what we need. We can optimize the circuit by using HDLs. ASIC is a very complex which may consist of millions of transistors. So, we need concurrent execution first of all. Apart from that, we need timing information and other complex features of the digital system too.
7. VHDL is based on which of the following programming languages?
a) ADA programming language
b) C
c) Assembly
d) PHP
Answer: a
Explanation: The syntax and whole structure of VHDL code is based upon ADA programming language whereas Verilog HDL finds its origin from C language.
8. What is the advantage of using VHDL instead of any other HDL?
a) Week typing
b) Based on ADA
c) Portability
d) Easy to code
Answer: c
Explanation: A circuit specified in VHDL can be implemented in different chips and is compatible with CAD tools provided by all companies. Therefore, without any modification, we can use VHDL code anywhere. This is the biggest advantage because digital circuit technology changes rapidly.
9. Which of the following is a characteristic of VHDL?
a) Case sensitive
b) Use of simple data types
c) Based on C programming language
d) Strongly typed language
Answer: d
Explanation: VHDL is a strongly typed language i.e. we have to write a long code to define operations.
10. Which of the following is a characteristic of Verilog HDL?
a) Strongly typed language
b) Case sensitive
c) Better library
d) Not portable
Answer: b
Explanation: Verilog HDL is a case sensitive language which means ‘a’ and ‘A’ means different if you are coding in Verilog.
This set of VHDL Multiple Choice Questions & Answers focuses on “Common Terms used in VHDL”.
1. Which of the following is the basic building block of a design?
a) Architecture
b) Entity
c) Process
d) Package
Answer: b
Explanation: Entity is the basic building block; all the information regarding input and output of the circuit to be designed is declared in Entity.
2. A package in VHDL consists of _________
a) Commonly used architectures
b) Commonly used tools
c) Commonly used data types and subroutines
d) Commonly used syntax and variables
Answer: c
Explanation: Package is a collection of all the commonly used data types and subroutines so that programmers can easily use them in their design without defining the same functions again and again.
3. Complete description of the circuit to be designed is given in _________
a) Architecture
b) Entity
c) Library
d) Configurations
Answer: a
Explanation: Architecture completely describes the circuit; while entity describes just the input and output of the design. Architecture may describe the behavior of the circuit or its structure.
4. An entity can have more than one architecture.
a) True
b) False
Answer: a
Explanation: Yes, An entity can have more than one architecture. One may define its behaviour and other may define its structure or dataflow. But, the converse of this statement is not true i.e. One architecture can’t define more than one entities.
5. What is the use of the Configuration statement?
a) To configure the components exactly in design
b) To complete the design process by adding libraries
c) To add more than one entities into a single architecture
d) To add some component in any entity architecture pair
Answer: d
Explanation: Configuration statement is used to bind any component instance with entity architecture pair. It is used to describe the behavior, which is used in almost each entity.
6. In VHDL, Bus is a type of ________
a) Signal
b) Constant
c) Variable
d) Driver
Answer: a
Explanation: Bus is a special kind of signal. It may have its drivers turned off.
7. What is the use of Generics in VHDL?
a) To turn on and off the drivers
b) To pass information to the entity
c) To describe architecture
d) To divide code into small processes
Answer: b
Explanation: Generics are used to pass the information to entity through parameters. In short, Generics are parameters which passes information to entity. For example, entity has variables for rise time and fall time delay; then the values for both delays can be passed by using Generics.
8. Driver can be seen as a _______ of the signal.
a) Part
b) Type
c) Final value
d) Source
Answer: d
Explanation: Driver is a source on the signal. All of the signals are driven by their Drivers. Any signal may have more than one driver too.
9. Predefined data for an VHDL object is called ________
a) Generic
b) Constant
c) Attribute
d) Library
Answer: c
Explanation: Attribute is the predefined datatype associated with any VHDL object. For example, operating temperature of any device will be its attribute.
10. A process is the basic unit of execution in VHDL.
a) True
b) False
Answer: a
Explanation: All the operations in the VHDL description are divided into processes during simulation and therefore, Process is the basic unit of execution.
11. Which of the following describes the structure of VHDL code correctly?
a) Library Declaration; Entity Declaration; Architecture Declaration; Configurations
b) Entity Declaration; Configuration; Library Declaration; Architecture Declaration
c) Configuration; Library Declaration; Entity Declaration; Architecture Declaration
d) Library Declaration; Configuration; Entity Declaration; Architecture Declaration
Answer: a
Explanation: In any VHDL code, first of all, we have to define libraries and packages we want to use. After Library Declaration part, Entities are declared. When Entities are created, then only we can describe its architecture. Last part in any VHDL code is Configuration.
12. Which of the following statement is true?
a) Package is a collection of Libraries
b) Library is a collection of Packages
c) Entity is a collection of Packages
d) Architecture is a collection of Entities
Answer: b
Explanation: A library consists of many packages which in turn is a collection of data types and subroutines. Entity is a collection of signals and variables and architecture describes the behavior or structure of Entity.
13. Which of the following is used at the end of a statement?
a) ;
b) —
c) _
d) No sign is used at the end of statement
Answer: a
Explanation: Semicolon is the sign used at the end of any statement. Double hyphen is used for writing a comment which means wherever we have a sign of double hyphen, the simulator will skip that line and start compiling from the next line.
14. Which of the following is correctly declared library for VHDL code?
a)
LIBRARY library_name;
USE package_name.parts;
b)
LIBRARY package_name.parts;
LIBRARY library_name;
c)
USE library_name;
LIBRARY library_name.package_name.parts
d)
LIBRARY library_name;
USE library_name.package_name.parts
Answer: d
Explanation: Library declaration is completed in two lines. First line declares the library and in second line we use ‘USE’ clause to define the package name we want to use from the respective library and the parts we want to use. For example, LIBRARY ieee; USE ieee.std_logic_1164.all; In this declaration, ieee is library and std_logic_1164 package is used; all in package part section specifies that all parts of package are used.
15. One can’t use more than one library in the VHDL code.
a) True
b) False
Answer: b
Explanation: There is no restriction on the number of libraries we want to use. One can define more than one library in VHDL code.
This set of Advanced VHDL Questions and Answers focuses on “Entity and Its Declaration”.
1. Which of the following is not defined by the entity?
a) Direction of any signal
b) Names of signal
c) Different ports
d) Behavior of the signals
Answer: d
Explanation: Entity specifies the name of the entity, the ports of the entity and all the information related to that entity. All designs are created using one or more entities. Declaration of ports in an entity includes the name of signals and there directions.
2. Which of the following can be the name of an entity?
a) NAND
b) Nand_gate
c) Nand gate
d) AND
Answer: b
Explanation: The name of entity can be basically any name, except VHDL reserved words. NAND is reserved for nand operation and same applies for AND. The name of entity can’t contain any space character. Therefore, only option b is the only legal word.
3. Which of the following is correct syntax for entity declaration?
a)
ENTITY entity_name IS
PORT( signal_names : signal_modes;
signal_names : signal_modes);
END entity_name;
b)
ENTITY entity_name
PORT( signal_names : signal_modes;
signal_names : signal_modes);
END ENTITY;
c)
ENTITY entity_name IS
PORT port_name
( signal_names : signal_modes signal_type;
signal_names : signal_modes signal_type);
END entity_name;
d)
ENTITY entity_name
PORT port_name
(signal_names : signal_modes;
signal_names : signal_modes);
END ENTITY;
Answer: a
Explanation: The correct syntax for declaring an entity block starts with reserve word ENTITY followed by name of entity and the next is reserve word IS. Name of entity can contain letters, numbers and underscore character. After this, PORT declaration is used. PORT declaration is used to declare the interface signals for the entity and to assign mode and type of data. The declaration is completed by using END operator and the entity name.
4. Refer to the VHDL code given below, how many input-output pins are there in MUX entity?
ENTITY mux IS
Port ( a,b : IN STD_LOGIC;
Y : OUT STD_LOGIC);
END mux;
a) 5
b) 4
c) 3
d) 2
Answer: c
Explanation: In the given declaration, entity has 3 I/O pins. The signals a and b are Input signals and y is the output signal. So, we can say that the declaration is for 2:1 MUX. In this way, we can find the number of I/O pins from the entity declaration.
5. The entity name ‘xyz’ and ‘XYZ’ will be treated the same.
a) True
b) False
Answer: a
Explanation: VHDL is a strongly typed language which means that there are very strict rules regarding the data types. But, there is no difference between names of entity. VHDL is not case sensitive therefore, ‘xyz’ and ‘XYZ’ are same.
6. Which of the following mode of the signal is bidirectional?
a) IN
b) OUT
c) INOUT
d) BUFFER
Answer: c
Explanation: INOUT is the only bidirectional mode for any signal. IN, OUT and BUFFER are unidirectional mode since they specifies the type to be either input or output. INOUT can be used as both an input to an entity and as an output of the entity. We can read as well as assign the value for INOUT type signal.
7. In an assignment statement, OUT signal can be used only to the ___________
a) Left of <= operator
b) Right of <= operator
c) Any side of <= operator
d) Right of := operator
Answer: a
Explanation: OUT signal is used to take an output from any entity. Therefore, we can assign it any value but can’t read any value from this type of signal. So, in an assignment statement, OUT type signal can be used on the left side of <= operator.
8. On which side of assignment operator, we can use the IN type signal?
a) Left
b) Right
c) Both
d) Can’t be used
Answer: b
Explanation: IN signal is for input only. We can read the value from IN signal. Therefore, it can be placed only on the right side of assignment.
9. What is the difference between OUT and BUFFER?
a) BUFFER can’t be used inside the entity for reading the value and OUT can be
b) BUFFER can only be read whereas OUT can only be assigned a value
c) BUFFER can be read as well as assigned a value but OUT can only be assigned
d) Both are same
Answer: c
Explanation: BUFFER is a unidirectional mode used as an output from the entity. But, the value of BUFFER can be used inside the entity i.e. it can appear on both sides of assignment operator whereas the value of OUT can’t be used inside the entity and can appear on the left side of assignment operator.
10. GENERICs are not declared in the entity.
a) True
b) False
Answer: b
Explanation: The declaration of GENERICs is also done in the entity itself. It is used to declare the constants that can be used to control the structure of behavior of the entity. The Generics are declared before port declarations.
11. Which of the following is an entity declared for a full adder?
a)
ENTITY full_adder IS
PORT(a, b, c : IN BIT;
s, co : OUT BIT);
END full_adder;
b)
ENTITY full_adder IS
PORT (a ,b : IN BIT;
s, c : OUT BIT);
END full_adder;
c)
ENTITY full_adder
PORT(a, b, c : IN BIT;
s, co : OUT BIT);
END full_adder;
d)
ENTITY full_adder IS
PORT (a, b, c, s, co : BIT);
END full_adder;
Answer: a
Explanation: A full adder has three inputs and two outputs. Inputs are two bits to be added and some carry. Outputs are sum and carry. Therefore, option a shows the correct declaration of entity full_adder. In this, a and b are the bits to be added and c is the input carry whereas, s is the sum output and co is the carry output.
12. How to control the structure and timing of the entity can be changed?
a) By using TIME variable in the entity
b) By changing the entity declaration from time to time
c) By using some special code
d) By using GENERICS
Answer: d
Explanation: The structure and timing constraints can be changed by declaring some constant using GENERICS declaration. For example, in the full adder example, number of bits to be added can be declared as array with its size N. this N can be declared as a constant in the GENERIC declaration part of entity. By changing N only, one can change number of bits for the addition.
13. Which of the following can have more than one driver?
a) IN
b) OUT
c) INOUT
d) BUFFER
Answer: c
Explanation: INOUT is the only bidirectional signal. This mode can have more than one driver. Therefore, INOUT can be driven by more than one drivers. All other modes like IN, OUT, BUFFER can have only one driver.
14. Which of the following is the default mode for a port variable?
a) IN
b) OUT
c) INOUT
d) BUFFER
Answer: a
Explanation: IN is the default mode for a port variable. If the mode of any signal is not specified in the port declaration, then it is considered as IN type signal. All other types are needed to be specified at the time of declaration.
This set of VHDL Multiple Choice Questions & Answers focuses on “Architecture”.
1. What does the architecture of an entity define?
a) External interface
b) Internal functionality
c) Ports of the entity
d) Specifications
Answer: b
Explanation: Basically, entity describes the interface to the VHDL model and its architecture describes the internal view of that entity. It describes the functionality and contains the statements which describe the behavior of entity.
2. Which of the following is the correct syntax for architecture declaration and definition?
a)
ARCHITECTURE architecture_type OF entity_name IS
Declarations_for_architecture;
BEGIN
Code;
….
END architecture_name;
b)
ARCHITECTURE architecture_name OF entity_name IS
BEGIN
Declarations_for_architecture;
Code;
….
END architecture_name;
c)
ARCHITECTURE architecture_type OF entity_name IS
BEGIN
Declarations_for_architecture;
Code;
….
END architecture_type;
d)
ARCHITECTURE architecture_name OF entity_name IS
Declarations_for_architecture
BEGIN
Code;
….
END architecture_name;
Answer: d
Explanation: Architecture has two parts which are declarative part and the code part containing concurrent and sequential statements. Declaration part is optional but the code part is essential. The declaration of architecture is started with the keyword ARCHITECTURE followed by its name and then the name of entity. Then, the declaration part is used to declare and then BEGIN keyword is used to start the code part.
3. What does the declarative part of architecture contain?
a) Declaration of another entity
b) Declaration of libraries and packages
c) Declaration of local signals, constants or subprograms
d) Declaration of Architecture type
Answer: c
Explanation: Declarative part is the optional part of architecture definition. In this section, the local signals, constants, variables or subprograms are declared which are needed in the architecture. The scope of variables declared in this region is limited to the architecture only.
4. The statements in between the keyword BEGIN and END are called _______
a) Concurrent statements
b) Netlist
c) Declaration statement
d) Entity function
Answer: a
Explanation: The proper word for the statements between BEGIN and END is Concurrent statements since they are executed concurrently. The code in between BEGIN and END describes the functionality or structure of the entity. BEGIN keyword specifies the starting of code.
5. Which of the following is the correct architecture for a simple Nand gate?
a)
ARCHITECTURE my_arch OF nand_gate IS
BEGIN
x <= a NAND b;
END my_arch;
b)
BEGIN
ARCHITECTURE my_arch OF nand_gate IS
x <= a NAND b;
END behavioral;
c)
BEGIN
ARCHITECTURE behavioral OF nand_gate IS
x <= a NAND b;
END my_arch;
d)
ARCHITECTURE nand OF nand_gate IS
BEGIN
x <= a NAND b;
END nand;
Answer: a
Explanation: For correct syntax, the word ARCHITECTURE must be followed by the name of architecture which may not contain the reserved words. After which BEGIN keyword is used to show the beginning of code section of the architecture and at last END keyword is used followed by name of architecture. Therefore, only option a is correct architecture of NAND gate explaining its functionality.
6. Which of the following can be the name of an architecture?
a) arch 1
b) 1arch
c) arch_1
d) architecture
Answer: c
Explanation: The name of architecture is its identifier and hence, it will follow the same rule as that of identifiers. It may contain alphanumeric characters and underscore character starting with alphabet always. Also, name can’t be same as any of the reserved word of VHDL.
7. An entity can’t be described by more than one architecture.
a) True
b) False
Answer: b
Explanation: It is false that an entity can’t have two or more architectures. An entity can be described by using more than one architecture. For an instance, one can define its behavior and another can explain its structure. However, the converse of the statement is not true, one architecture can describe only one entity.
8. Which of the following can’t be declared in the declaration part of the architecture?
a) Signals
b) Subprograms
c) Components
d) Libraries
Answer: d
Explanation: In the declaration part of architecture, the local data objects and subprograms are defined which can be used in the architecture only. However, a library contains packages which are generally used in every VHDL model and they are declared globally at the starting of VHDL code.
9. It is not possible to declare an entity after declaring its architecture.
a) True
b) False
Answer: a
Explanation: An entity is required first to describe its architecture. First of all, entity create an external interface of the system after which we can describe the internal view of entity. Until there is no entity, architecture declaration is not possible.
10. Which of the following statements execute faster?
a) Sequential statements
b) Concurrent statements
c) Declaration statements
d) Loop statements
Answer: b
Explanation: Concurrent statements execute faster than sequential statements. Sequential statements are those which are executed one after another whereas concurrent statements execute concurrently or simultaneously. Therefore, concurrent are faster.
This set of VHDL Interview Questions and Answers focuses on “Data Objects and Types”.
1. SIGNED and UNSIGNED data types are defined in which package?
a) std_logic_1164 package
b) std_logic package
c) std_logic_arith package
d) standard package
Answer: c
Explanation: SIGNED and UNSIGNED data types are defined in the std_logic_arith package of the IEEE library. These data types are mainly intended for arithmetic operations. This is why they are defined in the arithmetic package.
2. What is the correct method to declare a SIGNED type signal ‘x’?
a) SIGNAL x : IN SIGNED
b) SIGNAL x : IN SIGNED
c) SIGNAL x : IN SIGNED
d) SIGNAL x : IN SIGNED_VECTOR
Answer: c
Explanation: Unlike BIT and STD_LOGIC types; SIGNED and UNSIGNED follow the syntax similar to BIT_VECTOR and STD_LOGIC_VECTOR. Also, IN and OUT are just to specify the direction of signal.
3. An UNSIGNED type is always greater than zero.
a) True
b) False
Answer: a
Explanation: In SIGNED and UNSIGNED, SIGN word refers to the positive or negative sign of any number. UNSIGNED data type has no sign and therefore, it is always positive. Therefore, an UNSIGNED number will be always greater than zero.
4. What will be the value of x in the following code?
SIGNAL x : IN UNSIGNED (3 DOWNTO 0 );
x <= “1101”;
a) 12
b) 5
c) -5
d) 14
Answer: d
Explanation: x is declared as an UNSIGNED data type. Therefore, all the 4 bits will be data bits and it will be positive. So, converting 1101 in decimal, we get 1101 equivalent to 14 in decimal number system.
5. What is the decimal equivalent of x in the following code?
SIGNAL x : OUT SIGNED (3 DOWNTO 0 );
x <= “1101”;
a) -5
b) 5
c) -3
d) -14
Answer: c
Explanation: Signed numbers always have first bit representing the sign of the number which is one for the negative and zero for the positive. Also, signed number is represented in 2’s complement form. Therefore, the given number is -3.
6. Which of the following option is completely legal, given that a and b are two UNSIGNED type signals?
a) x <= a + b; y <= a – b;
b) x <= a OR b; y <= a AND b;
c) x <= a + b; y <= a OR b;
d) x <= a OR b; y <= a + b;
Answer: a
Explanation: SIGNED and UNSIGNED data types are intended for arithmetic operations mainly and using logical operators with these data types is illegal. Therefore, only option x <= a + b; y <= a – b; is completely legal. In all other options there are logical operations so those can’t be considered as legal.
7. If a and b are two STD_LOGIC_VECTOR input signals, then legal assignment for a and b is?
a) x <= a.b
b) x <= a OR b
c) x <= a + b
d) x <= a && b
Answer: b
Explanation: Unlike SIGNED and UNSIGNED, STD_LOGIC_VECTOR data type is used mainly for logical operations and we can’t use arithmetic operations with STD_LOGIC_VECTOR. Also, && is not the sign for any operation in VHDL, if you want to perform and operation, then you have to write AND not &&.
8. What do we call the data type used for representing distance, current, voltage, time, etc?
a) Integer
b) Real
c) Physical
d) Imaginary
Answer: c
Explanation: Physical type is used for representing physical values such as time, voltage, etc. by using some base unit. Physical quantities are used in various digital systems and these are important for modelling such systems. Integer and Real are the data types for numbers and there is no data type called Imaginary.
9. What is the meaning of the base unit?
a) Smallest possible unit of any physical literal
b) SI unit of any physical literal
c) CGS unit for any physical literal
d) Fundamental building block of any design
Answer: a
Explanation: Base unit is the smallest possible unit for any physical literal by using which we can derive all other units of the same literal. For example, in case of TIME, the base unit is nanosecond. We can create any bigger unit by using nanoseconds. For example 1 microsecond = 1000 nanosecond.
10. Which of the following is only predefined physical literal in VHDL?
a) VOLTAGE
b) TIME
c) CURRENT
d) DISTANCE
Answer: b
Explanation: TIME is the only predefined physical data type in VHDL. The base unit of TIME is nanosecond. TIME literal is defined in the standard package of std library.
11. SIGNAL a : REAL; which of the following is illegal assignment for a?
a) a <= 1.8
b) a <= 1.0 E10
c) a <= 1.0 E-10
d) a <=1.0 ns
Answer: d
Explanation: Units nanosecond written after the number shows that it is of type TIME and VHDL doesn’t allow TIME type to be assigned to a real Signal. So option d is illegal.
12. Multidimensional arrays can be used for the implementation of memories.
a) True.
b) False.
Answer: a
Explanation: Multidimensional arrays can be seen as array of arrays. For example, we need to implement ROM of 512×4 then we need to define a 2 dimensional array with 4 columns and 512 rows. So, memories can be defined by using 2D array. In which one dimension can show the size of memory and another can show the width of one word.
13. RECORD in VHDL is similar to________ in C.
a) Array
b) File
c) Structure
d) Pointer
Answer: c
Explanation: As in C, Structures are used to collect different data types under a common name. Similarly, RECORD type in VHDL is used for collecting different data types and objects in a single object.
14. What is the difference between SIGNAL and VARIABLE?
a) The value of SIGNAL never varies whereas VARIABLE can change its value
b) SIGNAL can be used for input or output whereas VARIABLE acts as intermediate signals
c) SIGNAL depends upon VARIABLE for various operations
d) SIGNAL is global and VARIABLE is local to the process in which it is declared
Answer: d
Explanation: SIGNALs are used to pass information between entities, they act as interconnection between different entities whereas VARIABLEs can be used in the process or subprogram in which it is declared. So, VARIABLEs are local to the block in which they are declared.
15. Access types are similar to _________ in traditional programming languages.
a) Pointers
b) Arrays
c) Structures
d) Files
Answer: a
Explanation: Access types are used to hold an address of some object which is quite similar to pointers in traditional programming languages. By using the address stored in Access data type, we can access another data objects similar to pointers.
This set of VHDL Multiple Choice Questions & Answers focuses on User defined Data Types”.
1. How the keyword “TYPE” is used?
a) TYPE datatype_name IS type_from_predefined_datatypes;
b) TYPE datatype_name IS datatype_range;
c) TYPE datatype_range IS datatype_name;
d) USE TYPE datatype_range IS datatype_name;
Answer: b
Explanation: The keyword TYPE is used to define new data type if any user wants to define for its own. The syntax for keyword is- TYPE datatype_name IS datatype_range. So, the new data type can have the values defined in range section of the declaration.
2. Which of the following is a wrong declaration for a new data type?
a) TYPE my_logic IS RANGE 0 to 100;
b) TYPE my_logic IS ;
c) TYPE my_logic IS ARRAY OF BIT;
d) TYPE my_logic IS <0 TO 20 >
Answer: d
Explanation: TYPE can be used in three forms as shown above. For defining range, there are two methods as illustrated in option TYPE my_logic IS RANGE 0 to 100; and option TYPE my_logic IS ;. If we want to define a user defined array then the sytanx like option TYPE my_logic IS ARRAY OF BIT; follows. But, we can’t define range by using <> sign.
3. One can’t define an array without any constraints in VHDL.
a) True
b) False
Answer: b
Explanation: We can define an array without any constraints in VHDL. When there are no constraints in array then it can have any number of elements. For example, TYPE my_type IS ARRAY OF BIT; this declaration defines an array of BIT data type without any constraint on the number of elements in the array.
4. A SUBTYPE can be defined as _________
a) A TYPE under a TYPE
b) A type of INTEGER datatype
c) A TYPE with some constraint
d) A TYPE without any constraint
Answer: c
Explanation: A SUBTYPE is a TYPE with some constraints. TYPE can be predefined data type and it can also be any user defined data type. But if SUBTYPE is derived from user defined datatype, then we first have to declare the type along with its range and then subtype can be defined.
5. Which of the following is the correct syntax for declaring a SUBTYPE?
a) TYPE type_name IS type_range AND SUBTYPE subtype_name IS subtype_range
b) SUBTYPE subtype_name IS subtype_range TYPE type_name
c) SUBTYPE subtype_name TYPE type_name IS subtype_range
d) SUBTYPE subtype_name IS TYPE subtype_range
Answer: d
Explanation: The correct way to define a SUBTYPE is the syntax shown in option d. For example, if we want to define a SUBTYPE of STD_LOGIC with 3 values only like X, 0 and 1. We can define it as SUBTYPE my _ subtype IS STD_LOGIC RANGE ‘X’ TO ‘1’.
6. Which of the following can’t be the value of x? Refer to the VHDL code given below.
TYPE color IS (red, green, blue, black, white, gray);
SUBTYPE primary IS color RANGE red to blue;
VARIABLE x: primary;
a) White
b) Red
c) Green
d) Blue
Answer: a
Explanation: PRIMARY is a subtype of COLOR as declared in the code. The range of PRIMARY is declared “red” to “blue”. It means that an object of Primary type can have values red, green or blue. So White can’t be assigned to x.
7. Look at the following declarations:
TYPE array1 IS ARRAY ( 0 TO 3 ) OF BIT_VECTOR (3 DOWNTO 0 );
TYPE array 2 IS ARRAY ( 0 TO 3 ) OF array1;
How many total bits can be stored in these arrays?
a) 16
b) 9
c) 64
d) 27
Answer: c
Explanation: First of all, array1 is array of BIT_VECTOR type that means it contains 4 BIT_VECTOR. One BIT_VECTOR is here declared to be consisting of 4 bits. Therefore, Array 1 can have 16 bits. Now, array2 is an array of 4 array1. Therefore, total bits are 4 × 16 = 64.
8. Refer to the four declarations below, which of the following is not a 2 dimensional array?
TYPE array1 IS ARRAY ( 3 DOWNTO 0, 1 DOWNTO 0 ) OF STD_LOGIC;
TYPE array2 IS ARRAY (3 DOWNTO 0 ) OF STD_LOGIC_VECTOR( 3 DOWNTO 0 );
TYPE array3 IS ARRAY (2 DOWNTO 0 ) OF array2;
TYPE array4 IS ARRAY ( 0 TO 3, 3 DOWNTO 0 ) OF BIT;
a) array4
b) array3
c) array2
d) array1
Answer: b
Explanation: Here, array1 is a 2-D array with 4 rows and 2 columns of STD_LOGIC type. Though, array2 declaration looks like 1D array, but it is 2D array, since it is of type STD_LOGIC_VECTOR, which is already a 1D array, so array2 is a 2D array. Similarly array4 is 4 × 4 matrix. But, array3 is a 3D array. Because it is 1D array of 2D array named as array2.
9. User can define its own integer data type.
a) True
b) False
Answer: a
Explanation: In VHDL, user can define either its own integer type or enumerated type. User defined integer type must always be a subset of predefined datatype. User can define the integer with some desired range. For example, we can define any integer named as my_integer with range 0 to 32 as given: TYPE my_integer IS RANGE 0 TO 32; in this way, one can define a subset of integer.
10. Which of the following is a SUBTYPE of INTEGER?
a) NATURAL
b) REAL
c) CHARACTER
d) STD_LOGIC
Answer: a
Explanation: We can say that NATURAL is a subtype of INTEGER. The range of NATURAL datatype is 0 to 2 31 -1, whereas the range of INTEGER is – (2 31 -1) to (2 31 -1). Therefore, it can be written as SUBTYPE NATURAL IS INTEGER RANGE 0 TO 2147483647.
This set of VHDL Multiple Choice Questions & Answers focuses on “Data Conversion”.
1. Refer to the VHDL code given below, which of the following line has error?
Line 1: SUBTYPE my_logic IS STD_LOGIC RANGE ‘0’ TO ‘1’;
Line 2: SIGNAL a: BIT;
Line 3: SIGNAL b: STD_LOGIC;
Line 4: SIGNAL c: my_logic;
Line 5: b<=a;
Line 6: b<=c;
a) Line 1
b) Line 4
c) Line 5
d) Line 6
Answer: c
Explanation: As a is a SIGNAL of BIT type and b is a SIGNAL of std_logic type; so we can’t perform direct operations on these data. For assigning the value of one data type to another data type, we need to use some type of data conversion. Without data conversion, it is illegal. However, line 6 is legal, because STD_LOGIC and my_logic both has same “base”, which means that my_logic is a subset of STD_LOGIC.
2. One can perform basic operations between different data types.
a) True
b) False
Answer: b
Explanation: VHDL is a strongly typed language i.e. it has very strict rules about predefined and user defined data types. So, we can’t perform any operation between data of different types. Although, it is possible to perform operation between two data types with same base.
3. How to correctly assign the value of 2x+10 to y in the following VHDL code?
TYPE long IS INTEGER RANGE -1000 TO 1000;
TYPE short IS INTEGER RANGE -10 TO 10;
SIGNAL x : short;
SIGNAL y : long;
a) y <= 2*x + 10;
b) long y <= long 2*x + 10;
c) short y <= long ;
d) y <= long ;
Answer: d
Explanation: For all the data types with same base, the conversion can be carried out at the time of operation itself. Therefore, if we want to assign a value of ‘short’ type to a variable of ‘long’ type; we may simply write ‘long’ just after the assignment operator. By doing so, user can convert one type into another. Note that, it is only possible if and only if both the types are having same base.
4. In the VHDL code given below, what will be the error at the time of compilation?
TYPE my_int IS INTEGER RANGE -32 TO 32;
TYPE other_int IS INTEGER RANGE 0 TO 100;
SIGNAL x : my_int;
SIGNAL y : other_int;
y <= x + 2;
…
a) Type mismatch
b) Syntax problem
c) No declaration
d) Can’t compile
Answer: a
Explanation: Here, we have two user defined data types which are my_int and other_int with the same base. But, we can’t directly perform any operation between the signals of these two different types. Such kind of error is called “Type Mismatch” error. First, user needs to convert my_int to other_int. so, the correct assignment statement will be:- y<= other_int ;
5. Which of the following package of IEEE contains most of the data conversion functions?
a) std_logic_1164
b) std
c) std_logic_arith
d) std_logic
Answer: c
Explanation: Most of the conversion functions are defined in the std_logic_arith package of IEEE library. When user need to convert one type of data into another type and both have different bases, then it is essential that he/she need to declare the std_logic_arith package in the library declaration part. However, when we need to convert the data types with same base, then the functions are defined in std_logic_1164 package.
6. If we are using conv_integer function, then which of the following cannot be the type of parameter ‘p’?
a) STD_LOGIC VECTOR
b) STD_ULOGIC
c) INTEGER
d) SIGNED
Answer: a
Explanation: The function conv_integer is used to convert the parameter ‘p’ of any type excluding STD_LOGIC_VECTOR into the integer type. This function can covert INTEGER, SIGNED, UNSIGNED, STD_ULOGIC types into integer type. After converting only, we can use ‘p’ as INTEGER type.
7. In the function conv_unsigned, what does p and b refers to?
a) p is the data object to be converted and b is the base of that data object
b) p is the data object to be converted amd b is the bits needed in converted variable
c) p is the parameter to be converted and b is the bits of same parameter
d) p is the type of data to be converted and b is the type of data into which p should be converted
Answer: b
Explanation: The function conv_unsigned is used to convert different data types in UNSIGNED type. Two arguments are used in this function which are p and b. p is the data object which we need to convert and b represents the no of bits in UNSIGNED type. So, conv_unsigned converts the parameter ‘p’ of INTEGER, SIGNED, UNSIGNED, STD_ULGOIC into UNSIGNED type of size ‘b’ bits.
8. Which of the following is the correct syntax to convert INTEGER ‘p’ into SIGNED number of ‘b’ bits?
a) conv_integer_signed;
b) conv_signed_integer;
c) conv_signed;
d) conv_signed_p;
Answer: c
Explanation: To convert INTEGER, SIGNED, UNSIGNED and STD_ULOGIC types into SIGNED type, the function conv_signed is used. The correct way to use this function is :- conv_signed where p is the object to be converted and b is the number of bits in SIGNED type.
9. The function conv_std_logic_vector is used for_______
a) Converting ‘p’ form STD_LOGIC_VECTOR to STD_LOGIC type
b) Converting any data type ‘p’ into STD_LOGIC_VECTOR with ‘b’ bits
c) Converting STD_LOGIC_VECTOR into ‘p’ type with ‘b’ bits
d) Converting STD_LOGIC into STD_LOGIC_VECTOR
Answer: b
Explanation: This function is used to convert the parameter ‘p’ of type INTEGER, UNSIGNED, SIGNED or STD_LOGIC into STD_LOGIC_VECTOR. Note that the size of converted variable will be ‘b’ bits. So, b represents the number of bits in the converted object.
10. What will be the value of y after the execution of the following VHDL code?
Library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
…
SIGNAL m : UNSIGNED (3 DOWNTO 0);
SIGNAL n : UNSIGNED (3 DOWNTO 0);
SIGNAL y : STD_LOGIC_VECTOR (7 DOWNTO 0);
y <=CONV_STD_LOGIC_VECTOR ((m+n), 8);
…
a) 8- bit STD_LOGIC_VECTOR m+n
b) 8- bit UNSIGNED m+n
c) 4- bit STD_LOGIC m+n
d) Error
Answer: a
Explanation: Here, the conversion function is used to convert the data objects into STD_LOGIC_VECTOR type. The operation ‘m+n’ is completely legal since both are UNSIGNED type, after this operation the result is converted into STD_LOGIC_VECTOR with size ‘8’ bits. So, the values assigned to ‘y’ will be of STD_LOGIC_VECTOR type of 8 bits.
11. Refer to the VHDL code given below, what will be the output?
Library ieee;
USE ieee.std_logic_1164.all;
USE ieee.std_logic_arith.all;
…
SIGNAL a : IN INTEGER;
SIGNAL b : IN UNSIGNED (3 DOWNTO 0);
SIGNAL y : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
y <<=CONV_STD_LOGIC_VECTOR ((a+b), 8);
…
a) 8- bit STD_LOGIC_VECTOR a+b
b) 8- bit UNSIGNED a+b
c) 4- bit STD_LOGIC_VECTOR a+b
d) Error
Answer: d
Explanation: The code is not completely legal. There will be an error of type mismatch. Since a and b are two completely different data types, one is INTEGER and another is UNSIGNED. So, we can’t perform the operation ‘a+b’. Therefore, to perform this operation, first a and b need to be of same type, which can be done by converting INTEGER into UNSIGNED or vice-versa.
This set of VHDL Multiple Choice Questions & Answers focuses on “Operators – 1”.
1. Which of the following is not an assignment operator?
a) <=
b) :=
c) =>
d) =
Answer: d
Explanation: Assignment operators are used to assign some value to a data object. <= operator is used to assign values to a SIGNAL. := operator is used to assign values to VARIABLE, CONSTANTS and GENERICS; this operator is also used for assigning initial values. Another assignment operator is =>, used to assign values to individual vector elements or others.
2. A VARIABLE y is declared of STD_LOGIC_VECTOR type of 4 bits, if you want to assign 1001 to y, then what is the write assignment statement?
a) y <= “1001”
b) y := “1001”
c) y <= ‘1’, ‘0’, ‘0’, ‘1’
d) y => “1001”
Answer: b
Explanation: To assign values to any variable, the := operator is used. Since, y is a VARIABLE STD_LOGIC_VECTOR type, we can only use := operator and not <= operator. => can be used, but while assigning individual elements of a vector.
3. Refer to the VHDL code given below, which is the legal assignment statement?
SIGNAL x: STD_LOGIC;
SIGNAL y: STD_LOGIC_VECTOR(3 DOWNTO 0);
a) y <= ;
b) y := “0100”;
c) y => “0100”;
d) y => x;
Answer: a
Explanation: To assign a value to a SIGNAL, either <= or => can be used only. But, if we want to use =>, then values need to be assigned to individual elements. => is used with OTHERS. Y<= means that the value assigned to y is 0100.
4. Which of the following logical operator has the highest precedence?
a) NAND
b) NOR
c) NOT
d) EXOR
Answer: c
Explanation: NOT is the logical operator which has highest precedence. If there are more than one logical operator in the same statement, then NOT will be given highest preference. If there is any in the statement then first preference will be given to and then to NOT operator.
5. In the following statements, y and z are equivalent to________
y <= NOT a AND b;
z <= NOT (a AND b);
a) y <= a’+b’ and z <= ’
b) y <= ’ and z <= a’+b’
c) y <= a’+b and z <= a’+b’
d) y <= a+b’ and z <= a.b
Answer: c
Explanation: As discussed above, NOT will be given highest preference. So, y becomes AND b) which is a’+b. similarly, in z first of all will be solved i.e.’ which is ’. By, De Morgan’s law, ’ = a’+b’. Therefore, y = a’+b and z = a’+b’.
6. Which of the following VHDL statement is equivalent to NAND operation, if y, a and b are SIGNALS?
a) y <= NOT a AND b
b) y <= NOT a OR NOT b
c) y <<= NOT a AND NOT b
d) y <<= NOT
Answer: b
Explanation: Logic NAND operation is ’ which is equivalent to a’ + b’ by using De Morgan’s law. NOT a AND b is equivalent to . NOT a AND NOT b is equivalent to . Similarly, NOT is ’.
7. ______ operator is unary as well as binary operator.
a) –
b) *
c) /
d) **
Answer: a
Explanation: Unary operator is the one which needs only one operand and Binary operator needs two operands. ‘–’ is the only operator which can be used with one as well as two operands. When used with single operand, the result is negative of the same number and similarly, when used with two operands then the result is difference of two operands.
8. The operator ‘&’ is called the_____ operator.
a) Logical AND operator
b) Bitwise AND operator
c) Arithmetic addition operator
d) Concatenation operator
Answer: d
Explanation: ‘&’ is called the concatenation operator and is a binary operator. It needs two operands and both of them must be arrays. It combines two arrays and produces one array of the size equal to the sum of sizes of two arrays.
9. What is the type of result of MOD operator?
a) Numeric
b) Integer
c) Array
d) Bit
Answer: b
Explanation: The MOD operator is called the modulo operator which gives the remainder of the division of two integers and hence the result is of integer type. For example, y <= a MOD b; will return the value of remainder when a is divided by b. suppose a= 12 and b= 5 then the value of y will be 2.
10. The operators like =, /=, <, >, >= are called _________
a) Arithmetic operators
b) Concatenation operators
c) Logical operators
d) Relational operators
Answer: d
Explanation: These operators are relational operators or Comparison operators since they are used to compare two operands. The = refers to equal to, /= refers to not equal to operator. Similarly,<, >, <=, >= are called less than, greater than, less than or equal to, greater than or equal to operators.
11. What is the type of result for comparison operators?
a) Boolean
b) Integer
c) Numeric
d) Array
Answer: a
Explanation: Comparison operators are used for the comparison of two operands and the result is of Boolean type i.e. true or false. For example, b:= “0010” < “0001”; In this statement, the value assigned to b will be FALSE, since this means 2 < 1, which is not true.
12. ABS operator is used to _________
a) Shift the operand
b) Gives absolute value for the operand
c) Give the result as nearest integer
d) To synthesize the result
Answer: b
Explanation: ABS operator is a unary operator which returns the absolute value. We can use this operator to increase the reliability of code. For example, we need to use π, then the value of the same is 22/7 or 3.14. In VHDL, if we use following statements: pi = 22/7; IF THEN WAIT; Then we might not get the result as we want. It will be unreliable. If we use ABS operator along with it, then it will be better. Like, IF=3.14) THEN WAIT; this will give the desired result.
13. Which of the following is exponentiation operator?
a) ^
b) *
c) /=
d) **
Answer: d
Explanation: Exponentiation operator in VHDL is represented by two asterisk signs. So, ** is the exponentiation operator which comes under the category of arithmetic operators. In VHDL, a**b means a^b.
This set of VHDL Interview Questions and Answers for freshers focuses on “Operators – 2”.
1. SIGNAL x : STD_LOGIC; In this statement x is ______
a) Variable
b) Identifier
c) Name
d) Literal
Answer: b
Explanation: Identifier is a simple name given to any constant, variable, signal, entity, port or a subprogram. A name must begin with alphabetic letter. It may contain alphanumeric characters and underscore sign. Reserved words of VHDL can’t be used as identifiers.
2. What is the use of shift operators?
a) To shift the data
b) To shift the identifiers
c) To shift the operators
d) To shift the STD_LOGIC_VECTOR
Answer: a
Explanation: Shift operators are used to shifting of data. These operators were introduced in the VHDL93.
3. What is the “SLL” operator?
a) Shift Logic Left
b) Shift Logically
c) Shift Left Logical
d) Shift Left
Answer: c
Explanation: SLL is a shift operator used to shift bits of the operand to one left position and fills the rightmost position with zero. Shift Left Logical operator will shift the bits logically. For example, we had data 0100 in the operand, then after applying SLL, we will get 1000.
4. The correct syntax for any logical shift operator like SLL and SRL is_____
a) bit_vector_operand <OPERATOR> integer_operand
b) integer_operand <OPERATOR> bit_vector_operand
c) std_logic_operand <OPERATOR> integer_operand
d) integer_operand <OPERATOR> std_logic_operand
Answer: a
Explanation: SLL and SRL operators can shift the operands of vector type. It may be BIT_VECTOR type or STD_LOGIC_VECTOR type. The left operand is shifted towards left or right depending on the operator with number of shifts represented by right operand which always must be an INTEGER type.
5. Refer to the VHDL code given below, what should be the output of the identifier ‘y’ and ‘z’?
VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1010;
VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000;
VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000;
…
y := x SRL 2;
z := x SLL 2;
…
a) y = 0100 and z = 0100
b) y = 0010 and z = 0100
c) y = 0100 and z = 1000
d) y = 0010 and z = 1000
Answer: d
Explanation: SRL operator will shift the operand towards right and SLL will shift the same towards left. All the left bits will be filled with zero in SRL operation and in SLL right bits will be filled with zero. Therefore, y must be x shifted towards right with 2 positions.
6. In the following VHDL code, the values of y and z are _____
VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1001;
VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000;
VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000;
…
y := x SRA 2;
z := y SLA 2;
…
a) y = 0000 and z = 0000
b) y = 1001 and z = 0000
c) y = 1110 and z = 0111
d) y = 0111 and z = 1110
Answer: c
Explanation: SRA and SLA expands to Shift Right Arithmetically and Shift Left Arithmetically respectively. These operators shift the left operand towards right or left by number of bits specified by right operand. Unlike SLL and SRL, the empty bits are not filled with zero, but they are replaced with the MSB in case of SRA and with LSB in case of SLA. For example, in above code, if we shift the x towards right arithmetically then it will become 1100, i.e. the MSB is replicated instead of zero. Therefore, Shifting to two positions will give y = 1110 and z= 0111.
7. SLL operation is equivalent to which of the following operations?
a) Multiplication by any natural number
b) Multiplication by 2
c) Division by 2
d) Exponential operation
Answer: b
Explanation: Shift Left Logical shifts the bits towards left and Shift Right Logical shifts towards right. In binary number system, shifting left refers to multiplication with two and similarly, shifting right refers to division by two. For example, the number 0010 represents 2 in decimal number system. Now, if we shift it left by one position then it will become 0100 which is equivalent to 4 in decimal number system. Therefore, shifting left is equivalent to multiplication operation.
8. Which of the following is equivalent division by 2 operator?
a) SRL
b) SLL
c) SLA
d) SRA
Answer: a
Explanation: SRL operator shifts the given operand towards right. For, example, if we have a number 0010, equivalent to two, which is shifted right then it will become 0001 which is equivalent to 1. Therefore, this operation corresponds to division of any number by two.
9. In the VHDL code given below, what will be the values of y and z?
VARIABLE x : BIT_VECTOR(3 DOWNTO 0) := 1001;
VARIABLE y : BIT_VECTOR(3 DOWNTO 0) := 0000;
VARIABLE z : BIT_VECTOR(3 DOWNTO 0) := 0000;
…
y := x ROR 2;
z := y ROL 2;
…
a) y = 0100 and z = 0000
b) y = 0000 and z = 0000
c) y = 0111 and z = 1110
d) y = 0110 and z = 0110
Answer: d
Explanation: ROR and ROL are Rotate Right and Rotate Left operators respectively. These operators’ wraps around the operand that means the bit shifted out will replace the vacant bit. Therefore, Rotating x two times towards right will give 0110 in y and when it is rotated left then it will be the same.
10. In a statement containing two or more operators of same precedence, how the expression will be solved?
a) Left to right
b) Right to left
c) Alphabetically
d) In a random manner
Answer: a
Explanation: In VHDL, to solve any expression a simple rule is followed. The rule is “highest precedence first, left to right within same precedence”. However, we can use parenthesis to control the order of operations, but by default it will solve left to right. It may be noted that parenthesis is the operator with highest precedence.
11. What will be the values of the following variables after MOD operations?
x = 5 MOD 3;
y = -5 MOD 3;
z = 5 MOD -3;
a) x = 2, y = -2 and z = -2
b) x = 2, y = 1 and z = -2
c) x= 2, y = -2 and z = 2
d) x = 2, y = -2 and z = 1
Answer: b
Explanation: MOD takes the sign of divisor which is the second operand, but not of first operand. In the first operand, it will simply give the remainder which is 2. In the second statement, the modulo will not contain negative, it will simply divide and the result will be 1. This is done by adding 3*2 in -5, in that case 1 is left, therefore modulo is 1. But, in third statement, divisor is negative so it will be taken as -.
12. What will be the values of following variables after REM operations?
x = 5 REM 3;
y = -5 REM 3;
z = 5 REM -3;
a) x= 2, y = 1 and z = -2
b) x = 2, y = -2 and z = 1
c) x = 2, y = -2 and z = 2
d) x = 2, y = 1 and z = 1
Answer: c
Explanation: Here, REM operator is used, which takes the sign of dividend instead of divisor unlike MOD operator. In case of negative divisor, the sign is ignored. Therefore, in first statement, the remainder is calculated normally, which is 2. In second statement, it will be considered as -. In third statement, it is simply solved like first statement, ignoring the negative sign.
13. XNOR is a logical operator in VHDL.
a) True
b) False
Answer: a
Explanation: XNOR is a logical operator representing Ex-NOR operation and was introduced in VHDL 93. In the previous versions, there was no XNOR operator and to perform Ex-NOR, we needed to implement it by using XOR itself.
This set of VHDL Multiple Choice Questions & Answers focuses on “Behavioural Modelling”.
1. The most basic form of behavioral modeling in VHDL is _______
a) IF statements
b) Assignment statements
c) Loop statements
d) WAIT statements
Answer: b
Explanation: Assignment statements are used basically in the behavioral modeling. In behavioral modeling, one needs to describe the value of outputs for various combinations of inputs, so we need to assign different values to output variables. Therefore, the assignment is the most used statement in behavioral modeling.
2. For any concurrent assignment statement, which of the following is true?
a) The statement is executed once
b) The statement is executed twice
c) The value of left operand is assigned to right operand
d) The statement is executed as many times as the value changes
Answer: d
Explanation: A concurrent assignment statement assigns the value of right operand to left operand and this statement is executed many times. Whenever the value of right operand is changed, the assignment statement is executed.
3. a < = b after 10ns; In this statement the keyword ‘after’ is used for introducing delay.
a) True
b) False
Answer: a
Explanation: The keyword ‘after’ is used for introducing delay in the assignment statement. Whenever the value of b is changed, the value of a is changed after 10ns. This 10ns is helpful while creating square waveform.
4. Which of the circuit is described by following VHDL code?
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY my_func IS
PORT(x, a, b : IN std_logic;
q : OUT std_logic);
END my_func;
ARCHITECTURE behavior OF my_func IS
SIGNAL s : INTEGER;
BEGIN
WITH s SELECT
q <= a AFTER 10 ns WHEN 0;
b AFTER 10 ns WHEN 1;
s <= 0 WHEN x = ‘0’ ELSE
1 WHEN x = ‘1’;
END behavior;
a) AND gate
b) OR gate
c) MUX 2:1
d) DEMUX 1:2
Answer: c
Explanation: In this code, the behavior of 2:1 MUX is explained. By using WITH statement, the output is selected by the use of select line. Here, s is used as select line and x is considered as the value of select line. Also, a and b are taken as two inputs and q as output.
5. The main problem with behavioral modeling is ________
a) Asynchronous delays
b) Simulation
c) No delay
d) Supports single driver only
Answer: a
Explanation: In behavioral modeling, there are different types of delays and this can create problem in functioning of system. Sometimes zero delay events are used to produce consistent results. If these are not properly ordered, results can be disparate between different simulations.
6. What is the use of simulation deltas in VHDL code?
a) To create delays in simulation
b) To assign values to signals
c) To order some events
d) Evaluate assignment statements
Answer: c
Explanation: Simulation deltas are used to order some specific events to avoid complications in simulations. Especially, in zero delay events, they are properly ordered so as to produce consistent results. It is actually a complex delay model used for zero delay events.
7. VHDL can’t handle multiply driven signals.
a) True
b) False
Answer: b
Explanation: A multiply driven signal is the one which has more than one driver. VHDL can handle these signals easily and in a unique way. These multiply driven signals are useful for modeling various data bus and bidirectional bus etc.
8. Which function is used to create a single value for multiple driver signals?
a) Resolution function
b) Package
c) Concurrent assignments
d) Sequential assignments
Answer: a
Explanation: The values of all the drivers are resolved together to create a single value for the signal. The method of resolving all the drivers is through a resolution function which is a designer writer function. That function is called whenever any one of the driver changes its value.
9. Refer to the VHDL code given below, which of the following signal is driven by multiple drivers?
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY function IS
PORT (b, c : IN BIT;
a, d : OUT BIT);
END function;
ARCHITECTURE behavior OF my_func IS
BEGIN
a <= b;
a <= c;
d <= b;
END behavior;
a) d
b) c
c) b
d) a
Answer: d
Explanation: A signal is called multiply driven signals if it is driven by more than one signals or the value of signal changes with respect to more than one signal. Here, the value of changes when the value of b or value of c changes. Therefore, a is driven by two drivers named as b and c. Each concurrent statement creates a driver for left operand.
10. A signal is driven by two signals b and c. How the value of b and c will be resolved to calculate the value of a?
a) By short circuiting both driver
b) By open circuiting one driver
c) By AND operation between two drivers
d) By NOT operation of both drivers
Answer: a
Explanation: The value of multiple driver signal is found by using resolution function. The default resolution function short circuits all the drivers and performs OR operation which means any change in any driver will cause change in output signal. The value of delays is also taken into consideration.
This set of VHDL Objective Questions & Answers focuses on “Type of Delays in Behavioural Modelling”.
1. Which of the following is default delay in VHDL?
a) Inertial delay
b) Transport delay
c) Delta delay
d) Wire delay
Answer: a
Explanation: In VHDL, inertial delay is the default delay in VHDL. If no delay type is specified then it will be used as inertial delay. The reason behind taking, inertial delay as default is that in most case it behaves similarly to the actual device to be designed.
2. What must be overcome by the output signal to change the value in case of inertial delay?
a) Time
b) Error
c) Inertia
d) Pulse
Answer: c
Explanation: In case of inertial delay model, the output signal has some inertia which must be overcome for the signal to change its value. If a signal value is maintained for a time longer than the delay through the device, the output signal value changes to a new state.
3. The inertia value in inertial delay model is equal to _________
a) Initial value
b) Delay
c) Input value at a specific time
d) Output value at a specific time
Answer: b
Explanation: The inertia value in inertial delay model is equal to the delay through the device. This value must be overcome first to change the signal state. If there is any impulsive change in between then the state of signal will not change after the specified delay.
4. Transport delay is a kind of __________
a) Synthesis delay
b) Simulation delay
c) Inertial delay
d) Wire delay
Answer: d
Explanation: Transport delay represents a wire delay in which any pulse is propagated to the output signal delayed by a specified delay value. Therefore, Transport delay is useful in modeling the delay line devices and path delays in ASICs.
5. In inertial delay, if the signal value is maintained for the time period less than delay tiem, then the signal value does not change.
a) True
b) False
Answer: a
Explanation: If there are any spikes or pulses in between the delay period then the output value doesn’t change accordingly. Because any pulse in between the delay period will be swallowed in case of inertial delay and the output state will not change.
6. A buffer with single input A and single output B has a delay of 20 nanosecond. If the value of input A changes after 10 ns from 0 to 1 and it changes again from 1 to 0 at 20 ns. At what time, the value of output B will be 1, if the inertial delay model is used?
a) 30 ns
b) 40 ns
c) 20 ns
d) Output will remain zero
Answer: d
Explanation: Inertial delay model swallows the pulses or spikes in between the delay time period. The buffer is executed at 0 ns for the delay of 20 ns and then the value of A changes at 10 ns, which again execute buffer and schedule the output to be 1 at 30 ns. But at 20 ns, the value of A again changes which executes the buffer again and schedule the output to be zero at 40 ns. Therefore, the output will not change. Inertial model doesn’t order events it will take into consideration only the last event.
7. The keyword TRANSPORT in any assignment statement specifies _______
a) Transport delay
b) Transfer the right operand immediately to left operand
c) Transporting the value of left operand to right operand
d) Inertial delay
Answer: a
Explanation: TRANSPORT is a keyword used for specifying the use of transport delay. The mechanism followed by the EDA tool will be the transport delay mechanism instead of the default delay type called inertial delay.
8. A buffer with single input A and single output B has a delay of 20 nanosecond. If the value of input A changes after 10 ns from 0 to 1 and it changes again from 1 to 0 at 20 ns. At what time, the value of output B will be 1, if the transport delay model is used?
a) 20 ns
b) 30 ns
c) 40 ns
d) Output will remain zero
Answer: b
Explanation: In case of transport delay model, all the spikes and pulses, no matter how small, are taken into consideration i.e. not swallowed down. Transport delay order the events rather than just scheduling the last event. Therefore, when the buffer is executed at 10 ns, it will schedule a 1 at B at 30 ns. After which, it is again executed at 20 ns and hence the output will be zero again at 40 ns.
9. In the VHDL code given below, which delay model is used?
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY buffer IS
PORT(a : IN STD_LOGIC;
b : OUT STD_LOGIC);
END buffer;
ARCHITECTURE buf OF buffer IS
BEGIN
b <= a AFTER 20 ns;
END buf;
a) Simulation delta model
b) Transport delay model
c) Inertial delay model
d) Multiple driver delay model
Answer: c
Explanation: The assignment statement b <= a AFTER 20 ns is a delay statement. As there is no delay type specified, consequently, it will be considered as inertial delay. If one wants to use transport delay model, then it needs to be specified unlike inertial delay. For example, b < TRANSPORT a AFTER 20 ns; this statement will introduce transport delay mechanism.
10. Following waveform shows the output B of a buffer having delay 10 ns for two different delay mechanisms, specify the name of delay mechanism for corresponding waveform.
vhdl-objective-questions-answers-q10
a) W1- Inertial, W2- Transport
b) W1- Inertial, W2- Inertial
c) W1- Transport, W2- Transport
d) W1- Transport, W2- Inertial
Answer: d
Explanation: W1 is transport since it doesn’t need to overcome the inertia and the events are scheduled sequentially after the specified delay time period. Whereas, in waveform W2, the output is concerned with the last value only. Therefore, waveform 2 is the illustration of inertial delay model.
11. For zero delay events, which of the following mechanism is used?
a) Transport delay mechanism
b) Inertial delay mechanism
c) Delta delay mechanism
d) Preemption delay mechanism
Answer: c
Explanation: For zero delay events, The output can disparate between two different simulation runs. For example, in a complex circuit, if we are using a NAND gate then the output can be affected by the order of the events, like AND operation first and after that NOT operation can produce some different result whereas it opposite order can produce some different result. Therefore, to avoid this at the time of simulation, we use the simulation delta delay model.
12. Which of the following delay model follows the principle of preemption?
a) Inertial delay
b) Transport delay
c) Delta delay
d) Wire delay
Answer: a
Explanation: Preemption technique means that only last event is taken into consideration whereas preceding events can be ignored. Same is the case with inertial delay model in which only last value of output is considered ignoring all the previous events or pulses or spikes etc.
13. Which of the following is not the application of inertial delay?
a) Buffer delay
b) PC wire line delay
c) Simple delay in OR gate
d) Inverter delay
Answer: b
Explanation: The inertial delay can be used for any of the logic circuit may it be a logic gate or any combinational circuit, but it can’t be used in any wire. Because in wire line delay, we need to order event sequentially, this is possible only in transport delay mechanism. Therefore, PC wire line delay can be implemented only by using a transport delay mechanism.
14. The condition to implement the simulation delta delay is _______
a) All events must be synchronous
b) The events must have at least one sequential circuit
c) No condition
d) All events must be zero delay event
Answer: d
Explanation: The simulation delta delay model is used to solve the problem of different output for same input between different simulation runs. This occurs when all the events have zero delay and are not properly ordered. So, simulation delta delay model is implemented when the events are with zero delay.
This set of VHDL Multiple Choice Questions & Answers focuses on “Generics”.
1. In which part of the VHDL code, generics are declared?
a) Package declaration
b) Entity
c) Architecture
d) Configurations
Answer: b
Explanation: Generics are a general mechanisms used to pass information to an instance of any entity and are declared in the entity itself. These are of constant type and are declared before port declarations. The declaration of generics is followed by the keyword GENERIC.
2. Which of the following is correct declaration for a generic?
a) GENERIC ;
b) GENERIC ;
c) GENERIC ;
d) GENERIC ;
Answer: a
Explanation: The declaration of generic is done in entity declaration part and the correct syntax to declare it is GENERIC . Since, generic is constant object, so := operator is used to assign the initial value.
3. What is the main use of the generic parameter?
a) Defining constant type
b) Assigning some initial value to constant
c) Reusability
d) Using constant type within the entity
Answer: c
Explanation: The purpose of defining a generic statement within an entity is to confer more flexibility and reusability. A generic parameter is basically used globally with some value. Whenever one want to reuse same thing again and again then defining it as a generic parameter will be useful rather than defining it again and again.
4. More than one generic parameter can be defined in a single entity.
a) True
b) False
Answer: a
Explanation: It is possible to define more than one parameter in an entity. If we want to define more than one generic parameter, then the two parameters must be separated by a semicolon. For example, GENERIC ; In this declaration n and m are two different generics in which one is of INTEGER and another is BIT_VECTOR type.
5. Which of the following is true about Generics?
a) Generics can be assigned information as part of simulation run
b) Generics cannot be assigned information as part of simulation run
c) Generic passes data to an entity which is not instance specific
d) Results of simulation can modify the value of generics
Answer: b
Explanation: All the data passed to an entity is instance specific and this data can’t be assigned any information as a part of simulation run. The value of generic is not a simulation specific value but, it is a instance specific value which can’t be modified by the simulation results.
6. A generic can’t be declared in a component declaration.
a) True
b) False
Answer: b
Explanation: A generic can be declared in entity as well as in any component declaration statement. It is not necessary to define generic in entity only. If structural modeling is used, then generic can be used in component declaration statement too. However, it must be noted that the generic is declared before ports declaration.
7. In most synthesis tools, only generics of type ________ are supported.
a) INTEGER
b) REAL
c) BIT_VECTOR
d) STD_LOGIC
Answer: a
Explanation: Integer type is the only generics type which is synthesizable in most of the EDA tools. Whereas, in some cases all the types are synthesizable. It is possible to define any type of generic but the thing is that they may not be synthesized.
8. GENERIC ; In this statement, the mode of generic ‘n’ is _______
a) Integer
b) Real
c) Generic
d) No Mode
Answer: d
Explanation: Generics are a means of passing specific information into an entity. Generics can have only a type but no mode. Integer is the type of generic. Mode of any variable or signal defines its direction which means whether it is used as an input signal or output signal. Therefore, mode is not defined in the case of generics.
9. Which function is used to map a generic on design?
a) Port map
b) Generic
c) Generic map
d) Port
Answer: c
Explanation: As generic is declared before a port in component and entity declaration. Similarly, to map a generic type, one can use generic map function before port map function in component instantiation part of the code. This function is used in structural modeling.
10. Generics in VHDL can be treated as _______
a) Global variable
b) Local variable
c) Variable
d) Signal
Answer: a
Explanation: Generics in VHDL can be taken as global variable which is declared once and is used in complete design. Unlike signals, generics doesn’t have a mode or direction and unlike variable the value of generics can’t be changed.
11. Which of the following can be used as a generic in a complex digital design with many inputs and two outputs?
a) Number of outputs
b) Number of inputs
c) Intermediate signals
d) No parameter
Answer: b
Explanation: Generics are used where a single change of value can change it everywhere in the code. For example, if one wants to change the input sizes then it can be changed in entity and respective change is seen everywhere in the code. Since the number of outputs is constant and therefore no need to use number of outputs as generics.
This set of VHDL Multiple Choice Questions & Answers focuses on “Block Statement”.
1. What do you mean by a block?
a) An object of architecture
b) Interconnection of two or more signals
c) A part of an entity
d) A sub module in an architecture body
Answer: d
Explanation: The sub modules in architecture can be described as blocks. A block is a unit of module structure, with its own interface, connected to other blocks or ports. For example, while designing CPU, one can divide the architecture into blocks in which one may be describing ALU and another may be describing Control signals and so on.
2. Which of the following is correct syntax for block definition?
a)
label : BLOCK
declarative_part;
BEGIN
concurrent_statements;
end BLOCK label;
b)
label : BLOCK
declarative_part;
BEGIN
concurrent_statements;
end label BLOCK;
c)
BLOCK block_name;
declarative_part;
BEGIN
concurrent_statements;
end BLOCK block_name;
d)
BLOCK block_name
declarative_part;
BEGIN
sequential_statements;
end BLOCK;
Answer: a
Explanation: A block is declared by using some label. First, a label is given to the block which is followed by a colon and then the keyword BLOCK. In the next line, signals, components, constants etc. are declared. After the declaration part of the block, BEGIN keyword is used followed by concurrent statements describing the behavior of the block.
3. What is the scope of variables or signals declared in the block statement?
a) Global to the design
b) Local to the architecture
c) Local to the block itself
d) Local to the entity of which architecture is defined
Answer: c
Explanation: The variables or signals declared in the BLOCK are available local in the block statement only. However, a block can declare constants, types, components, subprograms apart from variables or signals. But, anything declared in the block can be used in the block only.
4. Which of the following defines the interface to the block?
a) Block declaration part
b) Block header
c) Block statement part
d) Generic declaration part
Answer: b
Explanation: A block header defines the interface to an entity. The values of generics or components associated with the block are defined in the block header. It uses a port map and generic map functions to declare and map components and generics with the block.
5. Guarded block has an extra ________ expression.
a) Conditional
b) Declarative
c) Block
d) Guard
Answer: d
Explanation: VHDL has two types of block which are Simple blocks and guarded blocks. Guarded blocks have an extra guard expression. The role of guard expression is to control the execution of guarded block. The guarded statements in a guarded block are executed only when the guard expression is TRUE.
6. What should be the type of the value of guard expression?
a) BOOLEAN
b) INTEGER
c) REAL
d) BIT_VECTOR
Answer: a
Explanation: The type of result of guard expression should be BOOLEAN which may take only two values either TRUE or FALSE. The statements under guarded block are executed only when the result of guard expression is TRUE. Therefore, it is mandatory to have an expression with BOOLEAN output.
7. What is the main purpose of using blocks?
a) To improve reusability
b) To improve conditional execution
c) To improve readability
d) To improve speed of execution
Answer: c
Explanation: Blocks are useful to improve the readability and management of VHDL design. In a high level design, say CPU design, blocks are very useful since it can be divided into blocks which can further be managed easily rather than managing whole code. Another use of block statement is to disable some signals by using guard expression. However, the result of simulation will be same of the code using block and the same without blocks.
8. Guarded blocks are synthesizable.
a) True
b) False
Answer: b
Explanation: In general EDA tools, the guarded blocks are not synthesizable and unguarded blocks doesn’t add any additional functionality to the design and therefore, are usually ignored by synthesis tools. So, it is not much useful to use blocks in non-VITAL designs.
9. Which of the following is better for design partitioning?
a) Guarded block
b) Unguarded block
c) Component instantiation
d) Component declaration
Answer: c
Explanation: Since guarded and unguarded blocks are not synthesizable. So, component instantiation is certainly a better mechanism to handle design partitioning which is completely synthesizable. Therefore, it is recommended to use component instantiation rather than block statements.
10. A block can be nested within another block.
a) True
b) False
Answer: a
Explanation: Nesting of blocks is possible in VHDL. A block can be defined within another block. The nested block is called the child block and the other block is called parent block. Also, it is possible to define two signals with same name one in parent block and another in child block.
11. Which of the following is true about guarded blocks?
a) Guarded blocks can have only guarded statements
b) Guarded blocks can have both guarded as well as unguarded statements
c) Guarded blocks are executed when guarded expression is false
d) Guarded expression can have BIT type
Answer: b
Explanation: Guarded blocks can have both types of statements which are guarded and unguarded. Guarded assignment statements are those statements in which an assignment operator is followed by the keyword called GUARDED. For example, q <= GUARDED d AFTER 10 ns; here the assignment statement used is guarded statement.
12. Which of the following statement is used to describe regular structures?
a) BLOCK
b) GENERATE
c) USE
d) GUARDED BLOCK
Answer: b
Explanation: Generate statement is used to describe regular structures such as array of blocks, component instances or processes. There are two types of generation schemes one is FOR generation and another is IF generation.
13. What will be the values of out1 and out2?
ARCHITECTURE bhv OF example IS
CONSTANT out1 : BIT;
CONSTANT out2 : BIT;
BEGIN
B1 : BLOCK
CONSTANT S : BIT := 0;
BEGIN
B1-1 : BLOCK
SIGNAL S : BIT := 1;
BEGIN
out1 <= S;
END BLCOK B1-1;
out2 <= S;
END BLOCK B1;
END bhv;
a) out1 = 0 and out2 = 0
b) out1 = 0 and out2 = 1
c) out1 = 1 and out2 = 0
d) out1 = 1 and out2 = 1
Answer: c
Explanation: Objects declared in a block are visible to that block and the blocks nested within. But, when a child block declares an object with same name as the one in parent block then child’s declaration overrides the parent’s object. Therefore, S used in block B1-1 will be 1 and another will be 0.
14. What is the use of FOR generation?
a) For describing the exceptional signals
b) For describing the repeating structures
c) For describing half adder circuit
d) For any exceptional cases of structure
Answer: b
Explanation: FOR generation is similar to for loop in traditional programming languages. Therefore, it can be used to describe structures which use some repeating pattern or similar patterns. It is not useful to design half adder by using FOR generation statement.
15. Which of the following is the use of IF generation?
a) To handle repeating pattern of design
b) To handle exceptional cases of design
c) To design full adder circuit
d) To connect input instances with output
Answer: b
Explanation: IF is a conditional generation scheme. It can be used to handle some conditional or exceptional cases of the structure. These exceptions may occur at the boundaries. So, IF generation is generally used at boundaries.
This set of VHDL Multiple Choice Questions & Answers focuses on “Structural Modelling – 1”.
1. Which of the following is defined in structural modeling?
a) The structure of circuit
b) Behavior of circuit on different inputs
c) Data flow from input to output
d) Functional structure
Answer: a
Explanation: Structural modeling is the modeling of the circuit at the component level. This type of modeling is used to describe the structure of the system with all the components. Along with components, interconnections between them are also defined.
2. Which of the following is not a way of partitioning a design?
a) Component
b) Block statement
c) Processes
d) Generics
Answer: c
Explanation: A VHDL design can be partitioned in many ways but generics is not the way to partition the design. Generics are used as constants. A component can divide the design at a structural level. Similarly, Blocks and processes can divide the behavioral model of the design.
3. What is the basic unit of structural modeling?
a) Process
b) Component declaration
c) Component instantiation
d) Block
Answer: c
Explanation: Structural modeling describes the design at the component level. Like behavioral modeling is described by using processes, similarly, structural modeling is described by using component instantiation. Both processes and component instantiation are described in the architecture body.
4. Which of the following is similar to the entity declaration in structural modeling?
a) Component instantiation
b) Component declaration
c) Port map
d) Generic map
Answer: b
Explanation: Component declaration in structural modeling is similar to the entity declaration. It describes the external interface of the component or subcomponent. All the input and output ports are declared in the component declaration part.
5. What do you mean by component instantiation?
a) To use the component
b) To describe external interface of the component
c) To declare the gate level components
d) To remove any component from the design
Answer: a
Explanation: Component instantiation means to use the component in the circuit. Declaration of component just declares the input and outputs of the component but its instantiation describes its interconnection with other components and to port it in the circuit.
6. The structural model is similar to___________
a) Boolean relations of the circuit
b) Schematic block diagram of the circuit
c) Timing relations of the circuit
d) Components of the circuit
Answer: b
Explanation: The structural modeling in VHDL is similar to the schematic block diagram of the circuit. Just like block diagram defines the components and interconnection between them, same is the case with structural modeling.
7. Which of the following is correct syntax for component declaration?
a)
COMPONENT component_name IS
PORT ( port_mode : type port_name;
port_mode : type port_name;
….);
END component_name;
b)
COMPONENT component_name IS
PORT ( port_mode : type port_name;
port_mode : type port_name;
….);
END COMPONENT;
c)
COMPONENT component_name IS
PORT ( port_name : mode type;
port_name : mode type;
….);
END component_name;
d)
COMPONENT component_name IS
PORT ( port_name : mode type;
port_name : mode type;
….);
END COMPONENT;
Answer: d
Explanation: To define a component in the code, the keyword COMPONENT is used followed by the name of the component and keyword IS. In the next lines, the ports of the component are declared and the end is done with END keyword followed by the keyword COMPONENT.
8. Which of the following is the correct syntax for component instantiation?
a) instantiate : component_name PORT MAP ;
b) label : instantiate COMPONENT PORT MAP ;
c) label : component_name PORT MAP ;
d) label : instantiate component_name PORT MAP
Answer: c
Explanation: Component instantiation is done in the architecture part by using some label and the function called PORT MAP. The name of the component is followed by the function PORT MAP . The arguments list of the function contains the name of ports in the same order as they were declared. By using this we can define the interconnection between ports.
9. It is possible to use a component twice which was declared only once.
a) True
b) False
Answer: a
Explanation: There is no restriction on the number of times a component can be used whose declaration is done. It is needed to be declared only once. Just using two or more different labels, we can use the same component again and again.
10. Which of the following must be known to describe a structural model in VHDL?
a) Number of inputs and outputs
b) Components and their connections
c) Relation between inputs and outputs
d) Value of output for different input combinations
Answer: b
Explanation: It is necessary to know the whole circuit at the component level and how these components are interconnected with each other. Since structural model describes the input and output ports of a design, so we need the components and their connections.
This set of VHDL Questions and Answers for Experienced people focuses on “Structural Modeling – 2”.
1. In which part of the VHDL code, components must be declared?
a) Library
b) Entity
c) Architecture
d) Configuration
Answer: c
Explanation: The component can be declared only after entity declaration or in the package itself. So, components can be declared either in architecture or in package. If the component is declared in package, then just include the package and don’t declare it again in architecture body.
2. Which of the following function is used to map the component?
a) COMPONENT INSTANTIATE
b) PORT MAP
c) GENERIC MAP
d) USE
Answer: b
Explanation: To map a component in the circuit, first it needs to be declared. Once it is declared, one can use the PORT MAP function to map the port on the design. This function can have as many arguments as the number of ports in the component.
3. How many ways are there in VHDL to map the components?
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: There are two ways by which one can map the components in VHDL design excluding the mapping of generic units. One method is positional mapping and another mapping is nominal mapping. Positional mapping is generally used mapping.
4. What is the property of Positional mapping?
a) Easier to write
b) Less error prone
c) Ports can be left unconnected
d) Difficult to write
Answer: a
Explanation: Positional mapping is a type of component mapping that is generally used in VHDL and it is easier to write. But, positional mapping has slightly more chances of occurrence of an error.
5. __________ mapping is less error prone.
a) Port
b) Positional
c) Nominal
d) Generic
Answer: c
Explanation: Nominal mapping has less chances of error since every port is assigned the specific value which is not the case with positional mapping. So, nominal mapping can take time but it is less prone to errors.
6. A component has 3 ports- two inputs and one output. Which of the following statement is for the positional mapping of the component?
a) LABEL : my_component PORT MAP ;
b) LABEL : my_component PORT MAP ;
c) LABEL : my_component PORT MAP ;
d) LABEL : my_component PORT MAP;
Answer: a
Explanation: A component can be instantiated by using positional or nominal mapping. In case of positional mapping, arguments are written, in this case, 3 arguments among which first two must be taken as input and last one is taken as output port. SO, only option a is using the positional mapping in which l and m corresponds to a and b respectively and n corresponds to y.
7. The ports of a component can be left unconnected.
a) True
b) False
Answer: a
Explanation: In VHDL, It is possible to leave any port unconnected. If our requirement is to leave a port unconnected in the circuit, then it can be done by using a keyword ‘OPEN’. By doing so, the port will not be connected to any input or output.
8. Which of the following is the right way to leave a port unconnected?
a) L1 : my_component PORT MAP; a <= OPEN;
b) L1 : my_component PORT MAP;
c) L1: my_component PORT MAP;
d) L1 : my_component PORT MAP; a := OPEN;
Answer: c
Explanation: To leave any port unconnected the keyword used Is ‘OPEN’. This keyword can be used only in the arguments of the function PORT MAP by using “=>” operator. Therefore, option c is the right way to use keyword OPEN.
9. It is not necessary that the order of the arguments in PORT MAP is taken as the order in which ports are declared.
a) True
b) False
Answer: b
Explanation: The order of arguments is taken as the order of ports declared in the component declaration in case of positional mapping. For example, the following statement declares a component-
COMPONENT my_component IS
PORT (
a, b, c : IN BIT;
x, y : OUT BIT);
END COMPONENT;
U1: my_component PORT MAP(p, q, r, s, t);
Here, in the component instantiation statement p, q, r, s and t will corresponds to a, b, c, x and y respectively because of the order used at the time of declaration is inherited in the component instantiation statement.
10. How to declare a 2 input OR gate in the structural modeling?
a)
COMPONENT or IS
PORT ( a, b : IN BIT;
x, y : OUT BIT);
END COMPONENT;
b)
COMPONENT or IS
PORT ( a, b : IN BIT;
y : OUT BIT);
END COMPONENT;
c)
COMPONENT or_gate IS
PORT ( a, b : IN BIT;
x, y : OUT BIT);
END COMPONENT;
d)
COMPONENT or_gate IS
PORT ( a, b : IN BIT;
y : OUT BIT);
END COMPONENT;
Answer: d
Explanation: For a 2 input OR gate, there must be 2 inputs and only one output. Therefore, some options are legal. But, the name of component can’t be same as any reserved word of VHDL. Therefore, a name of component can’t be ‘or’.
This set of VHDL Interview Questions and Answers for Experienced people focuses on “Structural Modeling – 3”.
1. Which of the following is the correct order for a structural model in VHDL?
a) Libraries, Entity declaration, Component declaration, Component instantiation
b) Libraries, Component declaration, Entity declaration, Component instantiation
c) Libraries, Entity declaration, Component instantiation, Component declaration
d) Component declaration, Libraries, Entity declaration, Component instantiation
Answer: a
Explanation: In a VHDL code, first of all, the packages and libraries are declared which are then followed by entity declaration. After the entity is declared, to model a circuit on the structural level, first all the components are declared after which they can be instantiated.
2. Refer to the model given below, which circuit is designed?
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY design IS
PORT(a, b, c : in BIT;
x, y : out BIT);
END design;
ARCHITECTURE arch1 OF design IS
COMPONENT xor2 IS
PORT (i1, i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
END COMPONENT;
COMPONENT and2 IS
PORT(a1, a2 : IN STD_LOGIC;
P : OUT STD_LOGIC);
END COMPONENT;
COMPONENT or2 IS
PORT(d1, d2 : IN STD_LOGIC;
r : OUT STD_LOGIC);
END COMPONENT;
SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC;
BEGIN
X1: xor2 PORT MAP(a, b, s1);
X2 : xor2 PORT MAP(s1, c, x);
X3: and2 PORT MAP(a, b, s2);
X4 : and2 PORT MAP(a, c, s3);
X5: and2 PORT MAP(b, c, s4);
X6: or2 PORT MAP(s2, s3, s5);
X7: or2 PORT MAP(s4, s5, y);
END arch1;
a) Half adder
b) Comparator 2- bits
c) Full adder
d) Can’t be determined
Answer: b
Explanation: Though it is not possible to determine the circuits through its structural model until its components are not specified. In the above case, the components are clearly 2 input AND, OR and EXOR gates. These gates are connected to give one output called x as the EXOR of three inputs a, b and c. Another output y = ab + bc+ ac. So, it is a full adder circuit designed.
3. There is a special function called interconnect to define interconnections between pins.
a) True
b) False
Answer: b
Explanation: There is no special function for defining interconnection between two or more inputs or outputs. These interconnections are defined by using port map only. When we use same port for two or more components then they are interconnected.
4. Refer to the architecture given below, there are two outputs called x and y. The structure defined is a full adder circuit. Which of the outputs corresponds to sum output of the adder?
ARCHITECTURE arch1 OF design IS
COMPONENT xor2 IS
PORT (i1, i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
END COMPONENT;
COMPONENT and2 IS
PORT(a1, a2 : IN STD_LOGIC;
P : OUT STD_LOGIC);
END COMPONENT;
COMPONENT or2 IS
PORT(d1, d2 : IN STD_LOGIC;
r : OUT STD_LOGIC);
END COMPONENT;
SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC;
BEGIN
X1: xor2 PORT MAP(a, b, s1);
X2 : xor2 PORT MAP(s1, c, y);
X3: and2 PORT MAP(a, b, s2);
X4 : and2 PORT MAP(a, c, s3);
X5: and2 PORT MAP(b, c, s4);
X6: or2 PORT MAP(s2, s3, s5);
X7: or2 PORT MAP(s4, s5, x);
END arch1;
a) y
b) x
c) s5
d) c
Answer: a
Explanation: Since there are three components which are two inputs EXOR gate, AND gate and OR gate. The signal s1 is the output of EXOR of a and b inputs. This signal is further used to EXOR with c and the output is y. So, y = a EXOR b EXOR c, which corresponds to the sum output of the full adder.
5. Which modeling style is used in code given below?
ENTITY design IS
PORT(a, b, c : in BIT;
x, y : out BIT);
END design;
Architecture arch OF design IS
BEGIN
x <= a XOR b XOR c;
y <= (a AND b) OR (b AND c) OR (a AND c);
END arch;
ARCHITECTURE arch1 OF design IS
COMPONENT comp1 IS
PORT (i1, i2 : IN STD_LOGIC;
o : OUT STD_LOGIC);
END COMPONENT;
COMPONENT comp2 IS
PORT(a1, a2 : IN STD_LOGIC;
P : OUT STD_LOGIC);
END COMPONENT;
COMPONENT comp3 IS
PORT(d1, d2 : IN STD_LOGIC;
r : OUT STD_LOGIC);
END COMPONENT;
SIGNAL s1, s2, s3, s4, s5 : STD_LOGIC;
BEGIN
X1: comp1 PORT MAP(a, b, s1);
X2 : comp1 PORT MAP(s1, c, x);
X3: comp2 PORT MAP(a, b, s2);
X4 : comp2 PORT MAP(a, c, s3);
X5: comp2 PORT MAP(b, c, s4);
X6: comp3 PORT MAP(s2, s3, s5);
X7: comp3 PORT MAP(s4, s5, y);
END arch1;
a) Behavioral and structural
b) Structural
c) Dataflow
d) Dataflow and Structural
Answer: d
Explanation: Since there are two architectures defined for the entity ‘design’. So, two modeling styles are used. In the first architecture, the data flow from inputs to outputs is described by using Boolean equations therefore, it is dataflow modeling. In the second architecture, components are declared and instantiated. So, it is structural model.
6. What is the correct syntax for mapping a GENERIC parameter in structural modeling?
a) label : component_name GENERIC MAP PORT MAP
b) label : component_name GENERIC MAP
c) label : parameter_name GENERIC MAP PORT MAP
d) label : parameter_name GENERIC MAP PORT MAP
Answer: a
Explanation: Generic is a constant parameter which can be used in structural modeling. But, generic is not a component as such. It can be used as a specification to any component. The correct syntax to use a generic is GENERIC MAP followed by a PORT MAP function.
7. It is possible to use a GENERIC parameter as a separate component.
a) True
b) False
Answer: b
Explanation: A Generic is just a constant and hence can’t have any input or output ports. It is only used with any component to describe its specification. For example, any component needs an array of input ports, the index value of that array can be defined by using generic parameter and that generic parameter can be used with PORT MAP to map the ports.
8. A component instantiation statement generates a _______ of the component.
a) Class
b) Behavior
c) Structure
d) Object
Answer: d
Explanation: By ending the component declaration, its object is created which can be used further in the code to use the declared component. The component instantiation statement uses this object and inherits the properties of component declared. These properties include all the ports and their number.
9. The structural code for 4-bit adder is given below.
COMPONENT adder IS
GENERIC (n : INTEGER := 3);
PORT(input : IN BIT_VECTOR(n DOWNTO 0);
output : OUT BIT_VECTOR(n DOWNTO 0));
END COMPONENT;
If user want to convert this in an 8 bit adder, which of the following variable should be changed?
a) n
b) input
c) output
d) component
Answer: a
Explanation: The only way to change it is by changing the value of n. If n is changed from 3 to 7, then it will have 8 input bits and 8 output bits. In this way, by using generic, the whole structure can be altered easily. Also, it may be noted if the value of the generic is not specified, then it will take the value used at the time of entity declaration.
10. What is the other name for implicit mapping?
a) Nominal mapping
b) Positional mapping
c) Explicit mapping
d) Inclusive mapping
Answer: b
Explanation: Implicit mapping is another name for positional mapping in which only ports are specified without using any assignments. Similarly, nominal mapping is the other name for explicit mapping which uses proper assignments to instantiate the component. In VHDL, there are only two types of mapping called Positional and nominal, there is no mapping called inclusive mapping.
This set of VHDL Questions and Answers for Freshers focuses on “Types of VHDL Modelling”.
1. What does modeling type refer to?
a) Type of ports in entity block of VHDL code
b) Type of description statements in architecture block of VHDL code
c) Type of data objects
d) Type of Signals
Answer: b
Explanation: Modeling refers to the descriptive style we are using to describe our digital system. Modeling type is the type of statement used in architecture block to describe a specific system or circuit. It may define a structure or behavior or anything else.
2. Which of the following is not a type of VHDL modeling?
a) Behavioral modeling
b) Dataflow modeling
c) Structural modeling
d) Component modeling
Answer: d
Explanation: VHDL modeling is of three types. These types are behavioral modeling, dataflow modeling and structural modeling. There is no such modeling called component modeling. However, one can declare components in structural modeling.
3. In behavioral modeling, what do descriptive statements describe?
a) How the system performs on given input values
b) How the design is to be implemented
c) Netlist
d) Concurrent execution
Answer: a
Explanation: Behavioral style specifies what a particular system does in a program. It gives the details of output values corresponding to the set of input values. In general, behavioral modeling use processes to describe the functioning of system, but no detail is provided regarding the design of the system.
4. Which of the following statement is used in structural modeling?
a) portmap
b) process
c) if-else
d) case
Answer: a
Explanation: In structural modeling, the graphical representation of the system is described. All the modules, instances or components are defined along with their interconnections. It is defined that how the components are connected to each other by using nets or wires. The portmap function is used to map the specific component in the design.
5. What is the basic unit of behavioral description?
a) Structure
b) Sequence
c) Process
d) Dataflow
Answer: c
Explanation: The primary unit of a behavior description in VHDL is process which describes the behavior of system on various combinations of inputs. All the system is described by using processes and therefore, process is the basic unit.
6. Which of the following modeling style follows the sequential processing of instructions?
a) Dataflow modeling
b) Behavior modeling
c) Structural modeling
d) Component modeling
Answer: b
Explanation: Behavior modeling uses sequential processing whereas dataflow and structural modeling uses concurrent statements. In sequential statements, the instructions are executed one after another whereas concurrent statements are executed simultaneously.
7. __________ modeling uses logic gates and basic blocks to describe the functionality of system.
a) Behavioral
b) Structural
c) Dataflow
d) Component
Answer: c
Explanation: In dataflow modeling, the system is represented as flow of control and movement of data. It describes how data flows from input to output by using primitive logic functions. Unlike behavioral modeling, it uses concurrent statements and logic functions.
8. Structural style use processes.
a) True
b) False
Answer: b
Explanation: Structural style does not use processes since it just describe the graphical representation of system. It doesn’t need process statements. Process statements are required to describe the behavior and not structure. Therefore, structural doesn’t need processes.
9. Component instantiation is the part of __________ modeling.
a) Behavior
b) Component
c) Dataflow
d) Structural
Answer: d
Explanation: Component declaration and component instantiation is a part of structural modeling. It first declares the component and then instantiation takes place by using portmap function. Structural modeling is based on netlist.
10. Which of the following architecture defines the data flow modeling of ‘and’ gate?
a)
ARCHITECTURE and_1 OF and_gate IS
begin
y <= a AND b;
end and_1;
b)
ARCHITECTURE dataflow OF and_gate IS
Process(a, b, y);
begin
y <= a AND b;
end dataflow;
c)
ARCHITECTURE and_1 OF and_gate IS
begin
IF(a = ‘1’ and b = ‘1’) THEN
c <= 1;
ELSE c <= ‘0’;
end and_1;
d)
ARCHITECTURE dataflow OF and_gate IS
begin
y <= a AND b;
end and_1;
Answer: a
Explanation: Dataflow uses primitive and basic functions to describe the flow of data through registers from inputs to output. It uses concurrent statements and process is a sequential statement which can’t be used in data flow modeling. It is not necessary to write the name of ARCHITECTURE as ‘dataflow’.
11. Refer to the code given below, which type of modeling is used to describe the system?
ARCHITECTURE and_1 OF and_gate IS
begin
process(a, b, y)
begin
IF(a = ‘1’ and b = ‘1’) THEN
y <= ‘1’;
ELSE y <=’0’;
end IF;
END process;
END and_1;
a) Structural
b) Component
c) Dataflow
d) Behavioral
Answer: d
Explanation: Above shown code is for AND gate and it is using process statement. The code gives information about output values for different combinations of input values. Therefore, the code given is behavioral style of modeling.
12. Which logic function is described in the code given below?
ARCHITECTURE my_func OF my_logic IS
begin
process(a, b, y)
begin
IF(a = ‘0’ and b = ‘0’) THEN
y <= ‘0’;
ELSIF (a = ‘1’ and b= ‘1’) THEN
y<= ‘0’;
ELSE y <= ‘1’;
END if;
END process;
END my_func;
a) AND
b) EXOR
c) OR
d) EXNOR
Answer: b
Explanation: The modeling shown is behavioral modeling. The output y is low for 00 and 11 else the output is high. Therefore, the given logic is for exclusive OR gate. Since in EXOR he output is high for 01 and 10 which is shown in the code given.
13. Which modeling style does the following code represents?
Architecture my_logic OF logic_func IS
Component gate_1
PORT (b1, b2 : IN BIT;
s : OUT BIT);
END component;
Component gate_2 IS
PORT (b1,b2 : IN BIT;
C : OUT BIT);
END component;
SIGNAL a, b, sum, carry : BIT;
begin
EXOR : gate_1 portmap (a, b, sum);
AND : gate_2 portmap (a,b ,carry);
END my_logic
a) Structural
b) Component
c) Behavior
d) Dataflow
Answer: a
Explanation: The code describes the every component present in the circuit, here gate_1 and gate_2 are two components and then it describes the inputs and outputs of the gates by using portmap function. In this way structural modeling describes all the functions and their interconnection. Moreover, it uses concurrent statements.
14. Ports are known as _________ to the component.
a) Structure
b) Behavior
c) Function
d) Interface
Answer: d
Explanation: Ports are used to declare the inputs and outputs of a specific component in the structural modeling. They act as an external interface of the component since it tells the number of input and outputs a component can have.
15. What is the use of a function called port map?
a) Component declaration
b) Defining identifiers
c) Component instantiation
d) Defining inputs and outputs
Answer: c
Explanation: The function portmap is used for component instantiation. By taking instances of input output ports declared at the time of declaration, the component is instantiated. Basically, to define the relation of component with the signals, we use portmap.
This set of VHDL Multiple Choice Questions & Answers focuses on “Signal Assignment – 1”.
1. The signal assignment is considered as a ________
a) Concurrent statement
b) Sequential statement
c) Subprogram
d) Package declaration statement
Answer: a
Explanation: The signal assignment statement is typically considered a concurrent statement rather than a sequential statement. However, the statement can be used as a sequential statement as well but has a side effect of obeying the general rules for when the left operand is actually updated.
2. How can we use an assignment statement as a sequential assignment?
a) By using keyword WAIT
b) By using a delay mechanism
c) By using conditional statements
d) By using it in any process
Answer: d
Explanation: The assignment statements can appear either in architecture or in a process. According to this only, the signal assignment is classified as a concurrent and sequential assignment. If the signal assignment is done in a process, then it is a sequential assignment, otherwise it is a concurrent assignment.
3. The sequential assignment statement is activated, whenever ________
a) The waveform associated changes its value
b) The process is terminated
c) The execution is scheduled
d) The value of the target is needed
Answer: b
Explanation: The sequential assignment statement appears inside a process. The statements inside the process are sequential statements and the assignment is activated when the process ends. So, the assignment will take place at the time of process termination only.
4. The concurrent assignment statement is activated whenever ______
a) The execution is scheduled
b) The value of the target is needed
c) The waveform associated changes its value
d) The process is terminated
Answer: c
Explanation: Concurrent assignment statement has nothing to do with processes. It is executed whenever the waveform associated with it changes its value. The value of the target is updated every time the value of waveform changes.
5. Which of the following is correct syntax for a signal assignment statement ?
a) target <= {delay_mechanism} waveform;
b) target <= delay_mechanism waveform;
c) target <= delay_mechanism {waveform};
d) target <= {delay_mechanism} {waveform} value;
Answer: a
Explanation: The proper signal assignment is shown in option target <= {delay_mechanism} waveform;. The ‘target’ gets the value of ‘waveform’ by executing the delay mechanism. The delay mechanism is ,however, optional but is used most of the times for better timing performance of the circuit.
6. The conditional assignment statement is a _________ assignment.
a) Sequential
b) Concurrent
c) Selected
d) None of the above
Answer: b
Explanation: The conditional statement is a type of concurrent assignment statement in which the assignment is executed only if the condition specified is true. It may be noted that the condition is Boolean i.e. it may have only two values true or false.
7. Sequential assignments are synthesizable.
a) True
b) False
Answer: a
Explanation: Generally, sequential assignments are synthesizable by EDA tools. The assignment statement must be using some operators and types. The only case when these assignments are not synthesizable is when the types and operators are acceptable to the synthesis tools.
8. Delays are generally ignored in ________ assignments statements.
a) Concurrent
b) Conditional
c) Sequential
d) Selected
Answer: c
Explanation: Conditional and selected assignments are type of concurrent assignment. In case of concurrent assignments delays are usually taken into consideration. Whereas, there is no use of delays in sequential assignments since it is executed at the end of process. So, there is no need for delay in sequential assignments.
9. Which of the following can’t be a mode for target operand of assignment statement?
a) BUFFER
b) INOUT
c) OUT
d) IN
Answer: d
Explanation: The left operand of assignment statement, called the target operand is always assigned the value of another operand. There is no chance of using IN type target on the left side of an assignment statement. It is mandatory that the direction of target include output.
10. Which of the following is a variable assignment statement?
a) <=
b) :=
c) =>
d) ==
Answer: b
Explanation: To assign a value to variable, a variable assignment statement is used. The symbol used for variable assignment is ‘:=’ whereas when we assign some value to a signal, <= statement is used. In case of variables if we use <= instead of :=, there can be some problem with the delay mechanisms.
11. Which of the following is a keyword used for conditional assignment?
a) IF
b) WHEN
c) FOR
d) END
Answer: b
Explanation: Conditional statement is an assignment statement in which a condition is first tested and then assignment occurs. It uses the keyword WHEN to assign value to a signal conditionally. For example, y <= ‘1’ WHEN x = ‘0’. This is a conditional statement that will assign value 1 to signal y only when signal x is low.
12. For a signal used in sequential assignment, it can have _______ driver.
a) 1
b) 2
c) 3
d) 4
Answer: a
Explanation: Sequential assignment statement is the one that is used in a process. This statement is executed at the end of the process. No matter how many signal assignment statements are used, only the last one is taken into consideration. So, in a process, one signal can have only 1 driver.
This set of VHDL test focuses on “Signal Assignment – 2”.
1. The selected concurrent statement is equivalent to ________ sequential statement.
a) If else
b) Loop
c) Wait
d) Case
Answer: d
Explanation: Selected concurrent assignment statement is used when the target signal has to choose one value out of n values. This is similar to the case statement used in the process. It uses the keyword ‘SELECT’ to select one value.
2. Those statement which are placed under ________ are concurrent.
a) Process
b) Function
c) Architecture
d) Procedure
Answer: c
Explanation: VHDL code, in general, is a concurrent code. Only statements placed under Process, Function or Procedure are executed sequentially. All other statements are concurrent statements.
3. In case of concurrent assignment, order of statements doesn’t matter.
a) True
b) False
Answer: a
Explanation: Since execution of a concurrent statement is parallel and an assignment statement has to be executed whenever the signal associated with it changes its value. Therefore, there is no restriction on the order of the statements.
4. Which of the following can’t be implemented with concurrent statements only?
a) Multiplexer
b) Decoder
c) Adder
d) Counter
Answer: d
Explanation: In general, we use concurrent code to build combinational circuits and the reason is that order of statements is not a problem. So, we can’t use purely concurrent code to obtain sequential logic circuits due to use of clock and processes. Hence, counter can’t be designed by using concurrent code only.
5. Variable assignment statement executes in ______ time.
a) Immediately
b) After delay specified
c) After one clock cycle
d) After two clock cycles
Answer: a
Explanation: When a variable is assigned a value, the assignment executes in zero simulation time. In other words, it changes the value of variable immediately. Also, the delay mechanism is used in the signal assignment but not in variable assignment. Variable assignment doesn’t use any delay mechanism.
6. In the signal assignment statement, which delay is used?
x <= 1 AFTER 10ns
a) Transport delay
b) Inertial delay
c) Delta delay
d) Wire delay
Answer: b
Explanation: Inertial delay is the default delay in VHDL in which only last value is persisted ignoring all other delays. In the case of inertial delay, there is no need of specifying anything like we need to write TRANSPORT to specify the transport delay.
7. Inertial delay in Signal assignment is useful to ___________
a) Specify wire delay
b) Accumulate delay
c) Ignore input glitches
d) No use
Answer: c
Explanation: Inertial delay assignment takes only last assignment statement into consideration ignoring all the preceding assignments. So, any intermediate change will be ignored. Therefore, It is useful in ignoring input glitches.
8. Which of the following statement is a zero delay statement?
a) y <= x AFTER 10 ns
b) y <= TRANSPORT x AFTER 10 ns
c) y <= x
d) y := x AFTER 10 ns
Answer: d
Explanation: Signal assignment always have some amount of delay either inertial or transport. If there is no delay specified in signal assignment, even then the delta delay is used to assign value. Only variable assignment is executed immediately also the delay is ignored. Therefore, option d is zero delay statement.
9. Which of the following statement can’t be used to assign values in behavioral modeling of OR Gate?
a) Simple concurrent assignment
b) Sequential assignment
c) Conditional concurrent assignment
d) Selected concurrent assignment
Answer: d
Explanation: In the behavioral modeling, various output values are described w.r.t different combination of input values. A conditional concurrent assignment and selected concurrent assignment can add some condition for assigning values. Same can be done with sequential statements. By using simple concurrent statements, it is not possible to realize or gate.
10. Which of the following is not an assignment statement?
a) <=
b) :=
c) =>
d) :>
Answer: d
Explanation: There are three assignment statements in VHDL. <= is a signal assignment statement, := is used for variable assignment and => is used at the time of mapping the components and is used with ‘OTHERS’. These are 3 type of assignment operators.
11. OTHERS keyword is used with which kind of assignment?
a) Concurrent
b) Sequential
c) Selected
d) Conditional
Answer: c
Explanation: Selected concurrent assignment statement is used when you have to choose one value out of n values. In that case WHEN and OTHERS keywords are used. OTHERS is similar to the ELSE statement which will be selected when all the conditions are false.
12. The following code represents which of the logic gates?
WITH ab SELECT
y <= 1 WHEN “11”;0 WHEN OTHERS;
a) And gate
b) Or gate
c) Not gate
d) Nand gate
Answer: a
Explanation: Here, the selected signal assignment is used in which the output is getting the value 1 when both the inputs are 1. Otherwise, the output is 0. This is clearly the case of 2 inputs AND gate.
This set of VHDL Multiple Choice Questions & Answers focuses on “Process Statement – 1”.
1. Process is a _______ statement.
a) Concurrent
b) Sequential
c) Delay
d) Both concurrent and sequential
Answer: a
Explanation: Process statement itself is a concurrent statement. Since, the architecture of an entity can contain only concurrent statements, so, process is a concurrent statement. Basically, Process itself is a concurrent statement which includes sequential statement. The statements enclosed in a process statement are executed sequentially.
2. If there is more than one process in a VHDL code, How they are executed?
a) One after the other
b) Concurrently
c) According to sensitivity list
d) Sequentially
Answer: b
Explanation: All the processes in a design execute concurrently or in a parallel manner. However, at a given time, only one statement is executed within the process. More than one processes can execute in a parallel manner, but the same is not true for statements within a process.
3. A process has a declaration part.
a) True
b) False
Answer: a
Explanation: A process can have a declaration part followed by statement part. A process can have its local variables, constants, types or subtypes declared in it which will be visible to the process only. The local process variables can’t be used outside the process.
4. Local variables in a process can be declared __________
a) Anywhere within the process
b) After a sequential statement
c) Before the BEGIN keyword
d) After the BEGIN keyword
Answer: c
Explanation: BGIN keyword specifies the start of sequential statements. The process declaration part is an optional part and the variables must be defined before the BEGIN keyword. No declaration is allowed after the keyword BEGIN.
5. Which of the following is correct syntax for process declaration?
a)
{Label :} PROCESS
{process_declaration_part};
sensitivity_list;
BEGIN
sequential_statements;
END PROCESS {Label};
b)
PROCESS {sensitivity_list}
{process_declaration_part}
BEGIN
sequential_statements;
END PROCESS {Label};
c)
{Label :} PROCESS
{process_declaration_part}
BEGIN
sensitivity_list;
sequential_statements;
END PROCESS;
d)
{Label :} PROCESS {sensitivity_list}
{process_declaration_part}
BEGIN
sequential_statements;
END PROCESS {Label};
Answer: d
Explanation: A process is declared by using an optional label followed by keyword process and the list of signals to which process is sensitive. After which, there is a declaration part for the process and a statements section. Both parts are separated by keyword BEGIN. THEN, the process is terminated by using keyword END followed by Process.
6. Sensitivity list of a process contains __________
a) Constants
b) Signals
c) Variables
d) Literals
Answer: b
Explanation: A process has its sensitivity list containing the names of signals to which the process is sensitive. It can contain any number of signals which will trigger the process of change of value of any of these signals. It may not contain constants or variables, only signals are valid.
7. Which of the following statement is used when there are no signals in the sensitive list?
a) WHEN
b) IF ELSE
c) WAIT
d) CASE
Answer: c
Explanation: A process can be sensitive to one or more signals. These signals are either specified in the sensitivity list of the process. If there is no sensitivity list, then the signals used in WAIT statements are the signals to which process is sensitive.
8. What is the effect of the sensitivity list on the process?
a) Process executes when any of the signal in sensitivity list changes
b) Process executes sequentially when sensitivity list is specified
c) If there is no sensitivity list, then the process will not execute
d) Helps in simulation
Answer: a
Explanation: The sensitivity list contains those signals which affect the execution of the process. Whenever one or more statements inside the sensitivity list changes, the execution starts. So, the process is executed again and again whenever any value change. It starts from BEGIN keyword and all statements are executed serially and then it waits for change in any value.
9. It is mandatory to use a label for any process.
a) True
b) False
Answer: b
Explanation: The use of label is optional. The purpose of using label is just to improve the readability of code. If it is used, then at the end of the process the same label should be written. For example, if label L1 is used to start the process then at the end, it must be- END PROCESS L1.
10. If no signal in the sensitivity list is changed, then how many times the process will be executed?
a) 3
b) 2
c) 1
d) 0
Answer: c
Explanation: The process is executed at least once, no matter if the signal changes or not. At the time when the simulation is initiated, the process is triggered. After this one time execution of process, it waits for change in state of signals in sensitivity list.
11. Which of the following statements can be seen as sequential equivalent to the selected concurrent assignment?
a) IF ELSE
b) WAIT
c) WHEN
d) CASE
Answer: d
Explanation: The selected assignment is a concurrent statement and therefore, can’t be used inside a process. CASE statement is a sequential statement which can be seen as an equivalent to the selected assignment which chooses one of the n different signals or variables.
12. A __________ can’t be declared inside a process.
a) Signal
b) Variable
c) Constants
d) Subprograms
Answer: a
Explanation: The process has a declaration part in which everything can be declared except a signal. The variables, constants, types, subprograms can be declared in the process and the scope for variables declared in the process is local to the process itself.
This set of VHDL Quiz focuses on “Process Statement – 2”.
1. It is possible to use sensitivity list and wait statements in the same process.
a) True
b) False
Answer: b
Explanation: The sensitivity list and wait statements can’t be used simultaneously in the same process. One can either use sensitive list or wait statements in a process. Both of them are used to define the signals to which the process is sensitive. These sensitive signals execute process as an infinite loop.
2. The process can be __________ by using WAIT statements.
a) Suspended
b) Resumed
c) Suspended as well as resumed
d) Cannot be determined
Answer: c
Explanation: The signals used in WAIT statements are the statements which can also be declared in sensitivity list. These signals can be used to suspend as well as resume the process as many times as designer want.
3. A postponed process runs when ___________
a) All the other processes have completed
b) After completion of one particular process
c) Concurrently with all other processes
d) First of all processes
Answer: a
Explanation: A postponed process can be defined in VHDL-93. A postponed process runs when all the normal processes have completed at a particular point of time at the time of simulation. These processes can’t schedule any further events with zero delays.
4. Which of the following statement can’t be used inside a process?
a) WAIT
b) IF ELSE
c) Variable declaration
d) PORT MAP
Answer: d
Explanation: A process itself is a concurrent statement which can have only sequential statements. IF ELSE and WAIT statements can be easily used inside a process. Also, there is a declaration part of the process so variable declaration is possible. Only PORT MAP is not possible inside the process among the above options since it is a concurrent statement.
5. Which of the following signal cause the process to execute?
PROCESS (clr)
BEGIN
IF (clr = ‘1’) THEN
y <= ‘0’;
ELSE
y <= input;
END PROCESS;
a) input
b) y
c) clr
d) x
Answer: c
Explanation: The sensitivity list of the process contains only one signal which is ‘clr’. So, the process will be executed when the value of clr changes. Though value of input will be assigned to y once but change in value of ‘input’ will not cause execution of process again.
6. The value of y is initially 1 and it is changed after one delta cycle to 0. How many delta cycles will be taken to change the initial value of z, refer to the process given below?
PROCESS (y)
BEGIN
x <=y;
z <= NOT y;
END PROCESS
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: At the very beginning, the value of z is 0. After 1 delta cycle, the value of y changes which causes process to run again. So, in 2nd delta cycle process will be executed but assignments will be done after the execution of process is over. So, at the end of 2nd delta cycle, the assignments will be executed.
7. A combinational process must have all the _________ signals in its sensitivity list.
a) Input
b) Output
c) Declared
d) Used
Answer: a
Explanation: All the inputs must be used in the sensitivity list to get the desired list. Because if any of the input signal is updated then it is needed that the output also gets updated. To update any output, one needs to activate the process again which is possible only by the signals in the sensitivity list. Therefore, all the signals which it has to read or the input signals must be used in the sensitivity list.
8. There is no restriction on the number of wait statements inside a process.
a) True
b) False
Answer: a
Explanation: A process can have multiple WAIT statements and can be placed anywhere inside the process body. However, it can have only one sensitivity list but, there is no restriction on use of WAIT statements.
9. Which of the following circuit can’t be described without using a process statement?
a) Multiplexer
b) D flip-flop
c) Decoder
d) Comparator
Answer: b
Explanation: Since a flip flop requires a clock signal which can’t be used directly in architecture without using a process . So, for using the clock, using a process is mandatory. All the other circuits like multiplexer, decoder or comparator are combinational circuits and do not need any clock. So, they can be modeled without using a process.
10. Which of the following signal uses keyword EVENT?
a) Variables
b) Output
c) Input
d) Clock
Answer: d
Explanation: To use a clock signal in a design description, EVENT is used. It is used inside the process body which indicates the change in value of clock signal so that the design can be synchronized with the clock signal or clock frequency. It can be used in an IF statement to assign any input expression to the output.
11. Refer to the code given below, what kind of circuit is designed?
SIGNAL x : IN BIT;
SIGNAL y : OUT BIT;
SIGNAL clk : IN BIT;
PROCESS (clk)
BEGIN
IF (clk’EVENT and clk = ‘1’)
y ;<= x;
END PROCESS
a) Buffer
b) Latch
c) Flip flop
d) Shift Register
Answer: c
Explanation: It is clear from the code that it is a sequential circuit using clock EVENT and the value of input is assigned to the output directly. So, it can’t be a buffer since buffer doesn’t need any clock signal. So, It is a synchronized flip flop. Clearly, It can be said that the given flip flop is a D flip flop.
12. The driver of signal y is _________
PROCESS ()
BEGIN
y <= ‘1’;
y <= x;
y <= z;
END PROCESS;
a) z
b) x
c) x and z
d) 1
Answer: a
Explanation: Since the assignment statements are appearing inside a process. Therefore, they are sequential assignment statement. A signal being assigned a value inside a process can’t have multiple drivers. It can have only one driver since only last statement is taken into consideration. So, the signal y is driven by signal z.
13. The resolution function is needed to resolve the value of _______
PROCESS ()
BEGIN
y <= x;
y <= z;
END PROCESS;
a) z
b) y
c) x
d) No x, y and z
Answer: d
Explanation: Since these assignments are appearing inside a process so no signal can have more than one driver. A resolution function is needed only if the signal has multiple drivers. However, if these statements were used outside the process, then the resolution function was required to resolve the value of y.
This set of VHDL Multiple Choice Questions & Answers focuses on “IF Statement”.
1. What kind of statement is the IF statement?
a) Concurrent
b) Sequential
c) Assignment
d) Selected assignment
Answer: b
Explanation: IF statement is a sequential statement which appears inside a process, function or subprogram. This statement is used to execute some block of statements if a condition executed comes to be true.
2. Which of the following keyword is not associated with IF statement?
a) ELSE
b) THEN
c) ELSIF
d) WHEN
Answer: d
Explanation: The IF statement can use the keywords ELSIF, THEN and ELSE but not the keyword WHEN. IF statement is followed by a condition which is followed by the keyword THEN. After which to add more conditions one can use ELSIF and ELSE keywords.
3. Which of the following represents the correct order for keywords?
a) IF, THEN, ELSIF, THEN, ELSE
b) IF, ELSE, THEN, ELSIF, THEN
c) IF, ELSIF, THEN, ELSE, THEN
d) IF, THEN, ELSE, THEN, ELSIF
Answer: a
Explanation: In case of IF statement, the keyword IF is followed by the condition and then the keyword THEN. After this any other condition is entered by using ELSIF keyword and all the other exceptions are handled by using ELSE keyword. So, the correct order is shown in option a which is IF, THEN, ELSIF, THEN, ELSE.
4. What is the correct syntax for defining an IF statement?
a)
IF (condition) THEN
statements;
ELSIF (condition) THEN
statements;
….;
ELSE (condition) THEN
statements;
END IF;
b)
IF (condition) THEN
statements;
ELSIF (condition) THEN
statements;
….;
ELSE
statements;
END IF;
c)
IF (condition) THEN
statements;
ELSIF (condition) THEN
statements;
….;
ELSE (condition)
statements;
END IF-ELSE;
d)
IF (condition) THEN
statements;
ELSIF (condition) THEN
statements;
….;
ELSE
statements;
END IF-ELSE;
Answer: b
Explanation: For a sequential IF statement, the condition is evaluated and if it is found to be true then the statements under IF are executed and after that the sequence of ELSIFs is used and finally an ELSE is used and it is ended by using END keyword followed by IF.
5. If the condition of IF statement is an expression, then what should be the type of the result of the expression?
a) Bit
b) Std_logic
c) Boolean
d) Integer
Answer: c
Explanation: It doesn’t matter what is the type of the expression, the result must be of Boolean type. It can have only two values which may be either TRUE or FALSE. If the result is true, THEN the statements under IF are executed otherwise ELSE is executed.
6. In the following lines, what should be the value of signal y, if a and b both are at logic high?
PROCESS (a, b)
BEGIN
IF( a XOR b <=’1’)
y <= ‘1’;
ELSIF (a AND b <= ‘0’)
y <= a;
ELSE
y <= ‘0’;
END IF;
END PROCESS;
a) a
b) b
c) 0
d) 1
Answer: c
Explanation: At the time of synthesis, first the condition of IF statement is tested and it is found to be FALSE, so the statements under IF statements are skipped and the condition of ELSIF is tested. That condition again comes to be FALSE and hence the statement under else is executed. So, y is assigned 1.
7. It is possible to use nested IF in VHDL.
a) True
b) False
Answer: a
Explanation: Like other traditional languages, it is possible to use an IF statement inside another IF statement. In this case, when one IF statement is used inside another IF statement, this is called the nested IF statement. This allows to use more than one condition simultaneously.
8. Which of the following condition has topmost priority?
a) IF
b) ELSIF
c) ELSE
d) THEN
Answer: a
Explanation: IF has the topmost priority which means the remaining block will be executed only if the condition under IF gives FALSE. Otherwise, if it is true, then the block is shifted until END IF statement. After the IF condition, the next priority is ELSIF condition. ELSE is executed only if every preceding condition is FALSE.
9. What logic is described in the following logic?
PROCESS (a, b)
IF (a = ‘1’ AND b = ‘0’ OR a= ’0’ AND b = ‘1’) THEN
y <= ‘1’;
ELSIF (a = ‘1’ AND b= ‘1’) THEN
y <= ‘0’;
ELSE
y <= ‘0’;
END IF
a) EXOR
b) EXNOR
c) AND
d) NOR
Answer: a
Explanation: Here, in the given code, the output is 1 if either a is 1 or b is 1. In the ELSIF, the condition is that the output will be zero if both the inputs are 1. So, both inputs can’t be high at the same time. Therefore, the logic described is exclusive OR logic.
10. One IF statement can have multiple ___________
a) IF
b) ELSIF
c) ELSE
d) CASE
Answer: b
Explanation: It is possible to have multiple ELSIF parts within one IF – END IF block. The IF statement can have multiple ELSIF parts but can have only one ELSE statement part. ELSE part will be executed after each of the ELSIF part is checked and found to be FALSE.
11. More than one sequential statement can exist between each statement part.
a) True
b) False
Answer: a
Explanation: Yes, It is not necessary that within a single IF or ELSIF, only one sequential statement is allowed. Multiple statements can be there between each statement part. Unlike, traditional languages it doesn’t need {} to write multiple statements.
12. If a user gets an error at the time of simulation which is “ the IF statement is illegal” what could be the reason?
a) Using IF statement in architecture body
b) Using IF statement without ELSE
c) Using multiple ELSE statements
d) Using concurrent assignment in the IF
Answer: a
Explanation: It is not allowed to use IF in the architecture body directly. IF statement is a sequential statement and hence can be used in a process, function or procedure. However, using IF statement without ELSE is not any error, doing this is possible. The only error is that it can’t be used in the concurrent.
13. In a clocked process, IF statement is used to __________
a) To run statements sequentially
b) To use concurrent assignment within process
c) To detect the clock signal
d) To implement sequential circuit
Answer: c
Explanation: A clocked process is the process which uses a clock signal to design the circuit. In such process one may need to detect the rising or falling edge of the clock. For this purpose, IF statement can be used to detect the occurrence of a clock.
14. What will be the output in the following code?
ARCHITECTURE my_logic OF my_design IS
BEGIN
a <= 1;
b <= 1;
PROCESS (a, b)
BEGIN
IF (a AND b = 1) THEN
output <= a;
ELSIF (a OR b = 1) THEN
output <= b;
ELSE
output <= 0;
END IF;
END PROCESS;
END my_logic;
a) 0
b) 1
c) b
d) a
Answer: d
Explanation: Since the condition under IF is true so the statements under IF will be executed and hence output will be assigned the value of signal a. Though the condition under ELSIF is also TRUE but IF has the highest priority so all the following ELSIFs will be ignored. This is the problem in IF statement.
This set of VHDL Multiple Choice Questions & Answers focuses on “Case Statement – 1”.
1. What is the problem with IF statement?
a) Overlapping of conditions
b) No default value
c) The condition can be Boolean only
d) Restriction on number of ELSE statement
Answer: a
Explanation: The IF statement has a priority according to which conditions are being tested. Whenever it is found to be true, all the following ELSIF statements are skipped and the END IF is executed. Sometimes, it is possible that two conditions may overlap which can cause a change in output and we may not get the output as expected.
2. In which of the following statements, all the branches are equal in priority?
a) IF
b) CASE
c) WAIT
d) LOOP
Answer: b
Explanation: Only IF and CASE statements have branches. Among which IF statement has a priority scheduled which is IF, then ELSIF sequentially and ELSE at the lowest priority. Unlike the IF statement, CASE statement has no priority. All the branches are equal in priority and all the cases are covered. Due to this, it is obvious that there must not be any overlaps.
3. In case any of the conditions is not covered by ‘cases’ in the case statement, which of the following keyword can be used to cover all those conditions?
a) ELSE
b) ELSIF
c) REMAINING
d) OTHERS
Answer: d
Explanation: All the possible values, which a CASE expression can take, must be covered. For covering all the remaining values, which are not specified, the keyword OTHERS is used.
4. CASE is a sequential statement, which is similar to _________ concurrent statement.
a) Concurrent assignment
b) PORT MAP
c) WHEN
d) THEN
Answer: c
Explanation: CASE is similar to a selected signal assignment where the keyword WHEN is used along with the assignment statement. In case of sequential code, CASE can be used for the same purpose. Both CASE and WHEN uses the keyword OTHERS to handle the remaining permutations.
5. Which of the following is correct syntax for CASE statement?
a)
CASE expression IS
WHEN choice_1 <=
Sequential_statements;
WHEN choice_2 <=
Sequential_statements;
….
WHEN OTHERS <=
Sequential_statements;
END CASE;
b)
CASE expression IS
WHEN choice_1 =>
Sequential_statements;
WHEN choice_2 =>
Sequential_statements;
….
WHEN OTHERS =>
Sequential_statements;
END CASE;
c)
CASE expression IS
IF choice_1 <=
Sequential_statements;
ELSIF choice_2 <=
Sequential_statements;
….
ELSIF OTHERS <=
Sequential_statements;
END CASE;
d)
CASE expression IS
IF choice_1 =>
Sequential_statements;
ELSIF choice_2 =>
Sequential_statements;
….
ELSIF OTHERS =>
Sequential_statements;
END CASE;
Answer: b
Explanation: The CASE statement is started with the keyword CASE followed by any identifier or expression and the IS. The expression is solved to get the value and the result of expression is matched with the choices and when it is matched, the corresponding sequential statements are executed. If the value doesn’t match any of the choices, then the statements under OTHERS are executed. It may be noted that the choices are followed by the operator => but not <=.
6. The expression used in a keyword must be of a Boolean type.
a) True
b) False
Answer: b
Explanation: Unlike IF, it is not necessary that the expression used must give a Boolean value. It can be of any type. There is no such restriction on the type of expression used. It can be Integer, Character, Bit, Std_logic. There is no specific type of expression.
7. What will be the value of Z in the following code?
ENTITY case_1 IS
Port (a, b, c, y : IN INTEGER range 0 TO 31
z : OUT INTEGER range 0 TO 31)
ARCHITECTURE example OF case_1 IS
BEGIN
y <= 2;
a <= 4;
b <= 5;
c <=6;
PROCESS(a, b, c, y)
BEGIN
CASE y+1 IS
WHEN 1 =>
z <= a;
WHEN 2 =>
z <= b;
WHEN 3 =>
z <= c;
WHEN OTHERS =>
Z <= 0;
END CASE;
END PROCESS;
END example;
a) 2
b) 4
c) 5
d) 6
Answer: d
Explanation: First of all the expression is solved to get an integer, which is 3. Now, integer 3 is matched with the choices and the corresponding assignment will be executed. Therefore, c will be assigned to z since the choice 3 is matched with the outcome of the expression. In this way the z will get the value of c which is 6.
8. What should be the type of choices in the CASE statement?
a) Boolean
b) Integer
c) Same as expression
d) No restriction on the type
Answer: c
Explanation: It is necessary that the type of choices in the CASE statement is same as the type of expression in the same. For example, any expression is of type integer, and then all the choices must be of the type integer.
9. It is possible to use a range in the choice part of the CASE statement.
a) True
b) False
Answer: a
Explanation: This is possible to use a discrete range in the choices. It is not necessary that the choice can be a single integer or character only, it can be a range too. This can be done by using TO keyword. For example, WHEN 1 TO 3 is valid in which if the expression gives the value anywhere between 1 to 3, then this part of the CASE will be executed.
This set of VHDL MCQs focuses on “Case Statement – 2”.
1. If one wants to perform no action, when any condition is true, then which of the following keyword can be used?
a) NO OPERATION;
b) NOP;
c) NULL;
d) NEXT;
Answer: c
Explanation: A NULL statement is generally used in CASE statement. The system will ignore the null statement and proceed to the next statement. This statement is used to explicitly state that no action is to be performed when a condition is true. Generally, this can be used in the OTHERS part of the CASE block.
2. It is not possible to use range with _________ types.
a) Integer
b) BIT_VECTOR
c) STD_LOGIC
d) Natural
Answer: b
Explanation: The range used in the choices must be a discrete range. We can use the range in every data type but not with vector types. For example, if we write WHEN 000 TO 010 THEN, it will be an illegal statement. This is not synthesizable and will get an error as well.
3. The CASE statement in VHDL is similar to _________ in C.
a) Switch
b) If else
c) Pointers
d) Arrays
Answer: a
Explanation: In traditional programming languages like C, a Switch statement is used which is similar to the CASE statement of VHDL. In Switch, like CASE, one value from multiple possible values is chosen and the respective code is executed.
4. Which of the following operators can’t be used in the choices of a CASE?
a) Arithmetic
b) Logical
c) Relational
d) Every type of operators can be used
Answer: c
Explanation: The choices can’t include a Relational operator in it such as less than or greater than operators. Use of these operators can result in overlapping of conditions which is not allowed in the CASE statement.
5. It is possible to use a CASE statement without OTHERS.
a) True
b) False
Answer: a
Explanation: The OTHERS clause is used to cover all the remaining choices. In case, when one is sure that no choice is remaining, then the OTHERS clause has no use. Then the OTHERS clause is of no use.
6. What is the main use of a CASE statement?
a) To design multiplexers
b) To design Comparators
c) To design Flip flop
d) To design state machines
Answer: d
Explanation: CASE is basically used in the design of state machines. Since there are various combinations of present state and next states due to which there are various choices to select from. That’s why CASE is used in the modeling of state machines.
7. Which of the following is most complex?
a) IF THEN ELSE
b) Nested IF THEN ELSE
c) ELSIF
d) CASE
Answer: b
Explanation: The nested IF ELSE statement is most complex statement. Since it needs to define If again and again inside another ELSE statement. This is the equivalent of ELSIF clause but is more complex. Using ELSIF is easier than using nested IF ELSE.
8. Which of the following is not a legal statement used Ii CASE?
a) WHEN 1 =>
b) WHEN 1 TO 3 =>
c) WHEN 1|3 =>
d) WHEN 1 THEN
Answer: d
Explanation: The CASE statement can either use a single value or a discrete range followed by the => operator. Apart from this, | is called the or operator which means there are two values of choices are used. In option d THEN is used instead of => which is illegal.
9. CASE is more efficient than ELSIF.
a) True
b) False
Answer: a
Explanation: Since CASE uses a single block to define multiple choices and there is no overlapping between two choices. The overlapping is possible in case of ELSIF. Therefore, the CASE statement is more efficient and less complex than ELSIF clause.
This set of VHDL Multiple Choice Questions & Answers focuses on “LOOP Statement – 1”.
1. A loop statement is used where we needs to ________
a) Select one from many choices
b) Check a condition
c) Repeat the statements
d) Choose one from two cases
Answer: c
Explanation: As the name suggests, a loop statement includes a sequence of statements which have to be executed repeatedly zero or more times. There are different iteration schemes available to generate loops in which some condition may be included to generate a finite loop.
2. Loop is a ________ statement.
a) Concurrent
b) Sequential
c) Assignment
d) Functional
Answer: b
Explanation: Like IF, WAIT, CASE, LOOP is also intended exclusively for sequential code. It is a sequential statement which can be used inside a process, function or procedure only.
3. How many styles of loop statement does the VHDL have?
a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: There are two different styles of the loop statement which are FOR LOOP and WHILE LOOP. These are called the iteration schemes. However, it is possible to define a loop without using these iteration schemes. In that case we need to use WAIT statement.
4. What is the use of FOR loop?
a) To repeat the statement finite number of times
b) To repeat the statement until any condition holds true
c) To repeat the statements for infinite time
d) To repeat statements inside until any condition is false
Answer: a
Explanation: FOR LOOP iteration scheme is used to repeat the statements enclosed within a fixed number of times. There is no condition used in the for loop, but a limit is set which must be static and the loop will run only given number of times.
5. Which of the following is correct syntax for defining FOR LOOP?
a)
label : FOR LOOP loop_specification
sequential_statements;
….
END LOOP label;
b)
label : FOR loop_specification LOOP
sequential_statements;
….
END FOR LOOP;
c)
label : FOR LOOP loop_specification
sequential_statements;
….
END FOR LOOP;
d)
label : FOR loop_specification LOOP
sequential_statements;
….
END LOOP label;
Answer: d
Explanation: The FOR LOOP is defined by using an optional label followed by a keyword FOR. After which the specification is defined which is the number of times loop should execute. This specification is followed by keyword LOOP. After this we can start writing sequential statements and the loop is ended with END LOOP and an optional label.
6. What is the use of WHILE loop?
a) To repeat the statement finite number of times
b) To repeat the statement until any condition holds true
c) To repeat the statements for infinite time
d) To repeat statements inside until any condition is false
Answer: b
Explanation: WHILE LOOP is repeated until a condition no longer holds. The condition is first tested and if it is found to be true then the loop iteration starts. With the end of iteration, the condition is again tested and the process continues until the condition is not false.
7. Which of the following is correct syntax for WHILE LOOP?
a)
label: WHILE LOOP specification IS
sequential_statements;
END LOOP;
b)
label: WHILE LOOP condition
sequential_statements;
END LOOP label;
c)
label: WHILE condition LOOP
sequential_statements;
END LOOP label;
d)
label: WHILE specification LOOP
sequential_statements;
END LOOP;
Answer: c
Explanation: WHILE loop can be declared by using an optional label followed by the keyword WHILE. After writing WHILE, the condition must be written, the loop will execute until the condition will be true. Otherwise, the loop will not execute.
8. What does the next statement in loops do?
a) Skips the current iteration
b) Starts the next loop by ending the current
c) Exits the loop
d) Skips the next line of the loop
Answer: a
Explanation: The next statement is used to skip the current iteration and start the next iteration of the same loop. This statement passes the control the statement which is enclosing the innermost loop. This statement is useful when one needs to perform some action for every value except one.
9. What is the syntax to use the NEXT statement?
a) NEXT condition loop_label
b) NEXT loop_label WHEN condition
c) loop_label NEXT WHEN condition
d) loop_label NEXT condition
Answer: b
Explanation: The next statement can be used by using the keyword NEXT followed by the loop label so that it can execute the next iteration by passing the control to the statement containing loop_label. Loop label is followed by keyword WHEN and one condition so that the iteration is skipped only when the condition is true. If there is no label given to the loop then there is no need to write the label in the NEXT statement. In that case, next statement applies to the innermost enclosing loop.
10. It is not possible to write an infinite loop in VHDL.
a) True
b) False
Answer: a
Explanation: Since VHDL is a hardware description language, so unlike traditional programming languages we can’t write an infinite loop. Actually PROCESS itself is an infinite loop that executes whenever any signal of sensitivity list changes. It is necessary to add some exit statement or a condition in every loop.
This set of VHDL Multiple Choice Questions & Answers focuses on “LOOP Statement – 2”.
1. The correct syntax for using EXIT in a loop is ___________
a) EXIT loop_label WHEN condition;
b) EXIT WHEN condition loop_label;
c) loop_label WHEN condition EXIT
d) EXIT WHEN loop_label condition
Answer: a
Explanation: EXIT is the keyword used for the execution of EXIT statement. This keyword is followed by the optional loop label which again is followed by keyword WHEN and the condition which should by true for ending the loop. If the loop label is absent, then the exit statement automatically applies tot the innermost enclosing loop.
2. FOR loop uses a loop index, the type of loop index is _________
a) STD_LOGIC_VECTOR
b) BIT_VECTOR
c) INTEGER
d) REAL
Answer: c
Explanation: The loop index is used as a counter which counts the number of iterations and this loop index is an INTEGER by default. This is because by using an integer, the counting can be done easily which is not possible with real numbers.
3. Where do we declare the loop index of a FOR LOOP?
a) Entity
b) Architecture
c) Library
d) It doesn’t have to be declared
Answer: d
Explanation: The loop index doesn’t have to be declared because it is always an integer and can be directly used in a loop. So, it is locally declared for a loop. For example, FOR x in 1 TO 10 LOOP; Here ‘x’ is the loop index. Also, it can be reassigned a value within the loop.
4. A FOR loop is inside a WHILE loop. Inside the FOR loop, the EXIT statement is used in such a way that after 4 iterations, it will execute. After the execution of EXIT statement, the control will be passed ________
a) Outside the FOR loop
b) Outside the WHILE loop
c) At the next iteration of WHILE loop
d) At the next iteration of FOR loop
Answer: a
Explanation: If the loop is nested inside another loop, then exit statement will end the innermost loop only. It will not end the execution of all the loops. It will start execution from the innermost statement containing END LOOP. So, the control will be passed to the statement next to the end of FOR loop.
5. A for loop is initiated as given below, in total how many iterations will be there for the FOR loop?
FOR i IN 0 TO 5 LOOP
a) 3
b) 4
c) 5
d) 6
Answer: d
Explanation: As told earlier, i is the loop index which is integer by default. So, the counting will start from 0 and then 1 and so on till 5. Therefore, the loop will execute 6 times. If one wants to execute it 5 times then either 0 to 4 or 1 to 5 should be used.
6. All types of FOR loops are synthesizable.
a) True
b) False
Answer: b
Explanation: The loop index in FOR loop must contain a static value only. It is not possible to synthesize the design if the loop range is not static or it is a variable. So, we can’t use a variable in the loop range line otherwise the loop will not be synthesizable.
7. What is the use of EXIT statement in a loop?
a) For skipping one execution
b) For repeating one statement in the loop
c) For ending the condition and creating infinite loop
d) For ending the loop
Answer: d
Explanation: The exit statement completes the execution of an enclosing loop statement and passes the control to the statement after the exited loop. It will skip all the following iterations and starts execution after the statement containing END LOOP.
8. On what side of the assignment statement, one can use a loop index?
a) Left
b) Right
c) Left or Right
d) Loop index can’t be used in an assignment
Answer: b
Explanation: The loop index can be used on the right side of the assignment only. It has read only access. It means that we can’t use index as an output signal. However, it is possible to use this variable as an index to some vector type.
9. A WHILE loop is more flexible than FOR loop.
a) True
b) False
Answer: a
Explanation: Since we can’t use a signal or variable in the loop range statement, so the FOR loop always runs for a specified or constant number of times. Whereas a WHILE loop can be used to run a loop and we don’t need to know that how many times the loop must be executed.
10. The FOR loop is not synthesizable if it contains ______ statement.
a) WHEN
b) THEN
c) WAIT
d) IF
Answer: c
Explanation: The FOR loop is not synthesizable for two conditions. One is That the loop variable must be static. Another condition for the loop to be synthesizable is that it must not contain any kind of WAIT statement.
11. Which logic circuit is described in the following code?
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY system IS
GENERIC (l : INTEGER := 3);
PORT ( a, b : IN STD_LOGIC_VECTOR ( l DOWNTO 0);
c : IN STD_LOGIC;
x : OUT STD_LOGIC_VECTOR (l DOWNTO 0)
y : OUT STD_LOGIC);
END system;
ARCHITECTURE design OF system IS
BEGIN
PROCESS (a, b, c)
VARIABLE z : STD_LOGIC_VECTOR ( l DOWNTO 0);
BEGIN
z(0) := c;
FOR I IN 0 TO l LOOP
x(i) < = a(i) XOR b(i) XOR z(i);
z(i+1) <= (a(i) AND b(i)) OR (a(i) AND z(i)) OR (b(i) AND z(i));
END LOOP;
y <= z(l);
END PROCESS;
END design;
a) 4-bit full subtractor
b) 4-bit half subtractor
c) 4-bit half adder
d) 4-bit full adder
Answer: d
Explanation: The design shown in the architecture is the design of 4-bit ripple carry full adder. A generic parameter ‘l’ is used to define the number of bits and for loop is used to describe the data flow of adder. The ‘x’ output is corresponding to the sum output of the adder with 4 bits. Similarly, y output corresponds to the output carry of the adder with one bit only.
This set of VHDL Multiple Choice Questions & Answers focuses on “Assert Statement”.
1. Assert statement is a _____________ statement.
a) Concurrent and synthesizable
b) Sequential and synthesizable
c) Concurrent and Non-synthesizable
d) Sequential and Non-synthesizable
Answer: d
Explanation: Assert statement is a sequential statement which can appear inside a process, function or procedure. Also, this statement is a non-synthesizable statement which is used to report some textual string to the designer.
2. What is the use of assert statement in VHDL?
a) To print any string
b) To check the consistency and generate a message
c) Cause execution of sequential statements to wait
d) To check if a condition can stop the execution
Answer: b
Explanation: ASSERT statement is used to check the consistency of the program. It checks a condition and generates a message which is printed on the screen depending on the status of the condition whether it is true or false.
3. What is the correct syntax for using ASSERT statement?
a) ASSERT condition [REPORT string] [SEVERITY name];
b) Condition [REPORT string] [SEVERITY name] ASSERT;
c) Condition [SEVERITY name] [REPORT string] ASSERT;
d) ASSERT condition [SEVERITY name] [REPORT string];
Answer: a
Explanation: The ASSERT statement is declared by using a Boolean condition before which a keyword ASSERT is used. After the condition, a keyword called REPORT is used and the string is specified which the user wants to display. The string to be displayed is followed by the severity of the error and its name.
4. The assert statement displays a message when the condition is FALSE.
a) True
b) False
Answer: a
Explanation: The assert statement does nothing if the condition specified is true. If it is false, only then the message which is specified by the user is displayed on the screen. It is basically used for the status check of the program whether it is running correctly or not.
5. What is the use of REPORT statement?
a) To check the consistency
b) To make the statement wait
c) To print any string or output the string
d) To report the failure
Answer: c
Explanation: The REPORT statement is used to output any message to the screen. It is generally used in conjunction with the ASSERT statement where ASSERT checks the consistency and REPORT outputs the message specified by a user.
6. How many types of severity levels are there for the ASSERT statement?
a) 1
b) 2
c) 3
d) 4
Answer: d
Explanation: There are four severity levels in the assert statement. There can be four names of SEVERITY which are NOTE, WARNING, ERROR and FAILURE. Depending on these severity levels, the simulator is instructed to halt.
7. Which of the following is the default severity name for ASSERT?
a) NOTE
b) WARNING
c) ERROR
d) FAILURE
Answer: c
Explanation: The default severity level is ERROR. This means if we haven’t specified any severity level then it will be considered as ERROR severity.
8. By using which of the following severity level, the simulator can be halted?
a) NOTE
b) WARNING
c) ERROR
d) FAILURE
Answer: d
Explanation: In general, the simulator will generate a list of assert failures or the number of assert statements in which the condition was found to be false and shows at the end of the simulation. But, in the case of FAILURE severity, the simulator can stop working or it can come to a halt.
9. What kind of circuit may be described by using the following statement?
ASSERT NOT (s=’1’ and r = ‘1’) REPORT ‘’INVALID! S and R both can’t be 1” SEVERITY ERROR
a) Flip flop
b) Multiplexer
c) Decoder
d) Counter
Answer: a
Explanation: This can be a code for SR flip flop. Because the inputs S and R can’t be high at the same time in case of SR flip flop. It is invalid. ASSERT statement is used to show the same. When the condition is false then the message will be printed.
10. An ASSERT statement can’t be used as a concurrent statement.
a) True
b) False
Answer: b
Explanation: An ASSERT statement can be used outside a process. But, in that case it will behave as a postponed or passive process. In case of concurrent assertion, the simulator will monitor the condition continuously.
11. NOTE severity level can be used to __________
a) Stop the execution
b) Show the unusual situation
c) Pass a message from simulation
d) To give a warning to simulator
Answer: c
Explanation: The NOTE level has the lowest severity level which can be sued at the time of any small condition violation. This can be used to pass a message from the simulator.
12. Where should one use WARNING severity level?
a) To stop the execution
b) To alert the user about unexpected conditions
c) To pass the message from simulation
d) To give a warning about wrong conditions
Answer: b
Explanation: WARNING has the second lowest severity level and can be used in any unusual but not fatal situation. In the situations, where the simulation can be continued but the results cannot be predicted. For example, if any file is not opened as expected, in that case one may use a WARNING.
13. The use of ERROR severity is _________
a) To alert about unpredictable results
b) To pass information to the simulator
c) To Stop the execution
d) Where the simulation is not feasible
Answer: d
Explanation: In many cases, the simulation is not feasible or works completely incorrectly, there we can use the ERROR level severity. For example, when both inputs of SR flip flop are high, then the ERROR severity will be a good fit.
14. Where should we use FAILURE severity?
a) To identify a fatal error
b) To alert the user about simulation where the results are not correct
c) To ignore the error
d) To show the failure of simulation
Answer: a
Explanation: FAILURE is the top most severity and must be used where the assertion violation is a fatal error and it must be stopped at once. So, most catastrophic conditions must be shown by failure. For example, if the code of operation is illegal and can affect the whole design, then its better to halt the simulation.
This set of VHDL Multiple Choice Questions & Answers focuses on “WAIT Statements – 1”.
1. WAIT statement can’t appear under _______ directly.
a) Architecture
b) Process
c) Procedure
d) Subprogram
Answer: a
Explanation: WAIT statement is a sequential statement which is similar to IF statement and its more than one form are available. Since it is a sequential statement, it can appear inside a process, procedure or subprogram, but can’t appear under architecture. In architecture only concurrent statements can be used.
2. Which of the following can’t be used in a process when it has any WAIT statement?
a) IF
b) CASE
c) LOOP
d) Sensitivity list
Answer: d
Explanation: One can’t use a WAIT statement along with sensitivity list. It can either have a sensitivity list or some WAIT statements. However, IF, CASE and LOOP are some other sequential statements which can be used when the process has sensitivity list. WAIT statement also contain signals to which the process is sensitive.
3. How many forms of WAIT statement are there in VHDL?
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: There are three forms of WAIT statements among which all of them can be used for synchronous as well as asynchronous sequential code. Some sort of condition or time period is used to stop the execution of process and wait for some event to occur.
4. Which of the following is not the correct WAIT statement?
a) WAIT ON
b) WAIT WHILE
c) WAIT FOR
d) WAIT UNTIL
Answer: b
Explanation: WAIT ON, WAIT FOR and WAIT UNTIL are the three types of WAIT signals. There is no WAIT WHILE statement. WAIT ON, FOR and UNTIL are the different types which follow different syntax and different types of WAIT statement which suspends the process for some time.
5. WAIT UNTIL statements cause the process to wait ________
a) When a signal changes value
b) Until a condition is true
c) For a specific time period
d) When either a signal changes its value or a condition comes true
Answer: b
Explanation: WAIT UNTIL statement is a form of WAIT statement which causes the process to wait until a condition is true. It is mandatory that the type of condition used must be Boolean. It can be any kind of expression but the result must be of Boolean type.
6. What is the correct syntax for using a WAIT UNTIL statement?
a) WAIT UNTIL boolean_condition_or_expression;
b) WAIT UNTIL signal_name;
c) WAIT UNTIL time_value_or_expression;
d) WAIT UNTIL boolean_expression time_value;
Answer: a
Explanation: To write a WAIT UNTIL statement, a Boolean expression is used which causes the process to wait until the expression is true. Unlike IF, CASE and LOOP, the WAIT statement uses a semicolon at the end of the line.
7. What is the use of WAIT FOR statement?
a) To stop execution when the condition is false
b) To stop execution until a signal changes its value
c) To stop execution for a specific time period
d) To stop execution until the clock event occurs
Answer: c
Explanation: WAIT FOR statement is useful in the case when we want to suspend the process for a known time period. For example, a delay of 10 ns is used in case of a buffer execution then we can use a WAIT FOR statement.
8. How to define a WAIT FOR statement?
a) WAIT FOR signal_name;
b) WAIT FOR booelan_expression;
c) WAIT FOR clock_event;
d) WAIT FOR time_value;
Answer: d
Explanation: WAIT FOR statement can be used by writing the keyword WAIT FOR followed by a time expression. This time expression can be a simple value of time followed by units of time. Since the time is a physical literal of VHDL and its base unit is nanosecond . So, ns is mostly used. For example, WAIT FOR 100 ns; is the correct syntax for WAIT FOR statement.
9. Which of the following is the correct use of WAIT ON statement?
a) To stop execution until a signal changes its value
b) To stop execution when a signal changes its value
c) To stop execution when a condition specified is true
d) To stop execution when a condition specified is false
Answer: a
Explanation: The WAIT ON statement puts the process on a hold until any of the signal listed changes its value. This statement is thus useful in detecting the clock events and other similar events. For example, WAIT ON clk will cause the process to wait until a clock event takes place.
10. Which of the following is correct syntax for WAIT ON statement?
a) WAIT ON signal_assignments;
b) WAIT ON boolean_condition;
c) WAIT ON signal_list;
d) WAIT ON time_expression;
Answer: c
Explanation: The keyword WAIT is followed by a signal list which is similar to the sensitivity list of the process and the list is used to detect the events. Whenever any signal on the list changes the process resumes the execution.
This set of VHDL online test focuses on “WAIT Statements – 2”.
1. Which of the following statement uses only 1 signal?
a) WAIT FOR
b) WAIT UNTIL
c) WAIT ON
d) WAIT UNTIL and WAIT FOR
Answer: b
Explanation: In the case of WAIT UNTIL statement, there can be more than one condition but all conditions can use the same signal only. WAIT ON, on the other hand, accepts multiple signals. So, if a process has only one WAIT UNTIL statement then it can be concluded that the process is sensitive to only one signal.
2. Given that a process has no sensitivity list and has only one WAIT statement which is WAIT FOR statement. How many signals are there to which process is sensitive?
a) 0
b) 1
c) 2
d) Can’t be determined
Answer: d
Explanation: It is not necessary that we have to write the time value in WAIT FOR statement. One can also use an expression that will be first solved and then the resulting value will be taken as time value. In that case, we can’t say how many signals are used in the WAIT FOR statement. If the time value is directly given then the process has 0 signals in sensitivity list.
3. WAIT statement provides more flexibility than sensitivity list.
a) True
b) False
Answer: a
Explanation: Because the sensitivity list is always written at the starting of the process and this is not true in the case of WAIT statements. They can occur anywhere within the process. Moreover, there can be more than one WAIT statements in the process.
4. Which of the following WAIT statement is most useful for implementing a synchronous sequential circuit?
a) WAIT ON
b) WAIT FOR
c) WAIT UNTIL
d) WAIT TIME
Answer: c
Explanation: WAIT ON statement accepts multiple signals whereas WAIT UNTIL statement can have only one signal. In case of the synchronous sequential circuit there is only one clock signal to which the circuit must be sensitive. Therefore, WAIT UNTIL is most suitable for implementing the synchronous circuits.
5. What is the deadlock condition in VHDL?
a) When WAIT statement keeps on waiting forever
b) When WAIT UNTIL statement uses more than one signal
c) When WAIT ON statement has only one signal
d) When WAIT FOR statement doesn’t have any time clause
Answer: a
Explanation: Deadlock is a condition where a WAIT statement in a process can wait forever. This can happen when two signals are set by other processes and the condition expression can never be true. This condition is called as deadlock condition. To avoid this ASSERT statement can be used to check the continuity of process.
6. In case of sensitivity list the process suspends at the end of the process and in WAIT statement it suspends ____________
a) At the beginning
b) At the end
c) At the beginning of architecture
d) Where the WAIT statement is encountered
Answer: d
Explanation: WAIT statements are more flexible than sensitivity list and therefore, it can appear anywhere in the process. Wherever the WAIT statement is encountered, the process suspends and waits for any event or condition or a time period depending on the type of WAIT statement. After the condition is met the process continues from the statement next to the WAIT statement.
7. In combinational logic, how many WAIT statements can be used?
a) 0
b) 1
c) 2
d) 3
Answer: b
Explanation: However, process is rarely used to implement combinational logic but, sometimes it is required to use WAIT statement. In that case, only one WAIT statement can be there in the process. Otherwise, it can loop forever during initialization.
8. Refer to the code given below, which kind of circuit is implemented?
PROCESS
BEGIN
WAIT on a, b;
z <= a AND b;
END PROCESS;
a) Combinational
b) Synchronous sequential
c) Asynchronous sequential
d) State machine
Answer: a
Explanation: Since the process doesn’t contain any clock signal therefore, it can’t be a sequential circuit and hence the process is a combinational circuit. Also, there is only one WAIT statement. Therefore, the design must be a combinational circuit.
9. In a procedure is called from a process having a sensitivity list, how many wait statements one can use?
a) 3
b) 2
c) 1
d) 0
Answer: d
Explanation: In any process with a sensitivity list, there can be no WAIT statements. The same is true for any kind of function or procedure called from the process with sensitivity list. So, in any function or procedure called from a process, we can’t use WAIT statement.
This set of VHDL Question Bank focuses on “WAIT Statements – 3”.
1. Which of the following is true about WAIT UNTIL statement?
a) WAIT UNTIL statement is supported by synthesis tools
b) WAIT UNTIL statement is not supported by synthesis tools
c) WAIT UNTIL statement is supported in a clocked process only
d) WAIT UNTIL statement is supported in a combinational process
Answer: c
Explanation: Most of the synthesis tools support a single WAIT UNTIL statement in a clocked process only. That means WAIT UNTIL statement can be mostly used for implementing the sequential circuit or system.
2. Which of the following is true about WAIT ON statement?
a) WAIT ON statement is supported by synthesis tools
b) WAIT ON statement is not supported by synthesis tools
c) WAIT ON statement is supported in a clocked process only
d) WAIT ON statement is supported in a combinational process
Answer: d
Explanation: Some tools support a single WAIT ON statement as an alternative to a sensitive list in a combinational process or the process in which there is no clock signal. Therefore, WAIT ON is useful for combinational circuits.
3. In a procedure, __________ statement is not supported.
a) WAIT UNTIL
b) WAIT ON
c) WAIT FOR
d) WAIT FOR and unconditional WAIT
Answer: d
Explanation: In any procedure, the wait statements can be used . But, the WAIT FOR and simple WAIT or unconditional WAIT statement is not supported by synthesis tools inside the procedure.
4. What kind of circuit is implemented by the following architecture?
ARCHITECTURE my_arch OF my_design IS
BEGIN
PROCESS
BEGIN
WAIT ON clk;
IF(clk = ‘1’) THEN
y <= x;
END IF;
END PROCESS;
END my_arch;
a) D flip flop
b) Inverter
c) OR gate
d) Shift register
Answer: a
Explanation: Since the process is using a clock and a WAIT ON statement, so it is a sequential circuit. Also, the process is sensitive to clock. Whenever, any event on clock occurs, the process is resumed and checked if clock is one or not. If it is one, then the value of input is transferred to the output. So, clearly this is a D flip flop.
5. WAIT FOR statement is useful only for _________
a) Synthesis
b) Simulation
c) Gate level implementation
d) Optimization
Answer: b
Explanation: WAIT FOR statement is only good for simulation, you can’t synthesize it. Since, synthesis means to convert the logic into actual hardware circuit. If you are using WAIT FOR 10 ns, certainly, this can’t be used in a synthesis process. So, WAIT FOR can be used for simulation only.
6. A user wants to assign a signal after a wait of 20 ns. The process used has a sensitivity list. What is the possible way to achieve this?
a) By using WAIT FOR statement
b) By using AFTER clause
c) By using a separate process
d) By using WAIT ON statement
Answer: c
Explanation: As we know that a process can’t contain both a sensitivity list and a WAIT statement. So, WAIT FOR can’t be used in this case. Also, AFTER clause is ignored by synthesis tool when used inside a process. So, using AFTER is also not possible. The only way to do this is using another process which can communicate with this process.
7. Since WAIT statement can’t be synthesized many times, how a clock event can be detected then?
a) By using IF
b) By using ‘EVENT keyword
c) By using a CASE statement
d) By using a LOOP
Answer: b
Explanation: The clock can be detected by ‘EVENT keyword. One can use IF in conjunction with ‘EVENT to detect the clock event and high and low on the same. For example, IF will detect the rising edge of the clock.
8. A wait statement can have label preceding it.
a) True
b) False
Answer: a
Explanation: In VHDL 93, it is possible to use a label in front of WAIT statement. In that case, the syntax is as follows:
Label : WAIT {UNTIL | ON | FOR} {condition | signal | time_expression};
9. Which of the following can be used to make the process wait indefinitely?
a) WAIT FOR indefinite ns;
b) WAIT UNTIL false;
c) WAIT;
d) WAIT UNTIL true;
Answer: c
Explanation: When the WAIT is used without any clause following it then it is used as an infinite WAIT statement. The WAIT statement without any clause makes the process to wait indefinitely as there is no condition or signal or time period specified.
This set of VHDL Multiple Choice Questions & Answers focuses on “Signal vs Variables – 1”.
1. Which of the following is the correct use of the signal?
a) To set a default value
b) To pass value between circuits
c) To declare a variable
d) To represent local information
Answer: b
Explanation: The signal is a data object which is used to pass a value in and out of the circuit as well as between the internal units of a circuit. Basically, signal represents interconnection of circuits or simply they acts as wires.
2. What is the use of a variable?
a) To represent local value
b) To represent default value
c) To set default value
d) To declare a subprogram
Answer: a
Explanation: Variable usually appears inside a block which may be a sequential block like process, function or procedure. It is visible to the corresponding block only. Therefore, variables are used to represent local information.
3. Use of constants is to _________
a) Represent wires
b) Represent local information
c) Represent default value
d) Pass value between entities
Answer: c
Explanation: Constant is a data object which serves to establish default value. As the name suggests, the value of constant can’t be modified by using assignment statements. The value is once assigned and the same is used again and again.
4. How to declare a constant in VHDL?
a) CONSTANT name : type := value;
b) CONSTANT name := value;
c) CONSTANT name := type := value;
d) CONSTANT name := type : value;
Answer: a
Explanation: The correct syntax to declare a CONSTANT data object in VHDL is shown in option a. The keyword CONSTANT is followed by the name of the constant which in turn is followed by a colon sign. After the colon sign, the type of constant is specified and the value is assigned by using := assignment operator.
5. Which of the following is local to the block in which it is declared?
a) Signal
b) Integer
c) Constant
d) Variable
Answer: d
Explanation: Both Signals and Variables are global to the code whereas Variable is the only data object which is local to the block in which it is declared. For example, a variable x is declared in a process then x will be accessible only within the process.
6. A constant is declared in Architecture, it will be accessible in ________
a) Whole code
b) Within the same architecture
c) In the entity associated and corresponding architecture
d) In the process within the architecture
Answer: b
Explanation: A constant when declared in the architecture, it is global to the architecture. That means, no matter how many blocks are there in architecture, the constant can be used in each of those block. Unlike variable which is local to the variable only.
7. Which of the following can’t be declared in an architecture?
a) Signal
b) Constant
c) Variable
d) BIT_VECTOR
Answer: c
Explanation: We can’t use a variable data object in architecture directly. Variable is mainly intended for sequential code. So, variables can be declared and used in processes, functions or procedures. However, Signals and variables can be used in architecture.
8. What is the scope of a constant declared in an entity?
a) Local to the entity
b) Global to the whole code
c) Local to the port
d) Global to the entity and all the architecture associated
Answer: d
Explanation: The constant declared in an entity can be used in the entity itself as well as the architectures associated with the entity. For example, there are 3 architectures for an entity then all the 3 architectures can access the constant declared in the entity.
9. A user wants a constant to be declared in such a way that it can be accessible by whole code, where should the user declare this constant?
a) Package
b) Entity
c) Architecture
d) Configuration
Answer: a
Explanation: When a constant is declared in a package, it is truly global, for the package can be used by several entities and architecture. However, if the same was declared in entity then it can be accessed by the architectures of same entity only.
10. Which of the following is the default type of ports of an entity?
a) Variables
b) Constants
c) Signals
d) Functions
Answer: c
Explanation: Since ports of an entity represent the inputs and outputs of a part of the circuit. Therefore, VHDL takes the ports of entity as signals. If no type is specified in front of a port then it will be considered as a signal.
This set of VHDL online quiz focuses on “Signal vs Variables – 2”.
1. Which data object can’t be declared inside a process?
a) Signal
b) Variable
c) Constant
d) Integer
Answer: a
Explanation: A process consists of sequential statements and signals can be used inside the process. But, it is not possible to declare a signal inside the process. Variables, on the other hand, can be declared in a process.
2. When a signal is assigned a value inside a process, then the value of a signal is updated _________
a) Immediately
b) After one delta cycle
c) At the end of the corresponding process
d) At the end of architecture
Answer: c
Explanation: The signal is not updated immediately. The new value should not be expected to be ready before the conclusion of the corresponding process. It is updated at the end of the process and therefore, it is not recommended to assign two or more values to a signal in the same process since only last one is considered.
3. A variable is assigned a value inside a process, the new value of the variable will be available _______
a) After one delta cycle
b) Immediately
c) At the end of a process
d) At the end of architecture
Answer: b
Explanation: Unlike signals, the value of variable is updated immediately. In other words, we can say that the new value of the variable or its updated value can be used immediately in the next line of the code which is not the case with variables.
4. A variable can be used outside the process i.e. in the architecture.
a) True
b) False
Answer: b
Explanation: A variable can be used inside a process, function or procedure only. One can’t use it outside the process. The variables can’t be assigned values concurrently or in a parallel manner as we can do with the signals.
5. There are no delays in case of variables.
a) True
b) False
Answer: a
Explanation: As we know that the variables get their value at the same time or immediately. No delay can be used in the variable assignment. However, in signals there are two types of delay which are transport and inertial delays. This is not possible to use AFTER keyword in the variable assignment.
6. When there is no delay specified in a signal assignment , the delay will be _______
a) Zero
b) Transport delay
c) Inertial delay
d) Delta delay
Answer: d
Explanation: In a concurrent assignment statement either transport or inertial delay is used. Even if there is zero delay specified it will consider delta delay before assigning a value to the signal. So, it is not possible to assign the value to signal immediately even if no delay is specified.
7. During synthesis, a variable infers ________
a) Flip flop
b) Register
c) Wire
d) Variables are not synthesizable
Answer: c
Explanation: Both signal and variable are synthesizable and variables infers a wire at the time of synthesis. However, the signal, unlike variable, infers a flip flop at the time of synthesis.
8. In which of the following, the right hand side of an assignment is a waveform element?
a) Signal
b) Variable
c) Constant
d) Process
Answer: a
Explanation: The right hand side of a signal assignment statement is a sequence of waveform elements. These elements are having associated time expressions or delays which are generally followed by AFTER keyword.
9. Which of the following needs no evaluation of drivers?
a) Signals
b) Variables
c) Process
d) Functions
Answer: b
Explanation: Signals have drivers associated with them which need evaluation and resolution . On the other hand, variable has no driver associated so no evaluation is required at the time of simulation. So, variables are cheaper to implement as compared to signals.
10. What is there in right hand side of a variable assignment?
a) Time expressions
b) Waveform elements
c) Delays
d) Simple expressions
Answer: d
Explanation: Unlike signals, there are no waveform elements and timing expressions on the right hand side of a variable assignment. The right hand side of a variable assignment is always an expression which can be any of the Boolean, arithmetic or logical.
This set of VHDL Multiple Choice Questions & Answers focuses on “Package”.
1. Which of the following is true about packages?
a) Package is collection of libraries
b) Library is collection of packages
c) Package is collection of entities
d) Entity is collection of packages
Answer: b
Explanation: A library contains many packages and it is used to collect and describe elements that can be shared globally among all the design units. It may contain any commonly used data type, functions or constants.
2. A package may consist of _________ design units.
a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: A package may consist of two separate design units which are package declaration and package body. Package declaration is necessary part for any package whereas package body is an optional part. Package declaration, like entity declaration, describes the interface of the design and package body is similar to architecture in the VHDL code.
3. Any item declared in a package declaration section are visible to _______
a) Every design unit
b) Package body only
c) Library containing that package
d) Design unit that USE the package
Answer: d
Explanation: To use any component, constant, signal, subprogram or function declared in a package, one needs to declare the package in the code itself by using the USE clause. When the package is declared in the library declaration part of the code then the functions or datatypes defined in the package will be visible to the design unit.
4. What do you call a constant declared in the package declaration, without its initial value specified?
a) Constant
b) Package constant
c) Deferred constant
d) Undefined constant
Answer: c
Explanation: Deferred constants are constants that have their name and type declared in the package declaration section but the actual value is specified in the package body section. It is important to use package body when a deferred constant is declared in the package declaration body.
5. Which of the following is the correct syntax to declare a package?
a)
PACKAGE package_name IS
declarations;
END package_name;
PACKAGE BODY package_name IS
Functions and procedures descriptions;
END package_name;
b)
PACKAGE package_name IS
declarations;
PACKAGE BODY package_body_name IS
Functions and procedures descriptions;
END package_name;
c)
PACKAGE package_name IS
declarations;
END package_name;
PACKAGE BODY package_body_name IS
Functions and procedures descriptions;
END package_name;
d)
PACKAGE package_name IS
declarations;
PACKAGE BODY package_name IS
Functions and procedures descriptions;
END package_name;
Answer: a
Explanation: The PACKAGE keyword is followed by the name of package and after which there is an declaration part of the package. If any subprogram or deferred constant is declared in the package declaration, then a package body must be defined. Note that the package body doesn’t have a separate name. It uses the same name as that of package.
6. How to use a package in a VHDL design unit?
a)
USE PACKAGE package_name.part;
b)
LIBRARY library_name;
USE package_name.part;
c)
LIBRARY library_name;
USE library_name.package_name.part;
d)
USE library_name.package_name;
Answer: c
Explanation: To use a package, first we want to define the library in which it is actually declared. After that to use the package, we need to use the USE clause which is followed by library name and the package name and then the part of package which we need to include to the design.
7. It is possible to use hierarchical libraries in VHDL.
a) True
b) False
Answer: b
Explanation: VHDL doesn’t support hierarchical libraries. A VHDL library can consist of packages, entities, architectures, configurations but not libraries. We can have as many libraries as we want, but we cannot nest them.
8. Which of the following package is not synthesizable?
a)
PACKAGE my_pack IS
SIGNAL x : IN std_logic;
END my_pack;
b)
PACKAGE my_pack IS
CONSTANT x : INTEGER := 5;
END my_pack;
c)
PACKAGE my_pack IS
FUNCTION my_func RETURN BOOLEAN IS;
END my_pack;
PACKAGE BODY my_pack IS
Function description;
END my_pack;
d)
PACKAGE my_pack IS
TYPE color IS (red, green, blue);
END PACKAGE;
Answer: a
Explanation: Though it is possible to use and declare signals in packages but signal declaration may cause some problems in synthesis because a signal can’t be shared by two entities. However, it is possible to declare global signals in the design itself.
9. Among which of the following, it is necessary to declare a package body?
a)
PACKAGE my_pack IS
SIGNAL x : IN std_logic;
END my_pack;
b)
PACKAGE my_pack IS
CONSTANT x : INTEGER := 5;
END my_pack;
c)
PACKAGE my_pack IS
FUNCTION my_func RETURN BOOLEAN IS;
END my_pack;
d)
PACKAGE my_pack IS
TYPE color IS (red, green, blue);
END PACKAGE;
Answer: c
Explanation: Package declaration is always mandatory but package body is optional. When a function or deferred constant is declared in the package declaration, then it is necessary to use a package body so as to assign value to the constant or to describe the function.
10. It is possible to include another package in a package.
a) True
b) False
Answer: a
Explanation: Though it is not possible to nest libraries in VHDL but it is possible to nest packages. One can make use of another package inside a package by USE clause. In the package declaration, USE may be used to include another packages.
11. Which of the following is not a in-built package in VHDL?
a) STD_LOGIC_1164
b) TEXTIO
c) STANDARD
d) STD
Answer: d
Explanation: STD is not a package but it is a library. All other STD_LOGIC_1164, TEXTIO, STANDARD etc. are some in built packages of VHDL. STD_LOGIC_1164 is declared in the IEEE library. TEXTIO and STANDARD libraries are declared in STD library.
12. If a user wants to include his/her own package in the body, which library he/she must use?
a) STD
b) IEEE
c) WORK
d) STD_LOGIC
Answer: c
Explanation: WORK is a library which can be used to store and use user-defined packages. Similar to other libraries, it is also declared in the same manner by using LIBRARY keyword and to declare the package, USE clause is used.
13. Packages increases _______ of the code.
a) Reusability
b) Readability
c) Managing
d) Resolution
Answer: a
Explanation: Since packages can be used again and again in the different design units. So, same data types, functions, subprograms, constants can be used many times without any declaration. So, packages increase the reusability of the code.
14. It is possible to modify the STD_LOGIC_1164 package of IEEE library.
a) True
b) False
Answer: b
Explanation: The STD_LOGIC_1164 package has been developed and standardized by IEEE and only IEEE has rights to modify the package. User is not allowed to add or remove something from the package. It can only be included in the designs.
15. Which of the following can’t have multiple assignments or drivers?
a) STD_LOGIC
b) INTEGER
c) STD_ULOGIC
d) BIT
Answer: c
Explanation: The resolving functions for all except STD_ULOGIC has been defined in the respective packages. Only STD_ULOGIC is of unresolved type. So, multiple values can’t be assigned to the STD_ULOGIC type since there is no means of resolving the value.
This set of VHDL Multiple Choice Questions & Answers focuses on “Some Predefined Packages”.
1. Which of the following package need not to be a part of the VHDL code?
a) STANDARD
b) STD_LOGIC_1164
c) TEXTIO
d) STD_LOGIC_ARITH
Answer: a
Explanation: The package STANDARD is usually integrated directly in the simulation or synthesis program. Therefore, it doesn’t exist as a VHDL description. It doesn’t have to be explicitly included by the USE clause.
2. In which of the following library, the package STANDARD defined?
a) IEEE
b) STD
c) WORK
d) STD_LOGIC
Answer: b
Explanation: The package STANDARD is a part of STD library which doesn’t need to be included in the code. It is automatically included in the description without any extra statement or declaration. All other packages of STD library needs to be defined in the code itself.
3. Which of the following is not defined in the STANDARD package?
a) Basic data types
b) Functions for different operations for data types
c) Functions to read from the text files
d) Functions for arithmetic operators
Answer: c
Explanation: The package STANDARD contains all the basic data type like Boolean, bit, bit_vector, integer, character and so on. It also contains logical, comparison and arithmetic operators for these data types. It doesn’t contain any function to read and write into text files.
4. Which statement is correct to include a package in the code where we need to read from and write to text files?
a) USE STD.TEXT.all;
b) USE STD.TEXTIO.all;
c) USE IEEE.TEXTIO.all;
d) USE IEEE.TEXT.all;
Answer: b
Explanation: The package which contains procedures and functions needed to read from and write to text files is the TEXTIO package. This package is defined in STD library of the VHDL. So, the correct statement is USE STD.TEXTIO.all to include the TEXTIO package.
5. TEXTIO package is included in the code by default.
a) True
b) False
Answer: b
Explanation: It is not true that TEXTIO package is included in the code by default. However, it is defined in the STD library from which STANDARD and such packages are included by default but this is not the case with TEXTIO package. It needs the USE clause to be included in the package.
6. Among the four packages given below, which is the most used package of VHDL?
a) STD_LOGIC_1164
b) TEXTIO
c) STD_LOGIC_ARITH
d) NUMERIC_STD
Answer: a
Explanation: The STD_LOGIC_1164 package is most used package in VHDL since it contains definition of data types which are used for modeling wires at the time of synthesis. To use such data types, it is necessary to include STD_LOGIC_1164 in the code. In fact, it is used in almost every single design in VHDL.
7. The STD_LOGIC_1164 package is contained by _______ library.
a) STD
b) WORK
c) STD_LOGIC
d) IEEE
Answer: d
Explanation: The STD_LOGIC_1164 package has been developed and standardized by the IEEE and hence it is included in IEEE library of VHDL. It could be referenced easily by using two statements: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.all; Also, this is not included by default.
8. What is the most important use of STD_LOGIC_1164 package?
a) To define and use parallel operations
b) To use concurrent code
c) To use sequential code
d) Multi value logic system
Answer: d
Explanation: STD_LOGIC_1164 defines the data types like STD_LOGIC, STD_ULOGIC and the corresponding vector types. These data types basically work on multi valued logic system rather than two valued logic . So, to use this multi value logic we need to include the STD_LOGIC_1164 package.
9. Which package defines the data type STD_LOGIC_SIGNED?
a) STD_LOGIC_1164
b) STD_LOGIC_ARITH
c) STD_LOGIC_NUMERIC
d) IEEE
Answer: b
Explanation: SRD_LOGIC_ARITH is another package defined in the IEEE library. This package gives a definition of STD_LOGIC_SIGNED and STD_LOGIC_UNSIGNED data types. The basic purpose of STD_LOGIC_ARITH is to provide arithmetic accessibility to STD_LOGIC data types etc.
10. What is another name for STD_LOGIC_ARITH package?
a) STD_LOGIC_1164
b) STD_LOGIC_NUMERIC
c) NUMERIC_STD
d) ARITH_STD
Answer: c
Explanation: STD_LOGIC_ARITH is basically provided by Synopsys and NUMERIC_STD is provided by IEEE. Both of the packages are equivalent and define the same arithmetic functions. So, STD_LOGIC_ARITH is another name for NUMERIC_STD package.
11. The basic arithmetic function provided by STD_LOGIC_ARITH is for ______ data type.
a) STD_LOGIC_VECTOR
b) STD_LOGIC
c) INTEGER
d) CHARACTER
Answer: a
Explanation: STD_LOGIC_ARITH basically contain arithmetic functions to enable calculations and comparisons based on the types STD_ULOGIC_VECTOR and STD_LOGIC_VECTOR. So, calculations related to vector types of STD_LOGIC_1164 are in STD_LOGIC_ARITH package.
12. The following statement must be in _______ package.
TYPE my_type IS RANGE (0, 1);
a) STD_LOGIC_1164
b) STANDARD
c) STD_LOGIC_ARITH
d) IEEE
Answer: b
Explanation: Since the data type my_type can have only two values which are 0 and 1 which is the case of BIT data type. Therefore, my_type is BIT data type which is defined in STANDARD package. So, the given statement must be in STANDARD package.
13. Which of the following package may contain the given statement?
TYPE color IS RANGE (red, green, blue, black)
a) STD_LOGIC_1164
b) STANDARD
c) STD_LOGIC_ARITH
d) WORK
Answer: d
Explanation: There is no such pre defined data type which may take any value like red, green, blue or black. So, this must be a user defined data type and not a predefined one. Therefore, it must be defined in WORK package.
14. Following lines are a part of _______ package.
TYPE my_type IS (‘U’, ‘X’, ‘0’, ‘1’, ‘Z’, ‘W’, ‘ L’, ‘H’, ‘-‘);
a) STANDARD
b) STD_LOGIC_ARITH
c) STD_LOGIC_1164
d) WORK
Answer: c
Explanation: The given type shows 9 valued logic which is STD_ULOGIC type having 9 different values. This multi valued logic is defined in STD_LOGIC_1164 package of IEEE library. Apart from STD_ULOGIC, STD_LOGIC is also defined in STD_LOGIC_1164.
15. In STD_LOGIC_1164, the resolution function for ______ is not provided.
a) STD_LOGIC
b) STD_LOGIC_VECTOR
c) STD_ULOGIC
d) STD_ULOGIC_VECTOR
Answer: c
Explanation: STD_ULOGIC is the unresolved data type of the STD_LOGIC_1164 package. STD_LOGIC is the resolved version of STD_ULOGIC. Similarly, there are resolution functions to resolve vector types into scalar types.
This set of VHDL Multiple Choice Questions & Answers focuses on “Functions and Subprograms – 1”.
1. Functions and subprograms are both same.
a) True
b) False
Answer: b
Explanation: A subprogram consists of procedures and functions. Both of them are collectively called subprograms. So, subprogram is not same as a function but a function is a part of subprogram in case of VHDL.
2. A function is a ________ code.
a) Concurrent
b) Sequential
c) Concurrent as well as sequential
d) Process oriented
Answer: b
Explanation: A function is a section of sequential code. From the construction point of view, functions are very similar to the process. They employ all the sequential statements like IF, CASE etc.
3. Which of the following sequential statement can’t be used in a function?
a) WAIT
b) IF
c) CASE
d) LOOP
Answer: a
Explanation: A function can contain any kind of sequential statement may it be IF statement, CASE statement, LOOP statement, NEXT, EXIT or NULL. The only exception is the WAIT statement. One can’t use a WAIT statement inside a function.
4. What is the correct syntax for declaration of a function?
a)
FUNCTION function_name (parameter_list) RETURN return_type IS
declaration_part;
BEGIN
sequential_statements;
END FUNCTION;
b)
FUNCTION function_name (parameter_list) RETURN return_type IS
BEGIN
declaration_part;
sequential_statements;
RETURN expression;
END FUNCTION;
c)
FUNCTION function_name (parameter_list) RETURN return_type IS
BEGIN
declaration_part;
sequential_statements;
RETURN expression;
END function_name;
d)
FUNCTION function_name (parameter_list) RETURN return_type IS
declaration_part;
BEGIN
sequential_statements;
RETURN expression;
END function_name;
Answer: d
Explanation: The function is defined in the way shown in option d. The keyword FUNCTION is followed by the name of function which in turn is followed by the list of parameters in a parenthesis. After the list of parameters the return type of a function is specified followed by the declaration part of the function in which local variables can be declared. The declaration part and statement part is separated by keyword BEGIN. Then there is the RETURN statement and the function definition is end by END and function name.
5. The function is called from the ________
a) Function itself
b) Library
c) Main code
d) Package
Answer: c
Explanation: The function which is once declared is always called from the main code. Whenever a function call occurs, the control is passed to the space where the function is defined. Then, the function is executed till a RETURN statement comes, which returns the control to main code.
6. The parameters used at the time of function call are called _________
a) Formal parameters
b) Actual parameters
c) Real parameters
d) Complex parameters
Answer: b
Explanation: The parameters which are specified at the time of function call are called the Actual parameters whereas the parameters used at the time of function definition are called formal parameters. The values from actual parameters are copied to the formal parameters in the same order as specified.
7. Functions are always invoked as a _________
a) Constant
b) Variable
c) Signal
d) Expression
Answer: d
Explanation: Any function having a return type is always invoked as an expression. The expression is solved in the function definition and the result is specified by the return statement which can be taken as the result of the expression itself.
8. How many return arguments can be there in the function?
a) 1
b) 2
c) 3
d) 4
Answer: a
Explanation: It is very important thing to note that one function can return at most one value. The expression which is used in the return statement must result in the same type as that of return type specified in the definition. The value from the return expression is then returned to the main code.
9. Which of the following can’t be the parameter of function?
SIGNAL a, b : IN STD_LOGIC
VARIABLE c : INTEGER
CONSTANT d : INTEGER
a) a
b) b
c) c
d) d
Answer: c
Explanation: The parameter of a function can either be a signal or a constant. The variable can’t be used as a parameter of a function. Any of the data types which are synthesizable are allowed to use as a type of signals or constants.
10. A function call can be a concurrent as well as a sequential statement.
a) True
b) False
Answer: a
Explanation: The function can be called in the concurrent part of the code and it can be called in the sequential part of the code. It is not necessary that a function can be called inside a process only. However, it may be noted that the function itself contains only sequential statements.
This set of VHDL Questions and Answers for Entrance exams focuses on “Functions and Subprograms – 2”.
1. Refer to the function defined below, a and b have respectively following data objects.
FUNCTION my_func (SIGNAL a : STD_LOGIC_VECTOR; b : STD_LOGIC) RETURN BOOLEAN IS
…..;
a) Constant, Constant
b) Constant, Signal
c) Signal, Constant
d) Signal, Signal
Answer: c
Explanation: Until the data object is not specified, the corresponding must be considered as a constant. In the above function, a is specified as a signal but b is not specified therefore, b is taken as a constant. So, a is a signal as specified and b is a constant.
2. What should be the mode of signal a in the following function definition?
FUNCTION my_func (SIGNAL a : STD_LOGIC_VECTOR) RETURN INTEGER IS
…..;
a) IN
b) OUT
c) INOUT
d) BUFFER
Answer: a
Explanation: The default and only signal mode which is applicable to a parameter of the function is the IN mode. There is no need to specify the mode at the time of definition. It is obvious that the mode is taken as IN mode. No other mode can be used in the parameter of a function.
3. Functions are called using ______ no of ________ statement.
a) 1, If
b) 1, Assignment
c) 2, If
d) 2, Assignment
Answer: b
Explanation: The functions are called using a single assignment statement. A function is always invoked as an expression and therefore, it is called by using an assignment statement in which function appears on the right side of the assignment operator.
4. Which of the following type can’t be a parameter of a function?
a) Signals
b) Constants
c) Files
d) Variables
Answer: d
Explanation: Apart from signals and variables, the files can also be used as a parameter to a function. The only restriction is to use a variable in the parameter of the function. One may use signal of IN mode, any constants and files in the parameter list.
5. A component may be declared and instantiated inside a function.
a) True
b) False
Answer: b
Explanation: In the declaration part of a function, one may declare a variable. But the declaration of a signal and a constant is not allowed inside a function. The constant instantiation is a concurrent statement and a function consists of sequential statements. Therefore, it is not possible to declare and instantiate a component.
6. What is the use of resolution functions?
a) Return the value of a signal with multiple drivers
b) Resolve value of a constant with multiple drivers
c) Convert one data type into another
d) Convert one data object into another
Answer: a
Explanation: Resolution function is used to resolve the value of a signal when the signal is driven by multiple drivers. It returns the new value of the signal by resolving all the drivers to give a single new value.
7. It is not possible to use multiple driver signals without a resolution function.
a) True
b) False
Answer: a
Explanation: In VHDL, it is illegal to have a signal with multiple drivers without a resolution function attached to the signal. Most of the resolution functions are predefined in the packages provided by STD and IEEE. But, if there is no resolution function then we can’t assign multiple values to the signal.
8. A resolution function is invoked when ________
a) The signal is assigned multiple values
b) All the drivers has changed their value for once at least
c) Any of the driver changes its value
d) The signal is assigned a second value
Answer: b
Explanation: A resolution function is called whenever one of the drivers for the signal has an event occurred on it. The resolution function is then executed and it returns a single value from all the driver values, that value is the new value of the signal.
9. How many parameters are there in a resolution function?
a) 3
b) 2
c) 0
d) 1
Answer: d
Explanation: A resolution function has one parameter or argument and returns a single value. The parameter is of array type having the values of all the drivers attached to the signal.
10. What would be the length of array used as a parameter to the resolution function which resolves the value of a signal having 2 drivers?
a) 1
b) 2
c) 3
d) Infinite
Answer: b
Explanation: Though the array is unconstrained, but when the number of drivers is known, then the length is limited to the same number. For example, if there are two drivers for a signal, then the array used as a parameter must be of length two.
This set of VHDL Questions and Answers for Campus interviews focuses on “Functions and Subprograms – 3”.
1. In VHDL it is not possible to use recursive functions.
a) True
b) False
Answer: b
Explanation: Like all other traditional programming languages, in VHDL too we can use recursive functions. Recursive function is the function which calls itself again and again until a condition comes to be true. It is possible to call functions recursively.
2. Apart from using WAIT statements, which of the following is not possible in functions?
a) Variable assignment
b) Return statement
c) Variable declaration
d) Signal assignment
Answer: d
Explanation: The signal assignment can’t be done inside a function body. It is possible to declare a variable and assign it some value but it is not possible to declare and use signal assignment inside the function.
3. Conversion functions are used to _________
a) Resolve value of a signal with multiple drivers
b) Convert one data type into another
c) Convert one data object into another
d) Resolve value of a constant with multiple drivers
Answer: b
Explanation: Conversion functions are the functions which are used to convert any object of one data type into another data type. Some of such conversion functions are predefined in the packages. For example, CONV_INTEGER converts the parameter into an integer value.
4. The variables declared inside a function retain their values between two function calls.
a) True
b) False
Answer: b
Explanation: A function may declare local variables which are accessible inside the function only. These variables don’t retain their values between successive calls but are reinitialized each time the function is called.
5. The minimum number of parameters that must be there in a function is ___________
a) 0
b) 1
c) 2
d) 3
Answer: a
Explanation: Yes, It is possible to have a function which has no parameter specified in the parameter list. If we don’t need to pass any information to the function from the main code, then there is no need to use any parameter in the list.
6. Which of the following is not the legal name of a function?
a) abc
b) +
c) then
d) my_func
Answer: c
Explanation: As for all other identifiers, the name may not be any reserved word of VHDL and can have alphanumeric characters and an underscore sign. The only different thing with functions is that the name of function can be any operator sign also.
7. In the following code, which of the lines corresponds to the function call and function definition?
L1 : ARCHITECTURE adder OF adder IS
L2 : BEGIN
L3 : x <= sum ( SIGNAL a : STD_LOGIC; SIGNAL b : STD_LOGIC);
L4 : END adder;
L5 : FUNCTION sum ( SIGNAL a : STD_LOGIC; SIGNAL b : STD_LOGIC) RETURN STD_LOGIC IS
L6 : VARIABLE c : INTEGER;
L7 : BEGIN
L8 : c<= a OR b;
L9 : RETURN c;
L10 : END sum;
a) L5, L3
b) L5, L9
c) L3, L7
d) L3, L5
Answer: d
Explanation: Function call is when a function is invoked as an expression and the definition of function is where the whole description of function is given. Therefore, L3 corresponds to a function call and L5 is where function definition starts.
8. What is the ease provided by using functions?
a) Easy debugging
b) Easy reading
c) Easy calling
d) Easy implementation
Answer: a
Explanation: Using function results in easy debugging. Since reading and maintaining code is easy while using functions. Usually, the architecture of a code is very big and therefore, causes difficulty in debugging. So, by using functions, debugging is easy.
9. If a function has an operator sign as its name, then what will be the purpose of that function?
a) Conversion
b) Overloading
c) Resolution
d) Define the data type
Answer: b
Explanation: When we want to make any operator behave differently, then we can define a function whose name will be same as the operator. This process of using an operator in a different manner is called the operator overloading.
10. What is the alternative for specifying the vector size in the function?
a) Not using arrays
b) Defining every single element differently
c) Defining a subtype
d) Using bit vector
Answer: c
Explanation: Sometimes, it is necessary to use arrays. In functions, it is not possible to define the size of array or vector we are using. Instead, we can define a subtype for the same which can be used easily as a parameter to the function.
This set of VHDL Multiple Choice Questions & Answers focuses on “Procedures – 1”.
1. Procedures are invoked as _________
a) Statements
b) Expressions
c) Values
d) Assignments
Answer: a
Explanation: Unlike functions, procedures are invoked as a statement. Functions are always invoked as expressions as a part of the assignment statement but procedures are directly called as statements only. No assignment operator is needed.
2. Procedures are useful when _________
a) Functions are not synthesizable
b) Signals are needed to be declare
c) Multiple values are needed as a result
d) Architecture can’t contain some statement
Answer: c
Explanation: Procedures usually returns many values, which is not possible with the case of function. So, procedures are useful when there are multiple results coming from the procedure. Note that procedure can return single value as well.
3. Which of the following is correct syntax for procedure body?
a)
PROCEDURE procedure_name (parameter_list) IS
BEGIN
declarations;
sequential_statements;
END PROCEDURE;
b)
PROCEDURE procedure_name (parameter_list) IS
declarations;
BEGIN
sequential_statements;
END procedure_name;
c)
PROCEDURE procedure_name (parameter_list) IS
declarations;
BEGIN
sequential_statements;
concureent_statements;
END PROCEDURE;
d)
PROCEDURE procedure_name (parameter_list) IS
declarations;
BEGIN
sequential_statements;
concurrent_statements;
END procedure_name;
Answer: b
Explanation: The procedure definition is very similar to the function definition. It starts with the keyword PROCEDURE followed by the name of procedure and then the parameter list. Then local declarations are made within the procedure body, which are separated from the statements part by the keyword begin. Then the procedure body is ended by the keyword END followed by name of procedure.
4. Procedure doesn’t have a return type.
a) True
b) False
Answer: a
Explanation: Functions always have a return type which specifies the type of value which is returned by the function. But, procedures return multiple values; therefore, it is not possible to use a single return type. So, There is no return type for a procedure.
5. Which of the following could be the objects in the parameter list of a procedure?
a) CONSTANTS, VARIABLES
b) VARIABLES, SIGNALS
c) CONSTANTS, SIGNALS
d) CONSTANT, SIGNALS, VARIABLES
Answer: d
Explanation: A procedure may have any of three objects in its parameter list. A SIGNAL, CONSTANT as well as a VARIABLE can be used as a parameter to a procedure. In functions, only signals and constants can be parameters.
6. A procedure can’t contain a _______ statement.
a) WAIT
b) IF
c) RETURN
d) CASE
Answer: c
Explanation: A procedure, unlike functions, may contain WAIT statement but it doesn’t include any return statement. The assignments made in the procedure are considered as the values which are needed to be returned to the main code.
7. The parameter of a procedure can have any of the three modes.
a) True
b) False
Answer: a
Explanation: A procedure can have any number of IN, OUT or INOUT parameters which can be signals, constants or variables. There is no restriction on the mode of the signal It may be any of the three modes which are IN, OUT or INOUT.
8. Which of the following is the default class of any parameter with its mode as IN?
a) SIGNAL
b) CONSTANT
c) VARIABLE
d) SIGNAL or VARIABLE
Answer: b
Explanation: The default class for any IN mode parameter is CONSTANT. It means that if no mode is specified the parameters of mode IN are interpreted as class CONSTANT.
9. Which of the following is the default mode of a parameter of procedure?
a) IN
b) OUT
c) INOUT
d) IN or INOUT
Answer: a
Explanation: If no mode is specified in the front of a parameter, then it is considered as an input signal or of a mode IN. So, The default mode for a parameter of a procedure is IN mode which is similar to the functions.
10. It is given that the mode of a parameter is OUT mode but its class is not specified by the user. To which class does it belong?
a) INTEGER
b) CONSTANT
c) VARIABLE
d) SIGNAL
Answer: c
Explanation: The CONSTANT is the default class for the parameters of mode IN only. For other parameters that have their mode either as OUT or as INOUT the default class is considered as VARIABLE class.
This set of VHDL Questions and Answers for Aptitude test focuses on “Procedures – 2”.
1. Which of the following is not similar in both functions as well as procedures?
a) One can’t declare signals in functions as well as procedures
b) One can’t declare components in functions and procedures
c) In both, the WAIT statement is not synthesizable
d) Both can be declared inside a package
Answer: a
Explanation: The signals can be declared inside a procedure which is not possible with functions. However, all other things are common in both functions and procedures. One can use WAIT statement inside a procedure but it not synthesizable and both can be declared inside a package.
2. The mode and class of the following parameters are respectively ________
my_procedure( SIGNAL a : IN INTEGER; b : OUT INTEGER; c : BIT);
a) IN, SIGNAL; OUT, SIGNAL; IN, CONSTANT
b) IN, SIGNAL; OUT, CONSTANT; IN, VARIABLE
c) IN, SIGNAL; OUT, VARIABLE; IN, CONSTANT
d) IN, SIGNAL; OUT, CONSTANT; OUT, CONSTANT
Answer: c
Explanation: The default mode for any parameter is IN mode. So, the mode of C is IN mode and those of other two are specified. The class of a is specified as SIGNAL. The parameter b is of OUT mode so it will be considered as a VARIABLE and c is considered as a CONSTANT.
3. Which of the following is true about both functions and procedures?
a) WAIT statement can’t be used
b) When declared in a package, both require package body
c) SIGNALs can’t be declared
d) RETURN is used in both
Answer: b
Explanation: When function or procedure is placed in a package, then it is necessary to write the package body so that functions and procedures can be defined. However, WAIT can be used in procedures and same is true about signals. RETURN is not used in a procedure.
4. A user is encountering some error with his design, among which of the following the debugging must be easy?
a) In a code containing no functions or procedures
b) In a code containing functions but no procedures
c) In a code containing procedures but no functions
d) In a code containing both functions as well as procedures
Answer: b
Explanation: The debugging is easy with the use of functions. However, procedures also divide the code into small segments but there are some side effects with the procedures. For example, the change in value of a signal without being an argument of the procedure.
5. A procedure is called concurrently. It will execute when ________
a) Any of its parameters change
b) Any of its OUT parameters change
c) Any of its IN parameters change
d) Any of its IN or INOUT parameter change
Answer: d
Explanation: If the procedure is called outside a process then it is considered as a concurrent call. In that case, the procedure call statement executes whenever any of its parameter change with the mode IN or INOUT. There is no execution if the OUT parameter is changed.
6. In which of the following cases, the procedure can’t contain WAIT statement?
a) When called from inside a process
b) When called from inside a process with a sensitivity list
c) When called from architecture
d) When called from a LOOP statement
Answer: b
Explanation: The WAIT statement can be used inside a procedure until it is called from a process containing a sensitivity list. Also, if the procedure is called from a function, then the use of WAIT statement is not possible.
7. A procedure can have a label in front of it.
a) True
b) False
Answer: a
Explanation: In VHDL 93, the availability of labels in front of any special statement is made available. One may use an optional label in front of a procedure call or procedure definition to make it more readable. This is possible in VHDL.
8. In which of the following case, the code will not be synthesizable?
a) Code containing a WAIT statement inside a process
b) Code containing a WAIT statement inside a procedure
c) Code containing a RETURN statement inside a function
d) Code containing a CASE statement inside a function
Answer: b
Explanation: The design is synthesizable if the procedure doesn’t have any WAIT statement in it. Also, a process can have wait statement until it doesn’t have a sensitivity list. Moreover, Function should have RETURN statement to be synthesizable.
9. Which of the following may be specified by the code given?
TYPE op_code is ( ADD, SUB, MUL, DIV, LT, LE, EQ );
PROCEDURE first_unit ( A, B : in integer; op : in op_code;
Z : out integer; ZCOMP : out boolean ) is
BEGIN
CASE op IS
WHEN ADD => Z := A + B;
WHEN SUB => Z := A - B;
WHEN MUL => Z := A * B;
WHEN DIV => Z := A / B;
WHEN LT => ZCOMP := A < B;
WHEN LE => ZCOMP := A <= B;
WHEN EQ => ZCOMP := A = B;
WHEN others => Z := Z;
END case;
END first_unit;
a) CPU
b) CU
c) ALU
d) Memory
Answer: c
Explanation: It is clear from the code in which two parameters are showing inputs on which different operations are being performed. Therefore, It is the case of ALU unit of the CPU.
10. How many types of the output are returned by the code given?
TYPE op_code is ( ADD, SUB, MUL, DIV, LT, LE, EQ );
PROCEDURE first_unit ( A, B : in integer; op : in op_code;
Z : out integer; ZCOMP : out boolean ) is
BEGIN
CASE op IS
WHEN ADD => Z := A + B;
WHEN SUB => Z := A - B;
WHEN MUL => Z := A * B;
WHEN DIV => Z := A / B;
WHEN LT => ZCOMP := A < B;
WHEN LE => ZCOMP := A <= B;
WHEN EQ => ZCOMP := A = B;
WHEN others => Z := Z;
END case;
END first_unit;
a) 0
b) 1
c) 2
d) 3
Answer: c
Explanation: There are 2 types of the outputs. In the arithmetic operations the output is of INTEGER and for logical operations the output is logical or of BOOLEAN type which may be either true or false.
This set of VHDL Multiple Choice Questions & Answers focuses on “Attributes”.
1. What is the use of an attribute?
a) To find all characteristics of an entity
b) To find all characteristics of architecture
c) To extract some additional information about some object
d) To extract information about clock signals
Answer: c
Explanation: An attribute is a feature of VHDL that allows you to extract additional information about any object. This object can be either a signal, variable or a type. It can also be associated with an entity but it returns a single value which means single information.
2. Predefined attributes are defined as a part of _________ standard.
a) 1164
b) 1076
c) 1162
d) 1093
Answer: b
Explanation: The VHDL describes some fundamental kinds of attributes. These different attributes are defined as a part of 1076 standard. All other attributes which are defined outside this standard are called user defined attributes.
3. How many fundamental kinds of predefined attributes are there?
a) 2
b) 3
c) 4
d) 5
Answer: d
Explanation: There are five fundamental kinds of predefined attributes which are generally named after their return type. Value kind, Function kind, Signal kind, Type kind and Range kind are the five fundamental kinds of predefined attributes.
4. What is the basic syntax to write an attribute?
a) Object_name’ attribute_name
b) Attribute_name’ Object_name
c) Object_name : Attribute_name
d) Attribute_name : Object_name
Answer: a
Explanation: To use a predefined attribute, an object is used. First of all the object name is written followed by apostrophe sign and then the attribute name. There are parameters for some attributes which can be written within parentheses immediately after the attribute name.
5. Which can’t be a result of a predefined attribute?
a) A value
b) A function
c) An entity
d) A signal
Answer: c
Explanation: As specified before, an attribute can return a value, function, signal, type or range. It can’t return an entity. The result of an attribute can be a value in case of value kind attributes and similarly for other five fundamental types.
6. How to declare a user defined attribute?
a) ATTRIBUTE name’ return_type;
b) ATTRIBUTE name : return_type;
c) ATTRIBUTE’ name : return_type;
d) ATTRIBUTE’ name’ return_type;
Answer: b
Explanation: Apostrophe sign is used at the time when we need to use the attribute but not at the time of declaration. The declaration of user defined attribute includes the keyword ATTRIBUTE followed by the name of attribute. The type is also specified at the time of declaration which is placed after a colon sign.
7. Array attributes are those which ________
a) Returns array type
b) Can be used on arrays
c) Can’t be used on arrays
d) Returns scalar values
Answer: b
Explanation: Array attributes can be used on arrays. It can be used to find the range, length and other characteristics of an array. So, it can be used to find a particular index type.
8. Which of the following is used to extract information of non-array types?
a) Vector type
b) Scalar type
c) Non vector type
d) Array type
Answer: b
Explanation: Those attributes which are used to extract information of non-array types are called Scalar type or scalar kind attributes. It can be used only on pre-defined data types and not on enumeration data types.
9. Attributes on enumeration types are synthesizable.
a) True
b) False
Answer: b
Explanation: Attributes on enumeration types are not synthesizable and can’t be used in the design which we need to synthesize. Even there are some predefined attributes that are not completely synthesizable.
10. Attributes can be associated with the entities.
a) True
b) False
Answer: a
Explanation: It is true that the attributes can be associated with entities apart from functions, values or signals. The information about entities can also be extracted with the help of attributes.
This set of VHDL Multiple Choice Questions & Answers focuses on “Value Kind Attributes”.
1. What does a value kind attribute return?
a) A single value
b) A signal
c) A function
d) A type
Answer: a
Explanation: Value kind attributes to return a single value. This value can give information about anything like an array, a block or a type. This can be used to return the length of an array or some related information.
2. Value attributes are classified into _______ subclasses.
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: Value kind attributes are further broken down into three subclasses. This classification is done on the basis of the information they provide. For example, if an attribute is providing the information about an array then it is called Value array attribute.
3. Which of the following is not a category of Value kind attribute?
a) Value type attributes
b) Value array attributes
c) Value block attributes
d) Value function attributes
Answer: d
Explanation: The Value kind attributes are divided into three categories which are Value type attributes , Value array attributes and Value Block attributes .
4. If T is an object, then T’LEFT attribute returns ________
a) Upper bound of object
b) Leftmost value of object
c) Leftmost value of an array
d) Lower bound of the object
Answer: b
Explanation: T’LEFT is an attribute which returns the left bound or the leftmost value of the object T. This object can be any predefined type, array or any block as well. Similarly, T’RIGHT returns the rightmost value of array.
5. What does the attribute T’HIGH returns?
a) Upper bound of the object
b) Lower bound of the object
c) Highest value of the object
d) Rightmost value of the object
Answer: a
Explanation: T’HIGH is another value kind attribute which gives information about the type, array or block. It returns the upper bound of the type or array. In a similar manner T’LOW will returns the lower bound of the object T.
6. What will be the value of x and y?
TYPE my_type IS ARRAY (15 DOWNTO 0) OF BIT;
…
VARIABLE x, y : INTEGER;
x := my_type’LEFT;
y := my_type’HIGH;
…
a) 0, 0
b) 0, 15
c) 15, 0
d)15, 15
Answer: d
Explanation: Since the attribute used is for the type, so it is value type attribute. ‘LEFT will give the left bound of the type or the leftmost value which is 15. Here my_type is described as a data type which has bound 0 to 15. So, HIGH will return the upper bound which is 15. So, x and y both will be 15 in this case.
7. What will be the value of x and y in the code given below?
TYPE bit_range IS ARRAY (0 TO 15) OF BIT;
VARIABLE x, y : INTEGER;
x := bit_range’RIGHT;
y := bit_range’LOW;
…
a) 0, 0
b) 0, 15
c) 15, 0
d) 15, 15
Answer: c
Explanation: T’RIGHT returns the rightmost value of any type. So, x will be 15. Similarly, T’LOW retruns the lower bound of the same. Here the bounds of the array are 0 and 15 as lower and upper bound. So, the resulting value of y will be 0.
8. What will be the type of value returned by the attribute T’LENGTH?
a) BIT
b) INTEGER
c) STD_LOGIC
d) BOOLEAN
Answer: b
Explanation: T’LENGTH is a Value Array attribute which returns the length of array. For example, if an array has 32 elements, then it will return 32. So, T’LENGTH returns a value of integer type.
9. What will be the value of my_array’LENGTH, if my_array is defined as below code?
TYPE my_array IS ARRAY (15 DOWNTO 0) OF STD_LOGIC;
a) 15
b) 16
c) 0
d) 32
Answer: b
Explanation: Since, T’LENGTH returns the length of object T. So, my_array’LENGTH will return the length of my_array. Here, my_array has 16 elements from 0 to 15, so the value returned by ‘LENGTH attribute will be 16.
10. The formula for T’LENGTH is best described by which of the following?
a) T’HIGH – T’LOW + 1
b) T’HIGH – T’LOW
c) T’HIGH + T’LOW – 1
d) T’HIGH + T’LOW
Answer: a
Explanation: T’HIGH will return the upper bound of the array and T’LOW will return the lower bound of the array. Also, the number of elements in an array is given by upper bound – lower bound + 1. Therefore, option a describes the formula best.
11. Which of the following is the return type of value T’ASCENDING?
a) Bit
b) Integer
c) Boolean
d) Same as T
Answer: c
Explanation: Ascending is a value kind attribute which can take two values either TRUE or FALSE. Regardless of type of the object T, the value returned by attribute ‘ASCENDING is always of Boolean type.
12. For which of the following declarations, the value returned by ‘ASCENDING attribute will be true?
TYPE array_1 IS ARRAY (0 TO 31) OF BIT;
TYPE array_2 IS ARRAY (15 DOWNTO 0) OF BOOLEAN;
a) For array_1 only
b) For array_2 only
c) For both array_1 and array_2
d) Neither for array_1 nor for array_2
Answer: a
Explanation: The T’ASCENDING will return true only if the array T is defined as in an ascending order. For example, areay_1 is defined from 0 to 31 whereas array_2 is defined from 15 to 0. Therefore, in case of array_1, the value will be true.
13. Which of the following attribute is available for all types?
a) ‘LEFT
b) ‘ASCENDING
c) ‘BASE
d) ‘HIGH
Answer: c
Explanation: ‘BASE is an attribute available for all the types, May it be a predefined data type or user defined data type. It returns the base type of the object. The type of object must have some base type which is returned by attribute.
14. What kind of information is provided by the value block attributes?
a) About the block name
b) About the modeling of block
c) About the architecture name
d) About the inputs used in block
Answer: b
Explanation: Value block attributes returns information about how a block in a design is modeled. For example, whether the structural modeling is used or behavioral modeling is used within a block or architecture.
15. Which of the following returns TRUE if there is no component instantiation statement in the block?
a) ‘STRUCTURE
b) ‘BLOCK_COMPONENT
c) ‘BLOCK_BEHAVIOUR
d) ‘BEHAVIOR
Answer: d
Explanation: ‘STRUCTURE and ‘BEHAVIOR are two predefined attributes that are under the category Value block. Both of them return true value. ‘BEHAVIOR will return true if there is no component declaration and instantiation inside the block to which it is attached. However, ‘STRUCTURE performs exactly opposite.
This set of VHDL Multiple Choice Questions & Answers focuses on “Function Kind Attributes”.
1. Which of the following is returned by the function kind attributes?
a) Value
b) Function
c) Signal
d) Array
Answer: a
Explanation: Function attributes return values to the designer about the types, arrays or signals used. The name doesn’t tell that the attribute will return some function. It returns the information related to the function.
2. You are given with the position number of a value within a type, which attribute will you use to find its value?
a) ‘POS
b) ‘VAL
c) ‘POSITION
d) ‘VALUE
Answer: b
Explanation: The ‘value’ specified as an argument to the attribute specifies the position number and there are only two attributes which are predefined in the VHDL among the four options given. In which ‘VAL attribute is used to return the value from position number specified.
3. A value from a type is passed as an argument to the attribute to find its position number. Which attribute it should be?
a) ‘SUCC
b) ‘PRED
c) ‘VAL
d) ‘POS
Answer: d
Explanation: ‘POS is an attribute used to return the position value within a type if the value is known. For example, if a value 63is defined on the first number and we write ‘POS, the value returned will be 1.
4. What is the function of ‘SUCC attribute?
a) To return the value next to the value passed in argument of the attribute
b) To return the value previous to the value passed in argument of the attribute
c) To return the position of value next to the value passed in argument
d) To return the position of value next to the value passed in argument
Answer: a
Explanation: The attribute ‘SUCC is used to return the next value defined in the type. The value written in the argument of the attribute will be taken as the reference and the next value from that is returned.
5. Which of the following describes the function of ‘PRED?
a) To return the position of value next to the value passed in argument
b) To return the value next to the value passed in argument of the attribute
c) To return the value previous to the value passed in the argument
d) To return the position of value next to the value passed in argument
Answer: c
Explanation: ‘PRED attribute is used to return the previous value to the value passed in argument. Here, PRED is a representation for preceding value. There is no attribute for returning the position of previous to the value passed as an argument.
6. Which of the following is equivalent to the ‘SUCC attribute?
a) ‘PRED
b) ‘LEFTOF
c) ‘RIGHTOF
d) ‘LEFT
Answer: c
Explanation: ‘SUCC attribute returns the value next to the value in the argument. Similarly, ‘RIGHTOF returns the value in the type right to the value passed as a parameter to the attribute. Therefore, both are similar.
7. Which of the following is similar to ‘PRED attribute?
a) ‘LEFTOF
b) ‘RIGHTOF
c) ‘RIGHT
d) ‘LEFT
Answer: a
Explanation: The value previous to the argument value is returned by the ‘PRED attribute. The same is done by ‘LEFTOF, it returns the value left to the argument which means the same as that of ‘PRED. However, LEFT is a value kind attribute used to return the leftmost value.
8. What would be the value of x and y in the example given below?
TYPE color IS (red, yellow, green, blue, purple, orange)
VARIABLE x,y : color;
x := color’SUCC(green);
y := color’VAL(4)
a) blue, green
b) blue, blue
c) 4, blue
d) blue, 4
Answer: b
Explanation: Since ‘SUCC attribute returns the succeeding value of the argument. In the argument, value green is used so the succeeding value is blue. Therefore, x will be blue. Also, ‘VAL will return the value at 4th position which is blue.
9. What would be the value of x and y?
TYPE color IS (red, green, blue, yellow, purple, orange, black)
VARIABLE x : INTEGER;
VARIABLE y : color;
x <= color'POS(green);
y <= color'LEFTOF(green);
a) red, green
b) green, red
c) red, 2
d) 2, red
Answer: d
Explanation: Since x is an integer type and is assigned the value returned by ‘POS attribute. The value returned will be the position of green value which is 2. Another variable y can take any value within type color. The value in the left of green is red.
10. Identify the value of variable x from the lines given below.
SUBTYPE delay_time IS TIME RANGE 10 ns to 50 ns;
VARIABLE x := delay_time'BASE
a) ns
b) time
c) 10 ns
d) 50 ns
Answer: b
Explanation: ‘BASE is an attribute that is available for all predefined and enumerated data types. It gives the base type of object. Here, the subtype is defined with the base type TIME. So, x will contain TIME.
This set of VHDL Multiple Choice Questions & Answers focuses on “Signal Kind Attributes”.
1. What is the basic use of signal kind attributes?
a) To check any event on signals
b) To check if a function is called
c) To check if a signal is IN or OUT mode
d) To check a clock signal
Answer: a
Explanation: Signal kind attributes can provide information about any signals. These attributes can be used to report whether a signal has changed its value, what was the last value and after what time the signal changed, etc.
2. Which of the following returns the Boolean type always?
a) ‘LAST_VALUE
b) ‘LAST_EVENT
c) ‘EVENT
d) ‘STABLE
Answer: c
Explanation: ‘EVENT is an attribute which returns a Boolean value always. It returns true if any transition has taken place on the given signal during the current delta. Otherwise, it returns false. It always takes a signal as its object and detects any change on the value.
3. Signal kind attributes can’t have variables as their objects.
a) True
b) False
Answer: a
Explanation: Signal kind attributes are called so because they provide information about any signal. Unlike value kind and function kind in which variables can be used objects with attributes, it is not possible to use any data object with signal kind attributes except signals.
4. Refer to the statement given below, it is used for detecting _________
IF (clk’EVENT and clk = ‘0’)
a) Rising edge of the clock signal
b) Falling edge of the clock signal
c) Clock signal frequency
d) Time period of clock signal
Answer: b
Explanation: As described earlier, ‘EVENT will detect any change on the clock signal. This attribute is here used in conjunction with a condition that clock signal should be zero. So, the statement is used to detect the trailing or falling edge of the clock signal.
5. s’ACTIVE will return true if _________
a) Any transition from 0 to 1 on signal s during the current delta
b) Any transition from 1 to 0 on signal s during the current delta
c) Any change has occurred on the signal s during last 2 delta’s
d) Any change has occurred on the signal s during the current delta
Answer: d
Explanation: s’ACTIVE is an attribute which always returns the Boolean value always. It returns true if the signal is active during the current delta. It means the value will be true if any change has occurred on the signal during the current delta. Otherwise, it returns false.
6. Attribute s‘LAST_EVENT has a return value of ______ type.
a) BOOLEAN
b) TIME
c) INTEGER
d) Same as signal s type
Answer: b
Explanation: s’LAST_EVENT is an attribute which returns the time elapsed since the previous event occurred on the signals. This attribute is very useful for implementing timing checks like pulse width check, hold check etc.
7. What is the type of value returned by the s’DELAYED attribute?
a) TIME
b) BOOLEAN
c) INTEGER
d) Same as signal s
Answer: d
Explanation: s’DELAYED attribute is used to create a delayed version of same signal, delayed by an amount specified in the argument. It creates the signal delayed by ‘time’ value. So, the return type will be same as that of signals.
8. Which of the following statement is correct to check the violation of hold time?
a) IF’EVENT) THEN
b) IF = ‘1’) THEN
c) IF = ‘0’) THEN
d) IF = ‘1’ AND clk’DELAYED’EVENT) THEN
Answer: d
Explanation: The signal is created by ‘DELAYED attribute which is delayed by hold time and then it must be used in conjunction with the ‘EVENT attribute to check any event on the signal generated. By doing this, one may check the hold time.
9. The attribute s’TRANSACTION creates a signal of type ______
a) BOOLEAN
b) BIT
c) INTEGER
d) Same as signal s
Answer: b
Explanation: s’TRANSACTION creates a signal of time BIT that toggles its value for every transaction of the signal it is attachted to. Whenever there is some change in signal s, the value of BIT signal is toogled either from 1 to 0 or from 0 to 1.
10. What is the use of s’TRANSACTION attribute?
a) Check the continuity
b) Check the hold time
c) Interrupt handling by using WAIT
d) Create a square wave
Answer: c
Explanation: The ‘TRANSACTION attribute is generally used with the WAIT statement to handle the interrupts. Without ‘TRANSACTION attribute, the WAIT statement is sensitive to the events only, but with ‘TRANSACTION it can be activated on every transaction on the BIT signal output of attribute.
This set of VHDL Multiple Choice Questions & Answers focuses on “Type Kind and Range Kind Attributes”.
1. Which of the following is only a predefined type kind attribute?
a) ‘TYPE
b) ‘BASE
c) ‘RANGE
d) ‘RIGHT
Answer: b
Explanation: Type attributes return values of a kind type. There is only one type attribute which is T’BASE where T is any object. T’BASE will return the base type of object T. This object can be single, variable or constant.
2. T’BASE attribute can be used with another attribute only.
a) True
b) False
Answer: a
Explanation: T’BASE attribute returns the base type of a type or subtype. It can be used as the prefix to another attribute. It is available for all types and can’t be used independently. It must have a value kind or function kind attribute attached to it.
3. What will x’BASE and y’BASE return in the code given below?
TYPE color IS (red, blue, green, yellow, brown)
SUBTYPE color_gun IS color RANGE red TO green
VARIABLE x : color;
VARIABLE y : color_gun;
a) color, color_gun
b) color_gun, color
c) color, color
d) red, color
Answer: c
Explanation: As specified before, ‘BASE attribute will return the base type of any type or subtype. Here x is of the type color so x’BASE will return color. Similarly, y’BASE is of type color_gun which is a subtype with its base type color. So, y’BASE will also return color.
4. What will be the value of a in the statements given below?
TYPE color IS (red, green, blue, yellow, brown, black);
VARIABLE a : color;
a := color’BASE’RIGHT;
…
a) red
b) color
c) green
d) black
Answer: d
Explanation: Since ‘BASE attribute can’t be used independently, here it is used in conjunction with ‘RIGHT attribute. So, first of all color’BASE will return type color and then the ‘RIGHT attribute will return the rightmost value in the specified type. So, a will be assigned with black.
5. How many predefined attributes are there which are range kind attributes?
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: There are two predefined attributes in VHDL which return a value kind of range. These two attributes are called Range kind attributes. The predefined range kind attributes are a’RANGE and a’REVERSE_RANGE.
6. The object of a range kind attribute can be __________
a) Any signal, variable or constant
b) An array
c) A constrained array
d) An unconstrained array
Answer: c
Explanation: Range kind attributes works only on constrained array types. The arrays which have defined bounds are called constrained array types. These attributes return the range of the given array.
7. Which of the following is the most appropriate use of range kind attributes?
a) In implementing CASE
b) In implementing LOOP
c) In implementing IF
d) In implementing ASSERT
Answer: b
Explanation: Since range kind attributes return a range of an array. This range can be used in defining the LOOP structure. For loop needs a counter which needs a range like 1 TO n. This range can be provided by the range kind attribute.
8. What will be the value of array16’RANGE and array16’REVERSE_RANGE, if the array16 is an object defined as below?
TYPE array16 IS ARRAY(15 DOWNTO 0) OF BIT
a) 15 DOWNTO 0, 0 TO 15
b) 0 TO 15, 15 DOWNTO 0
c) 0 TO 15, 0 TO 15
d) 15 DOWNTO 0, 15 DOWNTO 0
Answer: a
Explanation: ‘RANGE attribute will just give the range of array to which it is attached to. In this case, the range of array16 is 15 DOWNTO 0. The reverse range will just give the range in reverse order, which will be 0 TO 15.
9. Which of the following is a new predefined attribute in VHDL 93?
a) T’BASE
b) T’RANGE
c) T’EVENT
d) T’ASCENDING
Answer: d
Explanation: T’ASCEDING is defined in the VHDL-93 which returns a value of BOOLEAN type. It returns true if a constrained array has range defined in ascending order. Otherwise, if the range is defined like 15 DOWNTO 0 then it will return false.
10. Which of the following attribute is not synthesizable?
a) ‘RANGE
b) ‘EVENT
c) ‘BASE
d) ‘REVERSE_RANGE
Answer: c
Explanation: Since ‘BASE requires another attribute to use it. It is not supported by the logic synthesis tools. Only predefined attributes which are synthesizable are ‘RANGE, ‘REVERSE_RANGE, ‘LENGTH, ‘EVENT, ‘LEFT, ‘RIGHT, ‘HIGH, ‘LOW, LAST_VALUE and ‘STABLE.
This set of VHDL Multiple Choice Questions & Answers focuses on “Configurations”.
1. Configuration is generally associated with ________
a) Behavioral modeling
b) Dataflow modeling
c) Structural modeling
d) All of the modeling styles
Answer: c
Explanation: Configurations are generally used to connect component instances to the entity or the external interface. It is basically used with modeling at the component level which is structural modeling.
2. It is necessary to use configuration to bind entity to the architecture in case of structural modeling.
a) True
b) False
Answer: b
Explanation: Configurations are optional and usually are not supported by the synthesis tools. They are used in structural modeling but it is not necessary every time to use a configuration. It makes code more complex.
3. Among the following cases, when the configurations must be used?
a) One entity and two architectures
b) Two entities and one architecture
c) Two entities and no architecture
d) One entity and no architecture
Answer: b
Explanation: The configurations are used when there are multiple number of entities and architectures. To associate one entity with an architecture. For example, there are two different entities defining different ports and an architecture using structural modeling is defining two components with ports in both entities. In that case, configuration can be used to associate the component with a proper entity.
4. Which of the following is correct syntax for defining a configuration?
a)
FOR instantation_label : component_name
USE ENTITY library_name.entity_name[(architecture_name)];
b)
FOR instantation_label : component_name
USE ENTITY entity_name[(architecture_name)];
c)
FOR component_name : instantiation_label
USE ENTITY library_name.entity_name[(architecture_name)];
d)
FOR component_name : instantiation_label
USE ENTITY entity_name[(architecture_name)];
Answer: a
Explanation: The configuration can be directly defined by using a FOR statement in which the label where the component is instantiated is written first and then the name of component is written. Then a USE clause followed by the name of library in which entity is present to which the component is to be linked. After which the architecture name is written which should be used.
5. Which of the following part is optional in a configuration statement?
a) Instantiation label
b) Library name
c) Entity name
d) Architecture name
Answer: d
Explanation: Architecture name is optional, all other parts are compulsory in a configuration statement. Architecture name is only written if there is more than one architecture associated with the entity then only we have to write architecture name.
6. What is the use of default configurations?
a) To bind the architecture and entity
b) To configure block statements in architecture
c) To bind generics with architecture
d) To bind components with entity
Answer: a
Explanation: When there is no configuration used in structural modeling, then default configuration is used to bind the architecture and entity. Default configuration is associated with entities and architectures. The component is automatically associated with the entity by looking at its ports and modes.
7. Which of the following is true about configurations?
a) To use architecture in configurations, it must be first added to some library
b) A configuration can use more than one architecture for an entity
c) To use an entity in configurations, it must be first added to some library
d) A configuration can’t use any architecture for any entity
Answer: c
Explanation: Since the library name is written before the name of the entity, so it is necessary to add the entity in some library to use it in a configuration. Also, a configuration binds only one architecture with an entity.
8. Apart from the components ________ can also be associated with configurations.
a) Constants
b) Generics
c) Integers
d) Signals
Answer: b
Explanation: Generics can also be defined and attached with the entity by using configurations. Configuration can bind generics and architectures as well. Just like port map and generic map, configurations do the same for these two.
9. It is necessary to define entity and configuration in the same library.
a) True
b) False
Answer: a
Explanation: For any design configuration of some design entity and the configuration itself must be included in the same library. In most cases, the library used is work library, but it is not mandatory to use work every time.
10. Which of the following is not a part of the configuration statement?
a) Architecture specification
b) Instance specification
c) Binding indication
d) Library binding
Answer: d
Explanation: There are always three parts in a configuration statement. First of all architecture is specified by using FOR keyword. Second part is instance specified in which component name followed by instance label is specified. Last part of the statement is a binding indication which specifies the entity name to which architecture should be associated.
11. As a VHDL designer, what should you make sure about the design so that it is synthesized correctly?
a) It must use a configuration when more than one architecture is used
b) All the component ports and entity ports must be matched
c) A configuration must be there always
d) A configuration is used when ports are mismatched
Answer: b
Explanation: Configurations are generally not supported by synthesis tools, so one must ignore them. It should be made sure that all the ports of all components are matching with their counterparts in entities.
This set of VHDL Multiple Choice Questions & Answers focuses on “Overloading”.
1. What is the meaning of overloading?
a) To use single function many times
b) To use same object for different subprograms
c) To use same name for different objects
d) To use single function many time with single call
Answer: c
Explanation: An object is said to be overloaded when the same object name exists for multiple subprograms or types. In VHDL different type of overloading is possible such as subprogram overloading, operator overloading etc.
2. Overloading a subprogram allows subprogram to ________
a) Operate on objects of different types
b) Operate on objects of same name
c) Operate on objects of different name
d) Operate on objects of same types
Answer: a
Explanation: Overloading a subprogram means to use a single name which has multiple definitions. It allows subprograms to operate on objects of different types. For example, a user define function my_func is called with two different object one of bit_vector type and another of integer type, in this case my_func must be defined twice.
3. Using overloaded subprograms and operators increase readability of code.
a) True
b) False
Answer: a
Explanation: The result of using overloaded subprograms and operators is models that are easier to read and maintain. It frees the designer from the necessity of generating countless unique names for subprograms that do virtually the same operation.
4. What is the necessary condition to overload parameters type of a subprogram?
a) The base type of two parameters must be same
b) The parameters must have a different name
c) The parameters can’t be of integer type
d) The base type of two parameters must differ
Answer: d
Explanation: To overload argument types, the base type of parameters of two functions must be different. For example, base types do not differ when two subtypes are of the same type, in that case compiler will return an error.
5. By overloading + operator, it is possible to _________
a) Use binary addition
b) Use arithmetic addition
c) Use it as subtract operator
d) Use it as ternary operator
Answer: a
Explanation: Overloading an operator allows the operator to perform the same operations on multiple types. In this case, + operator is predefined for arithmetic operation, it can be overloaded to perform the same on binary numbers.
6. Which of the following is true about the overloading of ‘+’ and ‘-‘ operators?
a) They can be defined as binary operators only
b) They can be defined as unary operators only
c) They can be defined as ternary operators only
d) They can be defined as either binary or unary operators
Answer: d
Explanation: These are the two operators which can be defined as both binary as well as unary operators. Binary operators are those which take two operands and unary operators take a single operator. It is not possible to define them as ternary operators.
7. Apart from subprogram and operator overloading, which of the following can be overloaded in VHDL?
a) Attributes
b) Types
c) IF statement
d) CASE statement
Answer: b
Explanation: Overloading of enumeration types is also possible in case of VHDL apart from operator and subprogram overloading. This means that different types can have same name just like subprogram overloading.
8. Which of the following function definition will return an error?
SUBTYPE log4 IS BIT_VECTOR (0 TO 3)
SUBTYPE log8 IS BIT_VECTOR (0 TO 7)
FUNCTION abc (a : log4) RETURN INTEGER;
FUNCTION abc (a : log8) RETURN INTEGER;
a) Only first call
b) Only second call
c) Both first and second call
d) No error
Answer: b
Explanation: Here the function abc is overloaded and both has parameters which also have same name or they are also overloaded. So, the base type of two parameters must be different. Here both have same base type which is BIT_VECTOR. Therefore, the second function will be illegal and the error is that two functions have been declared for same base type.
9. A user wants to perform a different operation on an array type and the function can be overloaded but the parameter is of same base type. How to do the same by using a single function?
a) By using conditional statement with ‘LENGTH attribute
b) By using loop statement with ‘LENGTH attribute
c) By using unconstrained array in parameters
d) It can’t be done by using single function
Answer: a
Explanation: Since the parameter is of same base type, it is just that it has different length. So, there is no need to overload the function. It can be defined in a single function only by using conditional statements. For example, one can do it like shown below:
IF(parameter’LENGTH =n) THEN
do_this;
ELSE do_this
10. In the two functions defined below, which would generate an error?
FUNCTION abc ( a, b: std_logic) RETURNS BOOLEAN;
FUNCTION abc( a, b, c: std_logic) RETURNS BOOLEAN;
a) Only function 1
b) Only function 2
c) Both functions 1 and 2
d) No error
Answer: d
Explanation: In case of subprogram overloading, either base type or number of parameters must be different. If the number of parameters are same, then parameters can have same name. But, if both functions have same number of parameters, then the names of parameters must differ.
11. It is possible to define a new operator ++ in VHDL.
a) True
b) False
Answer: b
Explanation: Yes, It is the important point to note that we can overload any predefined operator in VHDL, but it is not legal to define new components in VHDL. This is the common mistake which beginners make, we can’t define a new operator.
12. What is the correct syntax to define a function which overloads any operator, say + operator for bit_vector type?
a) FUNCTION + RETURN bit_vector IS
b) FUNCTION ‘+’ RETURN bit_vector IS
c) FUNCTION “+” RETURN bit_vector IS
d) FUNCTION RETURN bit_vector IS
Answer: c
Explanation: Function overloading and operator overloading both are same except one point which is operator which is to be overloaded must be placed in double quotation marks. Otherwise, the syntax for both type of overloading is same.
This set of VHDL Multiple Choice Questions & Answers focuses on “Aliases and Qualified Expressions”.
1. What does an alias declaration actually do?
a) Creates a new object
b) Doesn’t create a new object
c) Creates a new signal
d) Overwrites a file
Answer: b
Explanation: An alias declaration is used for an alternative name for an existing object. An object is any signal, variable or constant. Thus, an alias creates a duplicate or xerox of the existing object but doesn’t create a new object.
2. Which of the following is the correct syntax for declaring an alias?
a) ALIAS alias_name : object_name;
b) ALIAS alias_name ; object_name;
c) ALIAS alias_name – alias_type object_name;
d) ALIAS alias_name : alias_type object_name;
Answer: d
Explanation: To declare an alias, the keyword ALIAS is used. Then, the colon sign followed by the name of ALIAS. Then, the name of the object is then specified whose alias is to be created. So, that the duplicate for that object can be created.
3. For what purpose in the following, one can use alias?
a) To divide the complex part into smaller slices
b) To decrease the simulation time
c) To make use of same memory
d) To assign different memory locations
Answer: a
Explanation: In the complex designs, for example, in the design of CPU, one may need to divide the complex part I to smaller reference slices which are easy to maintain and it also increases the readability of the code.
4. Which of the following can’t be aliased?
a) Signal
b) Loop variable
c) Variable
d) File
Answer: b
Explanation: All the objects from the VHDL can be aliased i.e. signals, variables, constants. Even all the non-objects can also be aliased except Labels, Loop parameters and Generate parameters. These are the only three exceptions.
5. An alias of array type can reverse the order of the array.
a) True
b) False
Answer: a
Explanation: It is possible to reverse the order of an array in its alias created. For example, if an array is defined with the range 0 TO 7, then its alias can also define 7 DOWNTO 0. It will be completely legal in VHDL.
6. In what way the qualified expression differs from a normal expression?
a) It has a keyword qualified in front of it
b) Its type is explicitly defined
c) Its range is defined
d) It is similar to simple expression but is synthesizable
Answer: b
Explanation: Qualified expression is an expression whose type is being explicitly specified in the expression itself. In some cases, it is necessary to specify the type other it may be ambiguous to interpret the expression.
7. Which of the following is the correct syntax to define a qualified expression?
a) ’ type
b) ” type
c) type’
d) type”
Answer: c
Explanation: To define a qualified expression, first we need to specify the type which is followed by a single quotation mark. After specifying the type, then the expression is written.
8. Where one should use the qualified expression?
a) In all overloaded functions
b) In overloaded functions with different number of parameters
c) In overloaded functions with different parameter names
d) In overloaded functions with different parameter types
Answer: d
Explanation: When the parameters in two overloaded functions are of different type, then qualified expressions may be needed. In case of different number of parameters, it is easy to identify which function is called, to the user and to the simulation tool as well. But, if there are same number of parameters but different type, then the things may be ambiguous. So, there we need to specify the type of expression.
9. Which one of the following would be the best use of qualified expression?
a) Function overloaded with bit and integer types
b) Function overloaded with bit_vector and std_logic_vector
c) Function overloaded with bit_vector and std_logic
d) Function overloaded with std_logic_vector and bit
Answer: b
Explanation: In case of function overloading, where in one function the parameter is of bit_vector type and other is of std_logic_vector type, then it could be difficult to identify that which function is being called. Say, 0110 is the argument passed to function, one can’t identify its type by seeing. So, qualified expression must be used.
10. A qualified expression is synthesizable in VHDL.
a) True
b) False
Answer: a
Explanation: A qualified expression is usually supported by synthesis tools. So, qualified expression is synthesizable, the only condition is that it should use a type which can be synthesized.
This set of VHDL Question Paper focuses on “Generate Statement”.
1. Generate statement is a _______ statement.
a) Concurrent
b) Sequential
c) Concurrent as well as sequential
d) Process
Answer: a
Explanation: Generate statement is a concurrent statement that can be used in architecture directly. It is similar to loop statement in case of sequential statement. It give designer the ability to create replicated structures.
2. There are _______ types of GENERATE statement in VHDL.
a) 2
b) 3
c) 4
d) 5
Answer: a
Explanation: There are 2 types of GENERATE statement in VHDL. One is FOR generate and other is IF generate. They can be used to replicate a structure or logic and to enable/disable a block. FOR can be used for iterative elaboration of a logic and IF can be used for conditional elaboration of some block.
3. A generate statement is generally associated with ________ modeling.
a) Behavioral
b) Data flow
c) Structural
d) Behavioral and data flow
Answer: c
Explanation: A generate statement is usually associated with component instantiation which is a part of structural modeling. For example, the FOR generate can be used to instantiate arrays of components and similarly IF can be used to instantiate the component conditionally.
4. What is the correct syntax for FOR generate statement?
a)
label : FOR parameter IN range GENERATE
begin
declarations;
concurrent statement
END GENERATE label;
b)
label : FOR parameter IN range GENERATE
declarations;
begin
concurrent statement
END GENERATE label;
c)
label : FOR parameter IN range GENERATE
declarations;
begin
sequential statement
END GENERATE label;
d)
label : FOR parameter IN range GENERATE
declarations;
begin
sequential statement
END label GENERATE;
Answer: b
Explanation: For defining a generate statement the for loop is used in conjunction with GENERATE keyword. The local declarations can be made inside a generate block. Please note that generate is a concurrent statement which can contain concurrent statements only.
5. Using a label is compulsory with a GENERATE statement.
a) True
b) False
Answer: a
Explanation: Unlike other statements of VHDL, using a label is compulsory in a GENERATE statement. This label should be unique for each different GENERATE. Moreover, this label can be used to end the generate statement as well.
6. Which of the following is a correct statement for IF generate statement?
a)
IF condition GENERATE
begin
declarations;
concurrent_statements;
END GENERATE label;
b)
label : IF condition GENERATE
declarations;
begin
sequential_statements;
END GENERATE label;
c)
IF condition GENERATE
declarations;
begin
sequential_stataements;
END GENERATE label;
d)
label : IF condition GENERATE
declarations;
begin
concurrent_statements;
END GENERATE label;
Answer: d
Explanation: A label is compulsory with IF generate statement as well. However, IF is a sequential statement, but when used with GENERATE it includes concurrent statements. The declarative part and the staements part is separated by the keyword BEGIN.
7. FOR generate creates ____________ objects.
a) Dissimilar
b) Unique
c) Different
d) Similar
Answer: d
Explanation: The generate statement will instance an array of objects which are all of homogeneous type or similar. This allows to generate multiple objects with a single statement.
8. What is realized in the code given below?
LIBRARY IEEE;
USE IEEE.std_logic_1164.all;
ENTITY my_logic IS
GENERIC n : INTEGER := 8;
PORT (sig1 : bit_vector(n-1 DOWNTO 0);
Sig2 : bit_vector(n-1 DOWNTO 0));
END my_logic;
ARCHITECTURE test OF my_logic IS
COMPONENT or2
PORT(a0, a1 : IN BIT;
z : OUT BIT);
END COMPONENT or
BEGIN
ORARRAY : FOR i IN (n-1) DOWNTO 0 GENERATE
or_gate : or2
PORT MAP ( a0 => sig1(i),
A1 => sig2(i),
z => y(i));
END GENERATE ORARRAY;
END test;
a) 7- Bit parallel adder ignoring the carry
b) 7- Bit parallel adder including the carry
c) 8- Bit parallel adder ignoring the carry
d) 8- bit parallel adder including the carry
Answer: c
Explanation: Since, a generic is used to specify the length of the arry which is assigned a value 8. The loop iterates from 7 downto 0 that means 8 times. So, an array of OR gates is instantiated by using this code including 8 OR gates. So, it is 8 bit parallel adder ignoring the carry.
9. Which of the following is legal?
a)
label : FOR n IN 7 DOWNTO 0 GENERATE
concurrent_statement;
END GENERATE;
b)
label : FOR n IN 7 DOWNTO 0 GENERATE
declarations;
concurrent_statement;
END GENERATE;
c)
label : FOR n IN 7 DOWNTO 0 GENERATE
begin
declarations;
concurrent_statement;
END GENERATE;
d)
label : FOR n IN 7 DOWNTO 0 GENERATE
begin
concurrent_statement;
END GENERATE label;
Answer: a
Explanation: If the generate statement has no local declaration which means it has only statement part then there is no need to use the BEGIN keyword. Also, label is compulsory for a generate statement but it is not mandatory to use a label at the end of the generate statement.
10. Generate statements can’t be nested.
a) True
b) False
Answer: b
Explanation: It is possible to nest multiple generate statements means we can use one generate statement inside another generate statement. This can be useful to generate to dimensional or multi-dimensional arrays.
11. Which of the following is not possible to use inside the FOR generate statement?
a) IF
b) IN
c) EXIT
d) PORT MAP
Answer: c
Explanation: It is not possible to terminate the loop early in the case of generate statement. So, no such statement can be used inside the loop which can cause it to terminate early. Therefore, such statements like EXIT, BREAK etc. can’t be used.
This set of VHDL Multiple Choice Questions & Answers focuses on “All Keywords in VHDL – 1”.
1. What is the use of ABS keyword?
a) To use only complete number
b) To convert integer operand into real number
c) To convert decimal real operand into integer
d) To return absolute value of the operand
Answer: d
Explanation: ABS keyword is used to return the absolute value of the operand. It uses only one operand and returns its absolute value. This keyword is useful when we need absolute value after division.
2. Which of the following keyword was not present before VHDL 93?
a) OR
b) NOT
c) XNOR
d) XOR
Answer: c
Explanation: All the logic functions except EXNOR operation were present in VHDL 87. XNOR keyword was added in VHDL 93. To perform XNOR function, NOT and XOR were used collectively. It was not available to use.
3. Which of the following keyword is used to declare a pointer?
a) ACCESS
b) POINT
c) POINTER
d) USE
Answer: a
Explanation: An ACCESS type is very similar to the pointers in traditional programming languages like C etc. ACCESS type is always an address or a handle to a specific object.
4. ACCESS type can’t be used in ________ directly.
a) Process
b) Architecture
c) Functions
d) Loop
Answer: b
Explanation: Access types are always variable types. By the nature of access types, they can be used in sequential processing. Therefore, it can’t be used in architecture directly. Also, access type is not synthesizable in VHDL.
5. AFTER keyword is generally used with which of the following?
a) IS
b) IF
c) Assignment
d) When
Answer: c
Explanation: Generally, AFTER keyword is generally used with concurrent assignment statement. It is used in conjunction with assignment statement to produce delays in assignment. For both type of delays, AFTER keyword is used.
6. Which of the following assignment is associated with OTHERS keyword?
a) <=
b) =>
c) :=
d) >=
Answer: b
Explanation: There are three assignment operators in VHDL. Among which <= is used for signal assignment and := is used for variable assignment. Third assignment operate is => used with OTHERS keyword only.
7. Which of the following keyword is not associated with arrays?
a) TO
b) DOWNTO
c) ARRAY
d) GROUP
Answer: d
Explanation: TO and DOWNTO are the keywords used to describe the range of array and the array keyword is used for defining an array type in VHDL. Moreover, GROUP has nothing to do with arrays. It is used to group some names.
8. Which of the following is not a reserved word in VHDL?
a) Constant
b) Identifier
c) Variable
d) Signal
Answer: b
Explanation: Constant, Variable and Signal are the reserved words for defining three different types of data objects. However, identifier is a name and not a keyword. It is not in the list of reserved words of VHDL.
9. Which of the following is a reserved word, which may be used to terminate a loop?
a) BREAK
b) CONTINUE
c) EXIT
d) NULL
Answer: c
Explanation: There is only one keyword in VHDL which may be used to terminate the loop which is EXIT. There is no keyword like BREAK and CONTINUE. Only EXIT is used to come out of the loop and start concurrent statements.
10. GUARDED keyword is associated with ______
a) BLOCK
b) PROCESS
c) FUNCTION
d) COMPONENT
Answer: a
Explanation: GUARDED is a reserved word used to define a guarded block. A guarded block is like a block that executes conditionally. It contains some guard expression which is first simplified and then only the block is executed.
This set of VHDL Assessment Questions and Answers focuses on “All Keywords in VHDL – 2”.
1. When the keyword GUARDED is used, it is always mandatory that the statements inside will be executed concurrently.
a) True
b) False
Answer: a
Explanation: Since Guarded is always used with the BLOCK statement which itself is a block statement and contains concurrent statements. So, wherever we are using guarded, it means that the statement will be executed concurrently.
2. Among the following, with which keyword MAP is generally used?
a) IS
b) PORT
c) COMPONENT
d) LABEL
Answer: b
Explanation: MAP is generally used with PORT for mapping of the components. PORT MAP statement is used for instantiation of the component after its declaration is being done.
3. Impure is a type of _______
a) Data type
b) Array
c) Function
d) Component
Answer: c
Explanation: IMPURE keyword is used to define impure functions. An Impure function is a function which can return some different type given that the actual parameters are same.
4. How does keyword inertial affect an assignment statement?
a) By defining initial value from which delay should be started
b) To prevent overriding of following delay assignment statements
c) To specify wire delay
d) No effect
Answer: d
Explanation: Inertial delay is the default delay in VHDL. If the assignment statement is y <= x AFTER 10 ns; then it will be same as y <= INERTIAL x AFTER 10 ns; There is no difference between two given statements. So, adding inertial doesn’t affect the assignment.
5. Which of the following keyword must be used to specify wire delay?
a) TRANSPORT
b) INERTIAL
c) WIRE
d) DELTA
Answer: a
Explanation: The Transport delay is analogous to the delay incurred by passing a current through a wire and therefore, it is also called wire delay. To specify the transport delay type in an assignment, the keyword TRANSPORT is used.
6. Which of the following is associated with the INOUT keyword?
a) Type of a signal
b) Mode of a signal
c) Name of a signal
d) Function of a signal
Answer: b
Explanation: INOUT is a kind of mode of a signal specified in any entity or architecture. The signal can have four modes- IN, OUT, INOUT and BUFFER. So, INOUT is a mode of signal which is used to specify the signal can be used as input as well as output type.
7. The word LABEL is not reserved in VHDL.
a) True
b) False
Answer: b
Explanation: LABEL is also a reserved word in VHDL. However, we can write the name of label in starting of any specific statement. But, LABEL itself is a reserved word used for specify a label name in an attribute statement.
8. What is LINKAGE keyword associated with?
a) Signals
b) Variables
c) Constants
d) Identifiers
Answer: a
Explanation: LINKAGE keyword is associated with signals in VHDL. It is used to link VHDL ports with non-VHDL ports. This corresponds to the mode of a signal and is used when we need to connect VHDL design to some non-VHDL ports.
9. LINKAGE keyword is same as _______ mode.
a) IN
b) OUT
c) INOUT
d) BUFFER
Answer: c
Explanation: LINKAGE is same as INOUT mode of a signal. In case of LINKAGE, we can use the signal as we can use it in INOUT mode. There is no difference between LINKAGE and INOUT modes of a signal.
10. MOD keyword is a ________
a) Data type
b) Literal
c) Operator
d) Function
Answer: c
Explanation: MOD is the modulus operator which can be used on two integer operands. It is actually an arithmetic operator which can be applied to integer types only. It returns the remainder after dividing first operand by the second operand.
This set of VHDL Problems focuses on “All Keywords in VHDL – 3”.
1. The use of NEXT in VHDL is similar to _________ in C.
a) Break
b) Continue
c) Exit
d) Do
Answer: b
Explanation: NEXT statement is used to skip the current iteration of the loop and start with the next iteration. The same is being done by the continue statement is traditional programming languages like C, C++, etc.
2. NULL keyword is most of the time useful with _______ part of _______ statement.
a) IF, IF
b) ELSIF, IF
c) OTHERS, CASE
d) NEXT, LOOP
Answer: c
Explanation: NULL keyword is useful in situations where we have to explicitly specify that no action is needed. It is generally useful in the CASE statement with OTHERS. When all the cases are specified and we don’t want to perform anything when any other case occurs, then it can be used.
3. When a port of a component is not connected to any signal, then which of the following keyword is used to indicate the situation?
a) OPEN
b) CLOSED
c) ON
d) OFF
Answer: a
Explanation: When any of the port is not connected to any signal in the component instantiation statement, then OPEN keyword is used in the association list of the statement to indicate the open port.
4. Which of the line in following code is not legal?
L1 : PROCESS(a,b)
L2 : SIGNAL x;
L3 : BEGIN
L4 : c<= a AFTER 10 ns;
L5: END PROCESS
a) L2 only
b) L4 only
c) No error
d) Both L2 and L4
Answer: d
Explanation: A SIGNAL keyword is used to declare a signal which can’t be declared inside a process. So, L2 isn’t legal. Similarly, there is no role of delay for a sequential assignment statement. So, AFTER keyword is valid for concurrent assignment statement only.
5. A POSTPONED keyword used with a process will make it wait till _________
a) A specific process is suspended
b) A signal from the sensitivity list changes
c) All the processes are suspended
d) All the signals in sensitivity list changes
Answer: c
Explanation: A POSTPONED process is the one which is executed after the end of all processes. When all of the normal processes are suspended then the execution of postponed process starts.
6. Which of the following keyword is used to identify a clocked process?
a) CLOCKED
b) CLKED
c) SEQ
d) No specific keyword
Answer: d
Explanation: A clocked process also looks like a simple process. The only difference being a clock signal is used inside a clocked process. Whenever the clock event is identified or clock is simply used in the process then it is called a clocked process.
7. RANGE keyword is always used in _______
a) Type declaration
b) Array declaration
c) Loop declaration
d) Process declaration
Answer: a
Explanation: A Type declaration always includes three parts. The name of the Type, the base type and the range for the type. This range is always declared by using keyword RANGE followed by some values.
8. If we don’t use any keyword in the function definition, then which of the following is the type of function?
a) IMPURE
b) PURE
c) CASE
d) CONCURRENT
Answer: b
Explanation: There are two kinds of functions which are PURE and IMPURE. A function by default is considered as a pure function. If we want to declare an impure function then we need to write IMPURE, but this is not in the case of Pure function.
9. The REPORT keyword is usually associated with _______
a) RECORD
b) NULL
c) ASSERT
d) IF
Answer: c
Explanation: REPORT keyword is used with ASSERT statement. Assert statement checks the consistency of simulation and execution and report in conjunction with assert is used to report the kind of error through a message.
10. On which side of a signal assignment statement, UNAFFECTED keyword can be used?
a) Left hand side
b) Right hand side
c) On any of the side
d) Can’t be used in an assignment statement
Answer: b
Explanation: UNAFFECTED is a keyword used when we need not to assign a new value to the signal. This is the case used in a selected or conditional signal assignment statements. So, it can be used as a part of waveform only i.e. on the right hand side only.
This set of VHDL Multiple Choice Questions & Answers focuses on “Flattening and Factoring of Functions”.
1. What is the process of flattening?
a) Converting an optimized function to unoptimized form
b) Converting a Boolean function to PAL format
c) Converting a Boolean function to PLA format
d) Converting a Boolean function to POS form
Answer: c
Explanation: Flattening is a process of converting the unoptimized Boolean description into a PLA format. PLA format is a format in which the description is converted into sum of products form i.e. in the form of OR and AND arrays.
2. Flattening creates a flat signal representation of ______ levels.
a) 1
b) 2
c) 3
d) 4
Answer: b
Explanation: Flattening is named so because it creates a flat signal representation of only two levels: an AND level and an OR level. Because it converts the function into PLA form in which we can implement only sum of products.
3. How will you flatten the following function?
a = b AND c;
b = x OR (y AND z);
c = q OR w;
a) a = OR OR OR ;
b) a = AND AND AND ;
c) a = OR OR OR ;
d) a = OR OR OR ;
Answer: a
Explanation: Flattening means only two levels which are AND and OR arrays. So, there must be no intermediate levels. For example, in the question given above, b and c are two intermediate signals used. So, first b and c must be solved then only a can be solved. Therefore, flattening will give the resultant shown in option a. It is Boolean equivalent of the first without any intermediate node.
4. What is the result of flattening of functions?
a) Increased readability
b) Increased speed
c) Decreased speed
d) Decreased readability
Answer: b
Explanation: Flattening of functions increase the speed of functions. Since there are no intermediate nodes, there are few logic levels from the input to the output. It is only good for smaller functions in which numbers of terms are not more.
5. In which of the following functions, the flattening is difficult?
a) Functions containing many XOR
b) Functions which are already minimal
c) Functions which are slow due to intermediate nodes
d) Functions which is always false
Answer: a
Explanation: In case, when a function has many numbers of terms, especially with XOR functions. Because a n- input EXOR gate needs 2^ terms. Due to which it becomes much complicated to convert that particular function into flattened PLA form. Due to this reason the speed decreases.
6. Which of the following is the opposite of flattening of functions?
a) Structure
b) Adding intermediate nodes
c) Un-flattening
d) Factoring
Answer: d
Explanation: Factoring is the process of adding intermediate terms or nodes to add structure to a description. So, factoring is exactly opposite of flattening in which the intermediate nodes are removed and made a single PLA function.
7. The main advantage of using factoring is ________
a) Reducing the speed
b) Reducing the number of terms
c) Adding intermediate nodes
d) Reducing flattening
Answer: b
Explanation: The main disadvantage of flattening is that it confuses the whole function by adding more number of terms in one expression which decreases the speed. To overcome this disadvantage, factoring is used to reduce the number of terms in the expression.
8. What is another name for the factoring of functions?
a) De-flattening
b) Intermediation
c) Structuring
d) De-structuring
Answer: c
Explanation: Factoring is also known as structuring. This is the name given to factoring because it structures the expressions and increases their readability. It basically uses the concept of factoring used in mathematics to do so.
9. Which factor can be there in the following two functions?
x = a AND b OR a AND c;
y = b OR c OR d
a) a AND b
b) b OR a
c) b AND c
d) b OR c
Answer: d
Explanation: After factoring, using various Boolean properties, the term b or c can be factored out to a separate intermediate node. In the first expression, if we see it is equivalent to a AND . Also, b OR c is a part of second expression as well.
10. What would be the ideal case for a design?
a) Using factoring only
b) Using flattening only
c) Using both flattening and factoring
d) Neither using flattening and nor factoring
Answer: c
Explanation: Since factoring will add an intermediate node which can reduce speed. On the other hand, the flattening process will increase the speed. But, at the same time flattening can increase the area and decrease the fan-out. This is completely opposite to factoring which reduces the area and increases the fan-out.
This set of VHDL Multiple Choice Questions & Answers focuses on “Implementing Gates with Different Modelling – 1”.
1. Which of the following is a basic building block of digital logic?
a) Wires
b) Nets
c) Gates
d) Flip-flops
Answer: c
Explanation: Any kind of digital logic can be synthesized by basic logic gates like or gate, and gate, not gate, etc. By using these simple gates, we may synthesize many difficult circuits or functions. So, gates are the building block for any digital logic.
2. Which of the following gate is a universal gate?
a) AND
b) NAND
c) EXOR
d) EXNOR
Answer: b
Explanation: NAND and NOR are two universal gates. They are called so because we may implement any kind of basic logic gate by using any of these two universal logic gates. By using NAND or NOR, we may implement AND, OR, NOT and EXOR gates.
3. By how many modeling styles, the gates in VHDL can be implemented?
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: There are three modeling styles in VHDL in which we may implement any kind of logic or logic gate. These modeling styles are behavioral modeling, dataflow modeling and structural modeling.
4. Which of the following is not needed when modeling a simple gate?
a) Library
b) Entity
c) Architecture
d) Configuration
Answer: d
Explanation: Modeling a gate is a really easy task. There is no need for adding some CONFIGURATIONS to the design. The gates can be designed with any modeling style without using any kind of configuration statement. Also, describing architecture is essential along with entity. Package is needed to have some basic functions.
5. Which kind of modeling is used in the following description?
ARCHITECTURE my_arch OF my_design IS
BEGIN
c<= a OR b;
END my_arch;
a) Behavioral
b) Data flow
c) Structural
d) Behavioral and Dataflow
Answer: b
Explanation: In such cases, where the direct relation between inputs and outputs are described. A flow of data from the input side to the output side is described by using logic functions. Therefore, it is the case of dataflow modeling.
6. What is the type of modeling used in the code given below?
ARCHITECTURE my_arch OF my_design IS
BEGIN
y <= ‘1’ WHEN a =’1’ AND b = ‘0’;
‘0’ WHEN OTHERS;
END my_arch;
a) Behavioral
b) Dataflow
c) Structural
d) Combinational
Answer: a
Explanation: When the architecture describes the behavior of the circuit with respect to different combinations of inputs, then it is called behavioral modeling. The behavioral modeling uses a selected assignment to show the value of output for different inputs.
7. The architecture describes _______ gate implemented by _________ modeling.
ARCHITECTURE my_arch OF my_design IS
BEGIN
y <= NOT(a OR b);
END my_arch;
a) Or, behavioral
b) Not, Dataflow
c) Nor, behavioral
d) Nor, Dataflow
Answer: d
Explanation: Since the logic function is used to show the flow of data from input to the output. Therefore, The architecture describes the dataflow model of a gate. Also, the function is a not function performed on the output of or function. Therefore, the design is for NOR gate.
8. Which logic gate is described by the following model, also specify the type of modeling used?
ARCHITECTURE my_arch OF my_design IS
BEGIN
WITH ab SELECT
y <= 0 WHEN “11”
1 WHEN OTHERS
END my_arch;
a) NAND, Behavioral
b) NOR, Behavioral
c) NAND, Dataflow
d) NOR, Dataflow
Answer: a
Explanation: It is clear from the architecture that the description represents a behavioral model. Now, the gate described must be the one which has low output when all of its inputs are low. Otherwise, the output is high. This is the case with NAND gate. So, the given logic is behavioral model of NAND gate.
9. Which of the logic gate is described by the following model?
ARCHITECTURE my_arch OF my_design IS
BEGIN
COMPONENT my_comp IS
PORT( a, b : IN std_logic;
y : OUT std_logic);
END COMPONENT;
L1 : my_comp PORTMAP( x, y, z);
END my_arch;
a) OR
b) NOT
c) AND
d) Can’t be determined
Answer: d
Explanation: The description is the structural model for any gate. But, it is not possible to determine which kind of gate it is. The given information is not sufficient to determine the type of the gain. It can be concluded that structural model alone is not adequate to describe any component completely.
10. The design below can’t be of ________ gate.
ARCHITECTURE my_arch OF my_design IS
BEGIN
COMPONENT or_comp IS
PORT( a, b : IN std_logic;
y : OUT std_logic);
END COMPONENT;
L1 : or_comp PORTMAP( x, y, z);
END my_arch;
a) AND
b) OR
c) NOT
d) NAND
Answer: c
Explanation: This is up to the user, what name he/she wants to give to the component. For example, a user can name an AND gate as or_gate. The name can’t describe what logic is going to be performed by the component. Here, all the gates except NOT have two inputs. Also, the component described has two ports. Therefore, the component can’t be a NOT gate.
This set of Basic VHDL Questions and Answers focuses on “Implementing Gates with Different Modelling – 2”.
1. What is the minimum number of NAND gates required to implement an EXOR gate?
a) 2
b) 3
c) 4
d) 5
Answer: c
Explanation: We can implement an EXOR gate with a minimum of 4 NAND gates. However, when we follow the conventional way to convert an EXOR logic into the NADN logic, then the number of logic gates required is 5, but 1 of them is redundant and therefore, we can implement EXOR get by using 4 NAND gates.
2. Which of the following logic describes the EXOR gate?
a) y <= OR ) AND OR );
b) y <= OR b) AND )
c) y <= AND ) OR AND );
d) y <= AND b) OR );
Answer: d
Explanation: EXOR function or Exclusive OR is a function in which two inputs of the gate can’t be at high level exclusively, in that case the output will be low. It is described by Y = A’B + AB’. This function is described in the VHDL terms by using option d. Therefore, option d represents EXOR gate.
3. What logic circuit is described by the following code?
ARCHITECTURE gate OF my_gate IS
BEGIN
WITH ab SELECT
y<= 0 WHEN “01” OR “10”;
1 WHEN OTHERS;
END gate;
a) NAND
b) NOR
c) EXOR
d) EXNOR
Answer: d
Explanation: Since the output is high when all the two inputs are either high or low. Otherwise, the output is low. This is the case opposite of EXOR gate. So, this must be EXNOR gate.
4. Sometimes gates modeled with ________ modeling may behave differently.
a) Dataflow
b) Behavioral
c) Structural
d) Structural and Behavioral
Answer: a
Explanation: Sometimes, dataflow modeling doesn’t behave as we want it to. This different behavior can be with any of the gate. For example, OR gate may behave as AND gate for instance. This occurs at the time of synthesis due to switches in the switch bank.
5. The odd behavior of gates in dataflow modeling may be the result of ________
a) Sequential statements
b) Wrong logic definitions
c) Concurrency
d) Inappropriate assignments
Answer: c
Explanation: The VHDL code is concurrent code and it has its own advantages and disadvantages. Concurrency of VHDL results in faster execution. In some PAL or PLA device, it may be like executing AND after OR execution which may result in different results.
6. Which of the following option represents a structural model for not gate?
a)
Architecture not_gate OF my_func IS
BEGIN
x: IN STD_LOGIC;
y: OUT STD_LOGIC;
END not_gate;
b)
Architecture not_gate OF my_func IS
BEGIN
x: IN STD_LOGIC;
y: OUT STD_LOGIC;
y<= NOT x;
END not_gate;
c)
Architecture not_gate OF my_func IS
BEGIN
COMPONENT NOT IS
Port( x: IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
END not_gate;
d)
Architecture not_gate OF my_func IS
BEGIN
COMPONENT not1 IS
PORT( x: IN STD_LOGIC;
y: OUT STD_LOGIC);
END COMPONENT;
END not_gate;
Answer: d
Explanation: Since the structural modeling defines only the components with their input and output ports. But the name of component can’t be same as any reserved word of VHDL.
7. In CPLD, there are many input switches arranged in a switch bank, if an AND gate is behaving oddly but could be the reason?
a) Incorrect interconnections
b) Concurrent execution of statements
c) Mismatch of ports name and switches
d) Wrong libraries included
Answer: b
Explanation: A CPLD is a device which has many input outputs and logic gates and it also includes interconnection between them. The inputs are arranged in the form of switch banks, the gate may perform different due to concurrency of the statement. Due to concurrent statements, the state of a switch can vary and which can affect the output.
8. For gates, which of the following modeling style will corresponds to shortest code?
a) Behavioral
b) Data flow
c) Structural
d) Both data flow and behavioral
Answer: b
Explanation: Since in case of dataflow modeling we just need to define the relation between inputs and outputs using some logical function. So, gates can be modeled be using dataflow style in just one line. Whereas Behavioral needs selected assignment and structural used component declaration and instantiation.
9. Generally, structural modeling is used with another modeling style.
a) True
b) False
Answer: a
Explanation: We can’t describe a logic gate or circuit by using a structural model alone. At least one more architecture is needed to properly describe the behavior of the circuit. So generally more than one architectures are used.
10. Which of the following doesn’t corresponds to NAND gate?
a)
y <= NOT( a AND b)
b)
y <= NOT a OR NOT b
c)
y <= NOT a AND NOT b
d)
WITH ab SELECT
y <= 0 WHEN ”11”
1 WHEN OTHERS
Answer: c
Explanation: Option a corresponds to NAND gate and option d is also the truth table of NAND gate. Now in option b, the gate described is bubbled OR gate which is equivalent to NAND gate. Option c corresponds to bubbled AND which is equivalent to NOR gate.
This set of VHDL written test Questions & Answers focuses on “Implementing Sequential Circuits with VHDL”.
1. A sequential logic can’t be executed by concurrent statements only.
a) True
b) False
Answer: a
Explanation: It is true that a sequential logic can’t be executed by concurrent statements only. It requires the sequential statements because they make use of a clock signal.
2. Which of the following sequential circuit doesn’t need a clock signal?
a) Flip flop
b) Asynchronous counter
c) Shift register
d) Latch
Answer: d
Explanation: Latch has an enable input, but no clock signal. All other circuits including asynchronous counter needs a clock signal. It is called asynchronous because every flip flop doesn’t have same clock signal.
3. The following timing diagram shows ______ flip flop.
vhdl-written-test-questions-answers-q3
a) T flip-flop
b) D flip-flop
c) SR flip-flop
d) JK flip-flop
Answer: b
Explanation: Since there is only one input to the flip flop, therefore, it can be either D or T flip flop. But, the output becomes equal to the input signal as soon as there is a positive edge of the clock therefore, it is a delay flip flop.
4. The process used for implementation of sequential logic in VHDL is called ______ process.
a) Sequential process
b) Combinational process
c) Clocked process
d) Unclocked process
Answer: c
Explanation: A process with a clock signal in its sensitivity list is called a clocked process. In case of sequential logic circuit, one needs a clock signal in the sensitivity list.
5. Why do we need to define clock signal in the sensitivity list of the process?
a) To trigger the statement as soon as there is some event on clock
b) To trigger the clock signal as soon as there is some event on input
c) To trigger the clock signal as soon as there is some event on output
d) To trigger the statement as soon as there is some event on input
Answer: a
Explanation: To monitor the events on clock signal, whether it is positive triggered circuit or negative triggered circuit, we need to define the clock as a signal in the sensitivity list. When it is in the sensitivity list, then every single positive or negative edge of the signal will trigger the statements inside the process.
6. A user has designed JK flip flop by using the VHDL code. The output is continuously switching between 0 and 1. This condition is known as _______
a) Switching condition
b) Master slave condition
c) Race around condition
d) Edge triggered condition
Answer: c
Explanation: This continuous switching of output between 0 and 1 may be the result of toggle state of the flip flop. This occurs when both the inputs J and K are high and the output toggles its previous state. This condition is called the race around the condition.
7. Which of the following method is not used to remove the race around condition in a flip flop?
a) Using level triggered flip flop
b) Using master slave flip flop
c) Using edge triggered flip flop
d) All of the above are used to remove the race around
Answer: a
Explanation: The race around condition in JK flip flop can be removed by two methods which are using edge triggered flip flop and by using master slave flip flop. However, using level triggered flip flop cause the race around condition.
8. Which of the following attribute is generally used in implementation of sequential circuits?
a) ‘STABLE
b) ‘LENGTH
c) ‘LAST_EVENT
d) ‘EVENT
Answer: d
Explanation: Generally ‘EVENT attribute is used in implementation of sequential circuits, because sequential circuit makes use of clock signal which needs to be detected at every positive or negative edge.
9. Which of the following line is correct for detecting positive edge of a clock?
a) IF
b) IF
c) IF
d) IF
Answer: b
Explanation: The correct way to identify the positive edge of the clock signal is shown in option b. The ‘EVENT attribute will detect the event and clk = ‘1’ will check whether its high on clock or not. In this way the positive edge is monitored. We need to use AND operator because both of the conditions should be true.
10. A user doesn’t want to use the IF statement for detecting clock edge. It is possible to do the same by using any other keyword in VHDL.
a) True
b) False
Answer: a
Explanation: It is completely possible to detect the clock edge by any other method than IF statement. One can use the WAIT statement to detect either of the edge of the clock pulse.
This set of VHDL Multiple Choice Questions & Answers focuses on “Synchronous and Asynchronous Reset”.
1. Reset is a signal that is used for the initialization of the hardware.
a) True
b) False
Answer: a
Explanation: Hardware is not capable of doing the initialization on its own, so reset is used to initialize the hardware in the beginning. Reset clears any pending event or errors in the system and brings it back to its initial state.
2. How many types of resets are there in hardware design?
a) One
b) Two
c) Three
d) Four
Answer: b
Explanation: There are two types of resets in hardware designs: Asynchronous reset and synchronous reset. Asynchronous reset works independently of the clock while synchronous reset works with respect to the clock.
3. In synchronous reset, reset is sampled with respect to _______
a) Enable signal
b) Data input signal
c) Clock signal
d) Output signal
Answer: c
Explanation: In synchronous reset, the reset signal is sampled with respect to the clock signal. After the reset signal is enabled, it won’t change until the next active clock edge. The output will change only with the positive edge of the clock.
4. Which of the following is an advantage of a synchronous reset?
a) It is slow
b) It requires a clock signal to reset the circuit
c) It filters the reset signal
d) It needs a stretched reset
Answer: c
Explanation: Synchronous reset filters the reset signal. It prevents the circuit from glitches and results in smooth functioning. Glitches don’t happen in synchronous reset because it is in synchronization with the clock signal.
5. In asynchronous reset, reset is sampled independently of the _______
a) Enable signal
b) Data input signal
c) Clock signal
d) Output signal
Answer: c
Explanation: In asynchronous reset, reset is sampled independently of the clock signal. It means, after the reset signal is enabled, it will start effective immediately and it will not wait or check for the clock edges.
6. Synchronous reset is a fast reset.
a) True
b) False
Answer: b
Explanation: Synchronous reset is slow as it requires clock signal due to which it experience clock cycle related latency. Asynchronous rest is a fast reset since it can be reset without a clock signal and hence high speeds can be achieved.
7. Which of the following is NOT an advantage of asynchronous reset?
a) It is fast
b) It doesn’t require a clock signal to reset the circuit
c) Reset gets the highest priority
d) It may cause metastability
Answer: d
Explanation: Asynchronous reset doesn’t require an active clock signal to get flip-flops to a known state, it also has a lower latency as compared to synchronous reset due to which flip-flops behave in a non-predictive manner. The reset signal must be synchronized with the clock, when it is not, it causes metastability issues.
8. Asynchronous circuit is also called ________ circuit.
a) Combinational
b) Self-timed
c) Clock circuit
d) Delayed
Answer: b
Explanation: Asynchronous circuit is also called self-timed circuit because it is not governed by a global clock signal, it mostly uses signals which show completion of operations and instructions, defined by simple data transfer protocols.
9. Designation used by a flip-flop for the reset is ________
a) PRE
b) CLR
c) D
d) Q
Answer: b
Explanation: The flip-flop is SET when the preset input is activated without considering the synchronous inputs or the clock. The flip-flop is RESET when the clear input is activated without considering the synchronous inputs or the clock.
10. Preset and clear are asynchronous inputs.
a) True
b) False
Answer: a
Explanation: Preset and clear are asynchronous inputs as they work regardless of the clock input signal. They can set or reset the flip-flop without concerning about the status of the clock.
This set of VHDL Multiple Choice Questions & Answers focuses on “Asynchronous Preset and Clear”.
1. What type of inputs is preset and clear?
a) Data input
b) Output
c) Clock input
d) Control input
Answer: d
Explanation: Preset and clear are asynchronous control inputs, which means output responds to these inputs immediately because they have control over the output that is because they are not synchronized by an external clock.
2. Clear or preset with a bar above them shows that they have ________
a) Active high input
b) Active low input
c) Clocked input
d) No input
Answer: b
Explanation: The inversion bar over the designations of preset and clear shows that they have active LOW asynchronous inputs. If the preset input is active low, then the output of the flip-flop is set to one. If the clear input is active low, then the output of the flip-flop is reset to 0.
3. Asynchronous inputs are also called override inputs.
a) True
b) False
Answer: a
Explanation: Asynchronous inputs change the state of the flip-flop regardless of the clock input, they override inputs which can force a particular state onto the flip-flop that’s why they are also called override inputs.
4. The output of the flip-flop _______ when both the input, preset and clear are active low at the same time.
a) Is set to 1
b) Is set to 0
c) Becomes X
d) Is controlled by clock
Answer: c
Explanation: If preset is active low then Q=1, Q’=0. If clear is active low Q=0, Q’=1. It is not possible to preset and clear a flip-flop at the same time because Q can’t be 0 and 1 at the same instant of time, hence the output of the flip-flop will become X, which is don’t care.
5. What is the state of PRESET input?
a) Reset
b) Set
c) Invalid
d) Don’t care
Answer: b
Explanation: After the preset input is activated, the flip-flop will be SET i.e. Q=1 and Q’=0 without considering any synchronous input or clock input. So the state of the preset input is set.
6. What is the state of CLEAR input?
a) Reset
b) Set
c) Invalid
d) Don’t care
Answer: a
Explanation: After the clear input is activated, the flip-flop will be RESET i.e. Q=0 and Q’=1 without considering any synchronous input or clock input. The flip-flop will go back to its initial state.
7. What happens if both the inputs PRE and CLR are activated?
a) Flip-flop is reset
b) Flip-flop is set
c) Invalid State
d) No output
Answer: c
Explanation: If preset input and clear input both are activated in the flip-flop then, Q and Q’ go to the same state simultaneously which is not possible. Hence, then flip-flop gives an invalid state as the output.
8. Which of the following input on a flip-flop has control over the outputs?
a) Data input
b) Clock
c) Enable
d) Preset
Answer: d
Explanation: Preset is an asynchronous input, it has the control over the output while synchronous inputs have control over the output ONLY in step, or in sync with the clock signal transitions.
This set of VHDL Multiple Choice Questions & Answers focuses on “Implementing Logic Functions with VHDL – 1”.
1. Which of the following represents the correct order?
a) Given function, optimized function, implementation
b) Optimized function, implementation, given function
c) Implementation, optimized function, given function
d) Given function, implementation, optimized function
Answer: a
Explanation: First of all we are given with a logic function that is first optimized before implementing it. The optimization is first done by using a suitable method and then it is implemented in the VHDL.
2. Which of the following will reduce the cost of implementation?
a) Implementing with only one modeling style
b) Implementing with dataflow modeling
c) Optimization
d) Generating Net list first
Answer: c
Explanation: Optimization is the technique to get the minimal form for a given logic function. By implementing this minimal function, the cost of implementation is reduced significantly.
3. Which of the following is not a method of optimization of logic function?
a) Tabular method
b) By using Boolean laws
c) K-map
d) Rectangular method
Answer: d
Explanation: There are various methods available for optimization of logic functions like K-map, Boolean reduction, tabular method and cubical method. There is no such method called rectangular method to optimize the logic function.
4. Which of the following k-map represents the following given function?
y = AB + AB’C + A’BC
a) vhdl-questions-answers-implementing-logic-functions-vhdl-1-q4a
b) vhdl-questions-answers-implementing-logic-functions-vhdl-1-q4b
c) vhdl-questions-answers-implementing-logic-functions-vhdl-1-q4c
d) vhdl-questions-answers-implementing-logic-functions-vhdl-1-q4d
Answer: d
Explanation: In the logic function there are three terms, AB’C representing 101 and A’BC representing 011. Third term is AB which will corresponds to two 1’s which are ABC and ABC’ corresponding to 111 and 110.
5. Which of the following is equivalent to the Boolean expression A + AB?
a) A
b) B
c) AB
d) A + B
Answer: a
Explanation: This expression can bide minimized by using simple Boolean laws. In the given expression, let us take A common. This becomes A , According to sum laws of Boolean expressions, 1 + B must be equal to 1. So, it becomes A.1 which is equivalent to A.
6. Which of the following assignment statement is not generally used in the implementation of Boolean functions?
a) Concurrent assignment
b) Sequential assignment
c) Conditional assignment
d) Selected assignment
Answer: b
Explanation: Generally, these kind of optimized Boolean function doesn’t need any sequential processing and therefore, no sequential assignment is required. All the functions can be implemented with concurrent code only.
7. Which of the following are prime implicants of the following Boolean function?
Y= AB + BC'D’ + BCD'
a) A, B, C, D
b) AB, BC’D’, BCD’
c) AB, BD’
d) AB, CD
Answer: b
Explanation: Prime implicants of a function are the terms in the given function without any minimization. In this case the prime implicants are AB, BC’D’, BCD’.
8. How many logical operations are required to implement a Boolean function XY + X?
a) 0
b) 1
c) 2
d) 3
Answer: a
Explanation: The given function XY + X is first optimized to reduce the cost of implementation. So, the optimized function will be equal to X. As XY + X = X = X. To implement this no logical operation is needed. It just needs an assignment statement and no operation.
9. Look the code given below. Which of the following option is implemented by the VHDL code?
ARCHITECTURE my_func OF my_logic IS
BEGIN
y <= a AND (b XNOR c);
END my_func;
a) B’C’ + BC
b) AB’ + A’B
c) AB’C’
d) ABC + AB’C’
Answer: d
Explanation: The given function is a AND . So, It is Y = A. = AB’C’ + ABC. So, option ABC + AB’C’ is the correct function which is implemented by the code.
10. What is the VHDL code for the logical function AB’C + ABC + BC?
a)
ARCHITECTURE my_logic OF my_logic IS
BEGIN
y <= (a AND b AND c) AND (b AND c);
END ARCHITECTURE;
b)
ARCHITECTURE my_logic OF my_logic IS
BEGIN
y <= (a AND c) OR (b AND c);
END ARCHITECTURE;
c)
ARCHITECTURE my_logic OF my_logic IS
BEGIN
y <= (a AND c) AND (b OR c);
END ARCHITECTURE;
d)
ARCHITECTURE my_logic OF my_logic IS
BEGIN
y <= (a AND b AND c) OR (b AND c);
END ARCHITECTURE;
Answer: b
Explanation: As per the process the function will be implemented after optimization. To optimize the function, AB’C + ABC + BC = AC + BC = AC + BC. So, the correct statement should be A AND C OR B AND C.
This set of Tricky VHDL Questions and Answers focuses on “Implementing Logic Functions with VHDL – 2”.
1. What do you use to perform basic logic functions in VHDL while creating concurrent code?
a) Operators
b) If statement
c) PROCESS
d) GENERATE
Answer: a
Explanation: Operators are the most basic ways of creating concurrent code. These operators may be logical, arithmetic, shift operators or so on. Generally, logical operators are used in logic functions.
2. In the implementation of following function by using NAND keyword only, can be done in _____ operations.
X = A'B + AB'
a) 2
b) 3
c) 4
d) 5
Answer: c
Explanation: The given logic function resembles the export operation. An EXOR gate can be implemented by using 4 NAND operations. Therefore, the NAND keyword will be used 4 times in implementation of this function.
3. The maximum number of parameters in port map function while implementing logic function using gates only, is equal to ____________
a) Number of inputs
b) Number of outputs
c) Number of inputs + number of outputs
d) Infinite
Answer: c
Explanation: A port map function is used in structural modeling in which we use port map fumction to map a given structure. The parameters of port map identify the inputs and outputs of the circuit respectively starting from the left. Therefore, a port map can have maximum parameters as the sum of number of inputs and outputs of the port.
4. Which of the following is not representing a nibble?
a) x<= “0101”
b) x<= STD_LOGIC_VECTOR
c) x<= STD_LOGIC_VECTOR
d) x<= BIT_VECTOR
Answer: b
Explanation: A nibble is a group of 4 bits. In case of option x<= “0101”, it is clear that x is a group of 4 bits. Similarly in x<= STD_LOGIC_VECTOR and x<= BIT_VECTOR , we have four bits. But, in option x<= STD_LOGIC_VECTOR , we have 5 bits from 0 to 4. Therefore, option x<= STD_LOGIC_VECTOR is not a nibble.
5. In designing logic functions in VHDL, we can use arithmetic operators.
a) True
b) False
Answer: a
Explanation: It is completely legal to use arithmetic operator in implementation of a logic or Boolean function. We can obviously use arithmetic operators like +, -, * etc. in the logic functions, if required. It will not contain any error.
6. A “Multiplication by 2” logic is to be designed by using the VHDL code, which of the following operator can be used to implement the same?
a) SRL
b) SRA
c) SLA
d) SLL
Answer: d
Explanation: In binary number system, when we multiply a number by 2, it shifts one position to the left. For example, 4, when multiplied by 2, it becomes 8. So, it is clear that one can easily make multiplication by 2 logic by using a single operator called SLL or Shift Left Logical.
7. What kind of logic is represented by the given code?
ARCHITECTURE my_func OF my_logic IS
BEGIN
y <= x SRL 2;
END my_func;
a) Divide by 2
b) Divide by 4
c) Multiply by 2
d) Multiply by 4
Answer: b
Explanation: Since the code is using a shift right operator, therefore, it must be something to be divided. So, x is divided here and the result is stored in y. Here, the x is shifted to 2 positions right, which means that it is a divide by 4 (= 2 2 ) logic.
8. What information is not provided by the given logic’s output?
ARCHITECTURE my_func OF my_logic IS
BEGIN
y <= x SRL 2;
END my_func;
a) Result of the operation
b) Operands used
c) Remainder of the operation
d) Everything about the operation will be determined
Answer: c
Explanation: Because only a shift operator is used this will act as divide by 4 logic. But, if there is any remainder of the operation, that can’t be determined by the output. For that purpose a statement with REM operator must be used.
9. A user wants to implement a logic by using VHDL. In which he has inputs from two sensors which are smoke sensor and water level detector. If any input is high, he has to turn on the respective alarm. Which of the following is representing the correct code for the given logic?
a)
ARCHITECTURE alarm_control OF my_home IS
BEGIN
PROCESS(smoke_sensor, water_sensor)
BEGIN
IF(smoke_sensor = ‘1’) THEN fire_alarm = ‘1’;
ELSE fire_alarm = ‘0’;
END IF;
IF(water_sensor = ‘1’) THEN water_alarm = ‘1’;
ELSE water_alarm = ‘0’;
END IF;
END PROCESS;
END alarm_control;
b)
ARCHITECTURE alarm_control OF my_home IS
BEGIN
PROCESS(smoke_sensor, water_sensor)
BEGIN
IF(smoke_sensor = ‘1’) THEN fire_alarm = ‘1’;
ELSE fire_alarm = ‘0’;
END IF;
IF(water_sensor = ‘1’) THEN water_alarm = ‘0’;
ELSE water_alarm = ‘1’;
END IF;
END PROCESS;
END alarm_control;
c)
ARCHITECTURE alarm_control OF my_home IS
BEGIN
PROCESS(smoke_sensor, water_sensor)
BEGIN
IF(smoke_sensor = ‘1’) THEN fire_alarm = ‘0’;
ELSE fire_alarm = ‘1’;
END IF;
IF(water_sensor = ‘1’) THEN water_alarm = ‘1’;
ELSE water_alarm = ‘0’;
END IF;
END PROCESS;
END alarm_control;
d)
ARCHITECTURE alarm_control OF my_home IS
BEGIN
PROCESS(smoke_sensor, water_sensor)
BEGIN
IF(smoke_sensor = ‘0’) THEN fire_alarm = ‘1’;
ELSE fire_alarm = ‘0’;
END IF;
IF(water_sensor = ‘0’) THEN water_alarm = ‘1’;
ELSE water_alarm = ‘0’;
END IF;
END PROCESS;
END alarm_control;
Answer: a
Explanation: When the input to the controller is high from any of the sensor, then the respective alarm status should be high. This can be easily implemented by using IF control statements. So, by using IF statement, one can set the fire alarm if smoke sensor is giving a high input. Otherwise, water level detector will turn the water alarm on.
10. Optimized implementation of Boolean functions reduces the cost of implementation.
a) True
b) False
Answer: a
Explanation: By using a suitable method for optimization, the number of prime implicants will be reduced and hence less number of logical operations need to be performed in the VHDL code. This reduction will reduce the cost of implementation.
This set of VHDL Multiple Choice Questions & Answers focuses on “Implementing Combinational Circuits with VHDL – 1”.
1. Which of the following is a not a characteristics of combinational circuits?
a) The output of combinational circuit depends on present input
b) There is no use of clock signal in combinational circuits
c) The output of combinational circuit depends on previous output
d) There is no storage element in combinational circuit
Answer: c
Explanation: A combinational circuit is the one which has no storage of previous output. The next state or output of the combinational circuit depends only on its present input and hence no clock signal is required.
2. Sequential code can’t be used to design combinational circuit.
a) True
b) False
Answer: b
Explanation: There is no restriction on usage of any kind of statements while realizing a combinational circuit. Combinational circuit may be implemented by using statements like IF, CASE etc.
3. Which of the following is not a combinational circuit?
a) Adder
b) Code convertor
c) Multiplexer
d) Counter
Answer: d
Explanation: Since counter makes use of either clock signal or previous output to determine next state. Therefore, counter is a sequential circuit and all the others like multiplexer, adder and code convertors are the examples of combinational circuit.
4. The code given below is a VHDL implementation of _________
ARCHITECTURE my_circuit OF my_logic IS
BEGIN
WITH ab SELECT
y <= x0 WHEN “00”;
x1 WHEN “01”;
x2 WHEN “10”;
x3 WHEN “11”;
END my_circuit;
a) 4 to 1 MUX
b) 1 to 4 DEMUX
c) 8 to 1 MUX
d) 1 to 8 DEMUX
Answer: a
Explanation: In the given architecture, the output is single , which is selected with the help of a and b. So, a and b are select lines and y is the output which is selected from 4 inputs. Therefore, it is the multiplexer circuit with 4 inputs and 1 output.
5. Which of the following line of the code contains an error?
L1: ARCHITECTURE mux1 OF mux IS
L2: BEGIN
L3: y<= x0 WHEN x = ‘0’ ELSE
L4: <= x1 WHEN x = ‘1’;
L5: END mux1;
a) L2
b) L3
c) L4
d) No error
Answer: d
Explanation: There is no error in the given piece of the code. However, there was no need to use WHEN in the line L4 because there is no other case to be selected from many inputs. Last case can be directly expressed without any use of WHEN.
6. In a given combinational circuit, the concurrent statements are used with selected assignments using WHEN and ELSE keyword. What is the other alternative to implement the same?
a) WITH-SELECT
b) WITH-SELECT-WHEN
c) IF-ELSE
d) CASE
Answer: b
Explanation: Because only concurrent statements can be used, therefore, WITH-SELECT is the correct alternative for the method used by the user. But, WITH-SELECT also requires WHEN keyword to implement the selected assignment.
7. Which of the following entity declares the ports of a 3 by 8 decoder?
a)
ENTITY decoder IS
PORT( inp : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
Outp: OUT STD_LOGIC_VECTOR(8 DOWNTO 0));
END decoder;
b)
ENTITY decoder IS
PORT( inp : IN STD_LOGIC_VECTOR(8 DOWNTO 0);
Outp: OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
END decoder;
c)
ENTITY decoder IS
PORT( inp : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
Outp: OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
END decoder;
d)
ENTITY decoder IS
PORT( inp : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
Outp: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END decoder;
Answer: d
Explanation: In a 3 by 8 decoder, there must be 3 inputs and 8 outputs. For 3 inputs the dimension of vector must be 2 DOWNTO 0 and for output the dimensions should be 7 DOWNTO 0. Therefore, option d is the correct port entity of the 3 by 8 decoder.
8. For using a process to implement a combinational circuit, which signals should be in the sensitivity list?
a) Inputs of the circuit
b) Outputs of the circuit
c) Both of the Inputs and Outputs
d) No signal should be in the sensitivity list
Answer: a
Explanation: In a process used for the implementation of the combinational circuit, all the input signals used which are to be read, should appear in its sensitivity list. In a combinational circuit, there can be many inputs and those inputs should appear in the sensitivity list of the process.
9. A 4 to 16 decoder can be used as a code converter. What will be the inputs and outputs of the converter respectively?
a) Binary, Octal
b) Octal, Binary
c) Hexadecimal, Binary
d) Binary, Hexadecimal
Answer: c
Explanation: Since, 2 4 = 16, therefore, the decoder can act as hexadecimal to binary converter. Because, 4 bits input is converted to 16 bits output. Each bit corresponding to 4 output bits. So, clearly it is a hexadecimal to binary convertor.
10. Following entity may represent a ________ circuit.
ENTITY my_circuit IS
PORT (a, b : IN STD_LOGIV_VECTOR(3 DOWNTO 0);
x : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
y : OUT STD_LOGIC);
END my_circuit;
a) Half adder
b) Full adder
c) Multiplexer
d) Parallel adder
Answer: d
Explanation: The entity gives information about inputs and outputs of the circuit. The circuit has two inputs and both are of vector type. There is one vector output and another single bit output. Therefore, it has to be an adder, but because 4 bits are there in the input and output so it is a 4-bit parallel adder.
This set of Tough VHDL Questions and Answers focuses on “Implementing Combinational Circuits with VHDL – 2”.
1. The process statement used in combinational circuits is called ______ process.
a) Combinational
b) Clocked
c) Unclocked
d) Sequential
Answer: a
Explanation: The process, in which no clock signal is used, is called a combinational process. In a combinational process, the sensitivity list doesn’t include any clock signal for synchronization. In the case of sequential circuits the clock signal is used.
2. Why we need to include all the input signals in the sensitivity list of the process?
a) To monitor the output continuously
b) To monitor the input continuously
c) To make the circuit synthesizable by EDA tools
d) No special purpose
Answer: b
Explanation: If the input signals are not in the sensitivity list of the process, then one can’t monitor the change in input. Any change in input signal will not change the output simultaneously by running the process again.
3. If only two bit vectors are allowed to use in the VHDL code, then how many number of MUX will be required to implement 4 to 1 MUX?
a) 1
b) 2
c) 3
d) 4
Answer: c
Explanation: Since we have inputs with two bits only, so we can use 2 to 1 MUX to implement the required design. So, to design 4 to 1 MUX, we need 3 2 to 1 MUX and hence we can get the desired circuit by using 3 multiplexers.
4. A package is designed called mux4to1_package, in which a component called mux4to1 is defined, which is a 4 to 1 multiplexer. Now a user wants to design a 16 to 1 MUX by using the same component only, how many times he needs to use the PORT MAP statement?
a) 2
b) 3
c) 4
d) 5
Answer: d
Explanation: The problem statement says that a 16:1 MUX is to be designed by using 4:1 multiplexers only. This can be done by using 5 numbers of 4 to 1 multiplexers. Here, 4 MUXs are required to collect all the inputs and one is used to select one from the 4 multiplexers outputs.
5. In designing a 2 to 1 demultiplexer with input d, output y and select line s, which of the following is a correct process statement?
a) PROCESS
b) PROCESS, d, s)
c) PROCESS, d)
d) PROCESS
Answer: a
Explanation: In a combinational process, the sensitivity list must include all the inputs. For a 2 to 1 MUX, there must be 2 inputs which are d and d; also the process should be sensitive to the select line, so s also should be in the sensitivity list.
6. The given code represents a convertor. Which kind of convertor it is?
ENTITY convert IS
PORT(b: IN STD_LOGIC_VECTOR(3 DOWNTO 0);
x : OUT STD_LOGIC_VECTOR(7 DOWNTO 0));
END convert;
ARCHITECTURE convertor OF covert IS
BEGIN
PROCESS(b)
BEGIN
CASE b IS
WHEN “0000” => x <= “1111110”;
WHEN “0001” => x <= “0110000”;
WHEN “0010” => x <= “1101101”;
WHEN “0011” => x <= “1111001”;
WHEN “0100” => x <= “0110011”;
WHEN “0101” => x <= “1011011”;
WHEN “0110” => x <= “1011111”;
WHEN “0111” => x <= “1110000”;
WHEN “1000” => x <= “1111111”;
WHEN “1001” => x <= “1110011”;
WHEN OTHERS => x <= “0000000”;
END CASE;
END PROCESS;
END convertor;
a) Gray to BCD
b) 7 segment to BCD
c) BCD to gray
d) BCD to 7 segment display
Answer: d
Explanation: Clearly, it is a BCD to 7 segment display convertor. This circuit takes a 4 bit BCD input and convert it into 7 bits output which may be used for LED output and hence the 7 segment display can be operated.
7. What is the function of the below code?
ENTITY my_logic IS
PORT (din : STD_LOGIC_VECTOR(7 DOWNTO 0);
Count : STD_LOGIC_VECTOR(3 DOWNTO 0));
END my_logic;
ARCHITECTURE behavior OF my_logic IS
BEGIN
Count <= “0000”
PROCESS(din)
BEGIN
L1: FOR i IN 0 TO 7 LOOP
IF(din(i) = ‘1’) THEN
Count = count+1;
ELSE
NEXT L1;
END LOOP;
END PROCESS;
END behavior;
a) To count number of ones in the given data
b) To count number of zeroes in the given data
c) To reverse the order of given data
d) To perform binary multiplication of two data inputs
Answer: a
Explanation: Because a loop is used and din is monitored for every bit. If any bit in the din is one then the counter is incremented by one. Therefore, the code is counting the number of ones in a given vector of bits.
8. What will be the value of count output, if the data din is 11001111?
ENTITY my_logic IS
PORT (din : STD_LOGIC_VECTOR(7 DOWNTO 0);
Count : STD_LOGIC_VECTOR(3 DOWNTO 0));
END my_logic;
ARCHITECTURE behavior OF my_logic IS
BEGIN
Count <= “0000”
PROCESS(din)
BEGIN
L1: FOR i IN 0 TO 7 LOOP
IF(din(i) = ‘1’) THEN
Count = count+1;
ELSE
NEXT L1;
END LOOP;
END PROCESS;
END behavior;
a) 6
b) 0110
c) 2
d) 0010
Answer: b
Explanation: The count is a signal of bit vector type and hence the output will be a stream of bits. In this case there are 6 ones in the input, which corresponds to 0110 in the binary number system.
9. In the combinational process, the use of output signal in the sensitivity list is illegal.
a) True
b) False
Answer: b
Explanation: Though it is not illegal to use any output signal in the combinational process; but it is not good practice to do. The change in output will cause the process to run again which is not desirable. We can use the output signal in sensitivity list but it will not give desirable results.
10. A parity generator is a combinational circuit and is designed by using a combinational process.
a) True
b) False
Answer: a
Explanation: A parity generator is a combinational circuit since its output depends on the present input only. Also, no clock signal is required to implement and synchronize the parity generator so it can be implemented by combinational process.
This set of VHDL Multiple Choice Questions & Answers focuses on “Designing Shift Registers with VHDL”.
1. Shift registers comprise of which flip-flops?
a) D flip-flops
b) SR flip-flops
c) JK flip-flops
d) T flip-flops
Answer: a
Explanation: Shift registers comprise of a few single bit D flip-flops, one flip-flop for one data bit, either logic “1” or a “0”. They are connected together to form a sequence so that the output from the first flip-flop becomes the input of the second flip-flop and so on.
2. In serial input serial output register, the data of ______ is accessed by the circuit.
a) Last flip-flop
b) First flip-flop
c) All flip-flops
d) No flip-flop
Answer: b
Explanation: In serial input serial output register, the data of first flip-flop is accessed by the rest of the circuit and in serial input parallel output register, the data of the last flip-flop is accessed by the circuit.
3. In PIPO shift register, parallel data can be taken out by ______
a) Using the Q output of the first flip-flop
b) Using the Q output of the last flip-flop
c) Using the Q output of the second flip-flop
d) Using the Q output of each flip-flop
Answer: d
Explanation: In PIPO shift register there are parallel input pins to which data is presented in a parallel format and then the data is transferred to their respective output pins altogether by the same clock pulse. One clock pulse unloads and loads the data of one register, which requires it to use all the output pins of each and every flip-flop.
4. Four bits shift register enables shift control signal in how many clock pulses?
a) Two clock pulses
b) Three clock pulses
c) Four clock pulses
d) Five clock pulses
Answer: c
Explanation: One bit is shifted into the register in one clock cycle for data conversion so four bits will be shifted into the register in four clock pulses.
5. Time taken by the shift register to transfer the content is called _______
a) Clock duration
b) Bit duration
c) Word duration
d) Duration
Answer: c
Explanation: Serial computer needs less hardware because one circuit can be used over and over again to manipulate the bits that come out of the shift register. The time required by the shift register to shift the entire content is called word duration.
6. Transfer of one bit of information at a time is called _______
a) Rotating
b) Serial transfer
c) Parallel transfer
d) Shifting
Answer: b
Explanation: Movement of data at a rate of one bit per clock pulse from one end of the shift register to the other end is called serial transfer. Movement of data into all flip-flops at the same time is called parallel transfer.
7. Clock divider slow down the input clock of the shift register.
a) True
b) False
Answer: a
Explanation: Clock divider is also called frequency divider as it divides the input clock frequency and generates the output clock. VHDL code has a clock and resets as input and output as a divided clock.
8. Shift registers are used to delay the data signal.
a) True
b) False
Answer: a
Explanation: Shift registers are used to delay the data signal so that it can be used later for a data operation or output. One example could be, equalization of two parallel signals: a data and a data valid indicator. Data valid indicator is commonly used for the delay.
9. In gated D latch, which of the following is the input symbol?
a) D
b) Q
c) EN
d) CLK
Answer: a
Explanation: In the gated D latch, D is the data input, EN is active high enable, Q is the data output, CLK is the clock pulse.
10. Which register is used in the following code?
library ieee;
use ieee.std_logic_1164.all;
entity shift_siso is
port (Clock, Sin : in std_logic;
Sout : out std_logic);
end shift_siso;
architecture behav of shift_siso is
signal temp: std_logic_vector(7 downto 0);
begin
process (Clock)
begin
if (Clock'event and Clock='1') then
for i in 0 to 6 loop
temp(i+1) <= temp(i);
end loop;
temp(0) <= Sin;
end if ;
end process;
Sout <= temp(7);
end behav;
a) Serial in serial out
b) Serial in parallel out
c) Parallel in parallel out
d) Parallel in serial out
Answer: a
Explanation: In the above code, serial in serial out 8-bit register is used. It delays the data and stores it for each register. It may be 64 bits in length, longer if registers and packages are cascaded.
This set of VHDL Multiple Choice Questions & Answers focuses on “Designing Counters with VHDL”.
1. The ring counter is a serial shift register with feedback from the output of the last flip-flop to the input of the first flip-flop.
a) True
b) False
Answer: a
Explanation: Ring counter is a serial shift register based on continuous circulation. Feeding back the output of the serial shift register to its input without inversion creates a circuit.
2. Which of the following flip-flop is used by the ring counter?
a) D flip-flops
b) SR flip-flops
c) JK flip-flops
d) T flip-flops
Answer: a
Explanation: Ring counter comprises of a few single bit D flip-flops, one flip-flop for one data bit, either a logic 1 or a 0. They are connected together to form a sequence so that the output from the first flip-flop becomes the input of the second flip-flop and so on.
3. ‘shift_reg’ is used to initialize the _____________ in the shift register.
a) LSB
b) MSB
c) Register type
d) Register bits
Answer: b
Explanation: Shift register uses ‘shift_reg’ for the initialization. It sets the value of MSB in the shift register with the following code:
:= X”80″;)
4. How many types of shift operators are there in VHDL?
a) Three
b) Four
c) Five
d) Six
Answer: d
Explanation: There are six types of shift operators in VHDL: rol , ror , sll , srl , sla , sra .
5. How many types of the data type are there in the ring counter?
a) One
b) Two
c) Three
d) More than three
Answer: d
Explanation: There are more than three data types in VHDL, some of them are: STD_LOGIC_VECTOR data type – for more than one bit, the STD_LOGIC data type – for a single bit, the BIT_VECTOR data type – for two or more bits, STD_LOGIC_UNSIGNED data type – for addition and subtraction.
6. In __________ counter universal clock is not used.
a) Synchronous counter
b) Asynchronous counter
c) Decade counter
d) Ring counter
Answer: b
Explanation: In asynchronous counter, the universal clock is not used, only the first flip-flop is operated by the main clock and output of the previous flip-flops operates the clock input of the rest of the counters.
7. Synchronous counter use ________ global clock, unlike asynchronous counter.
a) One
b) Two
c) Three
d) zero
Answer: a
Explanation: Synchronous counter use one global clock that operates each flip flop and changes the output in parallel. One advantage of the synchronous counter as compared to asynchronous counter is, it can work on a much higher frequency than the asynchronous counter.
8. Asynchronous counters are generally used in circuits with higher frequency, where a large number of bits are involved.
a) True
b) False
Answer: b
Explanation: In asynchronous counters, there are small delays between the arrival of the clock pulse at the input due to the internal circuit of the gate so, if the delay of the all the stages are added together the total delay at the end of the counter can be very large. Therefore, asynchronous counters are not used in high-frequency circuits where large numbers of bits are involved.
9. How many different states does a decade counter count?
a) Eight
b) Nine
c) Ten
d) Eleven
Answer: c
Explanation: Ten different states are counted by a decade counter. It then resets to its initial state. A simple decade counter counts from 0 to 9. Also, counters could be made which can go through any ten states between 0 to 15.
10. The number of flip-flops used in a counter is _________ number of states in the counter.
a) Greater than
b) Less than
c) Equal to
d) Greater than equal to
Answer: d
Explanation: Number of flip-flops used in a counter is greater than equal to the number of states in the counter. It can be calculated by using ‘log2 n’ where n=number of states in the counter.
11. Two decade counters cascaded together will divide the input frequency by ________
a) 10
b) 100
c) 1000
d) 10000
Answer: b
Explanation: A decade counter has 10 states, so it divides the input frequency by 10. Two decade counters will divide the input frequency by 10*10=100.
This set of VHDL Multiple Choice Questions & Answers focuses on “Designing Moore Type FSM with VHDL”.
1. Output values of Moore type FSM are determined by its ________
a) Input values
b) Output values
c) Clock input
d) Current state
Answer: d
Explanation: The output values of a Moore type FSM are determined only by its current state. The output is computed by the state outputs which serve as the input in the flip-flop. The output changes synchronously with the clock edge and state transition.
2. Moore machine output is synchronous.
a) True
b) False
Answer: a
Explanation: Output of the Moore type FSM are synchronous, it works with respect to the clock and change only with the state transition. Mealy type FSM gives asynchronous output.
3. Finite state machines are combinational logic systems.
a) True
b) False
Answer: b
Explanation: Finite state machines are SEQUENTIAL logic systems. In sequential logic systems, the output depends on the inputs and also on the present state of the system. It consists of a set of states, set of rules for moving from state to state, inputs and outputs.
4. What happens if the input is high in FSM?
a) Change of state
b) No transition in state
c) Remains in a single state
d) Invalid state
Answer: a
Explanation: The system changes the state as long the input is high. The system also has an output which is 1 if the input is high since there is a change in state which leads to the output.
5. What happens if the input is low in FSM?
a) Change of state
b) No transition in state
c) Remains in a single state
d) Invalid state
Answer: b
Explanation: There is no transition in the state if the input is low. If the system is in a particular state, it remains in that state only until the input becomes high. The system also has an output which is 0 if the input is low since there is no change in the state, it doesn’t reach the output state.
6. In FSM diagram what does circle represent?
a) Change of state
b) State
c) Output value
d) Initial state
Answer: b
Explanation: In FSM diagram circle represent the states. For example: Assume there are four states in an FSM i.e. A, B, C and D. The encircled one out of the four will represent the state. If B is encircled, it shows FSM is in state B.
7. In the FSM diagram, what does arrow between the circles represent?
a) Change of state
b) State
c) Output value
d) Initial state
Answer: a
Explanation: In the FSM diagram, arrows between the circles represent the change of one state to another state. For example: Assume there are four states in an FSM i.e. A, B, C and D. The arrow between the states A and B show the transition of state from A to B.
8. In the FSM diagram, what does the information below the line in the circle represent?
a) Change of state
b) State
c) Output value
d) Initial state
Answer: c
Explanation: In the FSM diagram the information below the line in the circle represents the output value when in each state. It is represented by 1 and 0. If there is a state change then 1, otherwise 0.
9. Moore machine has _________ states than a mealy machine.
a) Fewer
b) More
c) Equal
d) Negligible
Answer: b
Explanation: In Moore type FSM, more logic is required to decipher the outputs which result in more circuit delays. Moore machines generally respond one clock cycle later while mealy machines respond in the same clock cycle. That is why Moore machines require more states.
10. State transition happens _______ in every clock cycle.
a) Once
b) Twice
c) Thrice
d) Four times
Answer: a
Explanation: Every arrow shows a transition from one state to another, transition of state happens once in one clock cycle. Depending on the present input, it may go to a different state every time so there is a change of state only one time.
This set of VHDL Puzzles focuses on “Designing Mealy Type FSM with VHDL”.
1. Output values of mealy type FSM are determined by its ________
a) Input values
b) Output values
c) Both input values and current state
d) Current state
Answer: c
Explanation: The output values of a mealy type FSM are determined by its current state and present input values both. Output can change after a change at the inputs immediately, independent of the clock.
2. What kind of output does mealy machine produce?
a) Asynchronous
b) Synchronous
c) Level
d) Pulsed
Answer: a
Explanation: Output of the mealy type FSM is asynchronous it can change in response to any change in the input regardless of the clock. Moore type FSM gives a synchronous output.
3. States in FSM are represented by ________
a) Bits
b) Bytes
c) Word
d) Character
Answer: a
Explanation: Transition states in FSM are represented by bits. The number of bits that are required to represent all the states in FSM is equal to the number of flip-flops required to implement that state machine.
4. What is the first step in writing the VHDL for an FSM?
a) To define the VHDL entity
b) Naming the entity
c) Defining the data type
d) Creating the states
Answer: a
Explanation: The first step in writing the VHDL for an FSM is defining the VHDL entity. The VHDL entity defines the external interface of the system that is being designed, which includes the name of the entity, the inputs and the outputs.
5. A Mealy machine is safer to use.
a) True
b) False
Answer: b
Explanation: Moore machines are safer to use because output changes one cycle later at the clock edge while in mealy machines, input changes the output in the same clock cycle which becomes a problem if two machines are interconnected.
6. Which of the following react faster to inputs?
a) Sequencer
b) Generators
c) Mealy machines
d) Moore machines
Answer: c
Explanation: Mealy machines react faster to the inputs because they react in the same cycle, they don’t wait for the clock. Moore machines react one cycle later.
7. What is the first state of FSM?
a) Wait loop state
b) Initial state
c) Output state
d) Activate pulse state
Answer: b
Explanation: The first state of the finite state machine is the initial-standby state. It waits until a 1 is read at the input to get started. It then goes to activate pulse state and transmits a high pulse.
8. Mealy machines have _________ states than Moore machine.
a) Fewer
b) More
c) Equal
d) Negligible
Answer: a
Explanation: Mealy machines have fewer states than Moore machine because they respond faster to the input in one cycle only, as they don’t have to wait for the clock. Moore machines generally respond one clock cycle later.
9. Mealy type FSM has a memory element.
a) True
b) False
Answer: a
Explanation: Mealy type FSM has a memory element since it’s a sequential logic system. The past inputs are stored inside the FSM’s memory and represent its state at a given time. The memory elements are the flip-flops.
10. In mealy type FSM, the path is labelled by which of the following?
a) Inputs
b) Outputs
c) Both inputs and outputs
d) Current state
Answer: c
Explanation: In mealy machines, each transition path is labelled with both, the inputs and the outputs and the circle contains the code for the internal state. In Moore machines path is labelled only with the inputs and the circle contains the output and the state code.
This set of VHDL Multiple Choice Questions & Answers focuses on “Top Level System Design”.
1. The top-level system design is modelled for functionality and performance.
a) True
b) False
Answer: a
Explanation: In the top-level system design each major component in the design is formed at the gate level and the design is simulated again for the timing, functionality and performance.
2. Which modelling is used in the top-level system design?
a) Low-level behavioural modelling
b) High-level behavioural modelling
c) Structural modelling
d) Data flow modelling
Answer: b
Explanation: High-level behavioural modelling is used in the top-level system design. It is the highest level of abstraction in the VHDL. This level simulates the behavioural level of the circuits and the development rate at this level is highest.
3. What are the two constructs used in most of the behavioural modelling?
a) Assign
b) Begin and end
c) Initial and always
d) Always and end
Answer: c
Explanation: The two constructs used in most of the behavioural modelling are Initial and always. All the other behavioural statements appear only inside these two structured procedure constructs.
4. How many levels of abstraction are there in the top-level system design?
a) One
b) Two
c) Three
d) Four
Answer: c
Explanation: There are three levels of abstraction: algorithm, register transfer level , and gate level. Algorithms cannot be synthesized, RTL is the input to the synthesis, gate level is the output from the synthesis.
5. Timing performance of design is checked by which of the following simulation mode?
a) Gate-level
b) Behavioural
c) Transistor-level
d) Switch-level
Answer: a
Explanation: Gate-level simulation is used to check the timing performance of a design. It quickly does the implementation of the design and helps in verifying the dynamic behaviour of the circuit which is usually not verified correctly by the static methods.
6. The statements in the initial construct constitute ________
a) End block
b) Initial block
c) Begin block
d) Always block
Answer: b
Explanation: The statements in the initial construct constitute the initial block. Initial block is executed only once during the simulation process, at time 0. If there are more than one initial blocks, then all the initial blocks are executed simultaneously.
7. The statements in the always construct constitute ________
a) End block
b) Initial block
c) Begin block
d) Always block
Answer: d
Explanation: The statements in the always construct constitute the always block. The always block starts executing at time 0 and keeps on executing during the complete simulation process. It is like an infinite loop.
8. Register data types and memory data types are updated by procedural assignments.
a) True
b) False
Answer: a
Explanation: Procedural assignments update reg, integer, real, time, real-time, and memory data types. The values in procedural assignments change the procedural flow constructs. The variables hold their values until they’re updated by another procedural assignment.
9. How many types of procedural assignments are there?
a) One
b) Two
c) Three
d) Four
Answer: b
Explanation: There are two types of procedural assignments which are blocking and non-blocking assignments. Blocking assignment doesn’t block the execution of the next statement. The non-blocking assignment allows for assignment scheduling.
10. In which order do the blocking assignment statements are executed in a sequential block?
a) Random order
b) Specified order
c) Ascending order
d) Descending order
Answer: b
Explanation: Blocking assignment statements are executed in a SPECIFIED order in a sequential block. The next statement executes only after the present blocking assignments are completed. A blocking assignment doesn’t block the execution of an upcoming statement in a parallel block.
This set of VHDL Multiple Choice Questions & Answers focuses on “RTL Simulation”.
1. What does RTL in digital circuit design stand for?
a) Register transfer language
b) Register transfer logic
c) Register transfer level
d) Resistor-transistor logic
Answer: c
Explanation: RTL in digital circuit design stands for register transfer level, used in HDL. Register transfer language is a type of intermediate representation close to assembly language. Resistor-transistor logic is used in BJTs as switching devices. Register transfer logic is used in state machine designs.
2. RTL is a design abstraction of what kind of circuit?
a) Asynchronous digital circuit
b) Synchronous digital circuit
c) Asynchronous sequential circuit
d) Analog circuit
Answer: b
Explanation: RTL is a design abstraction that shapes a synchronous digital circuit with reference to digital signals that flow between hardware registers and the logical operations are carried out on those signals.
3. RTL is used in HDL to create what level of representations in the circuit?
a) High-level
b) Low-level
c) Mid-level
d) Same level
Answer: a
Explanation: RTL is used in HDL for creating HIGH-LEVEL of representations in the circuit, from which lower-level of representations can be derived. Designing at the RTL level is a representative practice in modern digital design.
4. RTL mainly focuses on describing the flow of signals between ________
a) Logic gates
b) Registers
c) Clock
d) Inverter
Answer: b
Explanation: RTL focuses on describing the flow of signals between registers. There is a regularly repeated path of logic from the output of the register to its input, that is the reason it is called register transfer level.
5. Which flip-flop is usually used in the implementation of the registers?
a) D flip-flop
b) S-R flip-flop
c) T flip-flop
d) J-K flip-flop
Answer: a
Explanation: Registers are generally implemented as D flip-flops because connection for the shift register is the simplest with D flip-flop, as there is a single data input in it. The flip-flop also stores the output of whatever logic is applied to its data input as long as the clock input is high.
6. Which of the following tool performs logic optimization?
a) Simulation tool
b) Synthesis tool
c) Routing tool
d) RTL compiler
Answer: b
Explanation: Synthesis tool performs logic optimization in RTL by converting high-level description of the design circuit into an optimized gate level representation by the use of basic logic gates like and, or, nor, etc.
7. RTL is a combination of both combinational and sequential circuits.
a) True
b) False
Answer: a
Explanation: RTL is a combination of both combinational and sequential circuits. Combinational logic performs all the logical operations in the circuit and it typically consists of basic logic gates and registers make synchronized sequential logic.
8. Setup time is the time required for input data to settle after the triggering edge of the clock.
a) True
b) False
Answer: b
Explanation: The time required for an input data to settle BEFORE the triggering edge of the clock is called the setup time. It is measured with respect to active clock pulse edge only.
9. Hold time is the time needed for the data to ________ after the edge of the clock is triggered.
a) Decrease
b) Increase
c) Remain constant
d) Negate
Answer: c
Explanation: Hold time is the time needed for the data to remain constant after the edge of the clock is triggered. Data must remain stable, if the incorrect data is latched then, it leads to hold violation.
10. Simulator enters in which phase after the initialization phase?
a) Execution phase
b) Compilation phase
c) Elaboration phase
d) Simulation phase
Answer: a
Explanation: Simulator enters in execution phase after the initialization phase, the actual simulation of the behaviour of the design takes place in the execution phase. Each simulation process in the active queue is taken out and executed until it suspends.
11. Conversion of RTL description to Boolean _______ description is a function of the translation procedure in the synthesis process.
a) Optimized
b) Unoptimized
c) Translation
d) PLA format
Answer: b
Explanation: Conversion of RTL description to Boolean unoptimized description is a function of translation procedure in the synthesis process. The logic synthesis tool converts the description to an unoptimized, intermediate, internal representation.
