VLSI Pune University MCQs
VLSI Pune University MCQs
This set of VLSI Multiple Choice Questions & Answers focuses on “Basic MOS Transistors-1”.
1. Electronics are characterized by ____________
a) low cost
b) low weight and volume
c) reliability
d) all of the mentioned
Answer: d
Explanation: Electronics are characterized by reliability, low power dissipation, extremely low weight and volume, low cost, can cope up with high degree of sophistication and complexity.
2. Speed power product is measured as the product of ____________
a) gate switching delay and gate power dissipation
b) gate switching delay and gate power absorption
c) gate switching delay and net gate power
d) gate power dissipation and absorption
Answer: a
Explanation: Speed power product is measure in picojoules and it is the product of gate switching delay and gate power dissipation.
3. nMOS devices are formed in ____________
a) p-type substrate of high doping level
b) n-type substrate of low doping level
c) p-type substrate of moderate doping level
d) n-type substrate of high doping level
Answer: c
Explanation: nMOS devices are formed in a p-type substrate of moderate doping level. nMOS devices have higher mobility and is cheaper.
4. Source and drain in nMOS device are isolated by ____________
a) a single diode
b) two diodes
c) three diodes
d) four diodes
Answer: b
Explanation: The source and drain regions are formed by diffusing n-type impurity, it gives rise to depletion region which extend in more lightly doped p-region. Thus Source and drain in an nMOS device are isolated by two diodes.
5. In depletion mode, source and drain are connected by ____________
a) insulating channel
b) conducting channel
c) Vdd
d) Vss
Answer: b
Explanation: In depletion mode, source and drain are connected by conducting channel but the channel can be closed by applying suitable negative voltage to the gate.
6. What is the condition for non saturated region?
a) Vds = Vgs – Vt
b) Vgs lesser than Vt
c) Vds lesser than Vgs – Vt
d) Vds greater than Vgs – Vt
Answer: c
Explanation: The condition for non saturated region is Vds lesser Vgs – Vt. In non saturation region, MOSFET acts as voltage source. Varying Vds will provide a significant change in drain current.
7. In enhancement mode, device is in _________ condition.
a) conducting
b) non conducting
c) partially conducting
d) insulating
Answer: b
Explanation: In enhancement mode, the device is in non conducting condition. For n-type FET, the threshold voltage is positive and p-type threshold voltage is negative.
8. What is the condition for non conducting mode?
a) Vds lesser than Vgs
b) Vgs lesser than Vds
c) Vgs = Vds = 0
d) Vgs = Vds = Vs = 0
Answer: d
Explanation: In enhancement mode the device is in non conducting mode, and its condition is Vds = Vgs = Vs = 0.
9. nMOS is ____________
a) donor doped
b) acceptor doped
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: nMOS transistors are acceptor doped. Acceptor is a dopant which when added forms p-type region. Some of the accpetors are silicon, boron, aluminium etc.
10. MOS transistor structure is ____________
a) symmetrical
b) non symmetrical
c) semi symmetrical
d) pseudo symmetrical
Answer: a
Explanation: MOS transistor structure is completely symmetrical with respect to source and drain.
11. pMOS is ____________
a) donor doped
b) acceptor doped
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: nMOS is acceptor doped and pMOS is donor doped devices. Acceptor doped forms p-type region and donor doped forms n-type region.
12. Inversion layer in enhancement mode consists of excess of ____________
a) positive carriers
b) negative carriers
c) both in equal quantity
d) neutral carriers
Answer: b
Explanation: Inversion layer in enhancement mode consists of excess of negative carriers that is electron.
13. What is the condition for linear region?
a) Vgs lesser than Vt
b) Vgs greater than Vt
c) Vds lesser than Vgs
d) Vds greater than Vgs
Answer: b
Explanation: The condition for linear region is Vgs > Vt. The power of MOS in the linear region is less. It is a power dissipating region.
14. As source drain voltage increases, channel depth ____________
a) increases
b) decreases
c) logarithmically increases
d) exponentially increases
Answer: b
Explanation: As source drain voltage Vds increases, the channel depth at the drain end decreases.
This set of VLSI Interview Questions and Answers focuses on “Basic MOS Transistors-2”.
1. MOS transistors consist of which of the following?
a) semiconductor layer
b) metal layer
c) layer of silicon-di-oxide
d) all of the mentioned
Answer: d
Explanation: MOS transistors is formed as a sandwich consisting of a semiconductor layer, a silicon-di-oxide layer and a metal layer.
2. In MOS transistors _______________ is used for their gate.
a) metal
b) silicon-di-oxide
c) polysilicon
d) gallium
Answer: c
Explanation: In MOS transistors, polycrystalline silicon is used for their gate region instead of metal. Polysilicon gates have replaced all other older devices.
3. The gate region consists of ____________
a) insulating layer
b) conducting layer
c) lower metal layer
d) p type layer
Answer: b
Explanation: The gate region is a sandwich consisting of semiconductor layer, an insulating layer and an upper metal layer.
4. Electrical charge flows from ____________
a) source to drain
b) drain to source
c) source to ground
d) source to gate
Answer: a
Explanation: Electrical charge or current flows from source to drain depending on the charge applied to the gate region.
5. Source in MOS transistors is doped with ______ material.
a) n-type
b) p-type
c) n & p type
d) none of the mentioned
Answer: a
Explanation: Source and drain in the MOS transistors are doped with N-type material and substrate is doped with p-type material.
6. In N channel MOSFET which is the more negative of the elements?
a) source
b) gate
c) drain
d) source and drain
Answer: a
Explanation: In N channel MOSFET, source is the more negative of the elements and in the case of P channel MOSFET, it is the more positive of the elements.
7. If the gate is given sufficiently large charge, electrons will be attracted to ____________
a) drain region
b) channel region
c) switch region
d) bulk region
Answer: b
Explanation: If the gate is given sufficiently large charge, the negative charge carreirs, electrons will be attracted from the bulk of the substrate material into the channel region below the oxide.
8. Enhancement mode device acts as ____ switch, depletion mode acts as _____ switch.
a) open, closed
b) closed, open
c) open, open
d) close, close
Answer: a
Explanation: Enhancement mode transistor acts as open switch whereas depletion mode transistor acts as normally closed switch.
9. Depletion mode MOSFETs are more commonly used as ____________
a) switches
b) resistors
c) buffers
d) capacitors
Answer: b
Explanation: Depletion mode MOSFETs are more commonly used as resistors than as switches. As permanently on switch it has high resistance.
10. Enhancement mode MOSFETs are more commonly used as ____________
a) switches
b) resistors
c) buffers
d) capacitors
Answer: a
Explanation: Enhancement mode MOSFETs are more commonly used as switches and depletion mode devices are more used as resistors.
11. Depletion mode transistor should be large.
a) true
b) false
Answer: a
Explanation: Depletion mode transistors should be made large that is long and thin to create the large ‘on’ resistance.
12. Which expression is true?
a) charging time < discharging time
b) charging time > discharging time
c) charging time = discharging time
d) charging time and discharging time are not related
Answer: b
Explanation: When driving a capacitive output load, charging time will be long compared to the discharging time.
13. Overheating in device occurs due to less number of resistors per unit area.
a) true
b) false
Answer: b
Explanation: When the number of resistors per unit area increases, the device may not dissipate heat very well. This results in device overheating which leads to its failure.
14. In n channel MOSFET ______________ is constant.
a) channel length
b) channel width
c) channel depth
d) channel concentration
Answer: a
Explanation: In all n channel MOSFET transistors, channel length is constant where as channel width can be varied.
This set of VLSI Multiple Choice Questions & Answers focuses on “VLSI Design”.
1. VLSI technology uses ________ to form integrated circuit.
a) transistors
b) switches
c) diodes
d) buffers
Answer: a
Explanation: Very large scale integration is the process of creating an integrated circuit with thousands of transistors into one single chip.
2. Medium scale integration has ____________
a) ten logic gates
b) fifty logic gates
c) hundred logic gates
d) thousands logic gates
Answer: c
Explanation: Small scale integration has one or more logic gate. Further improved technology is medium scale integration which consists of hundred logic gates. Large scale integration has thousand logic gates.
3. The difficulty in achieving high doping concentration leads to ____________
a) error in concentration
b) error in variation
c) error in doping
d) distribution error
Answer: b
Explanation: As photolithography comes closer to the fundamental law of optics, achieving high accuracy in doping concentration becomes difficult, which leads to error due to variation.
4. _________ is used to deal with effect of variation.
a) chip level technique
b) logic level technique
c) switch level technique
d) system level technique
Answer: d
Explanation: Designers must simulate multiple fabrication process or use system level technique for dealing with effects of variation.
5. As die size shrinks, the complexity of making the photomasks ____________
a) increases
b) decreases
c) remains the same
d) cannot be determined
Answer: a
Explanation: As the die size shrinks due to scaling, the number of die per wafer increases and the complexity of making the photomasks increases rapidly.
6. ______ architecture is used to design VLSI.
a) system on a device
b) single open circuit
c) system on a chip
d) system on a circuit
Answer: c
Explanation: SoC that is system on a chip architecture is used to design the very high level integrated circuit.
7. What is the design flow of VLSI system?
i. architecture design
ii. market requirement
iii. logic design
iv. HDL coding
a) ii-i-iii-iv
b) iv-i-iii-ii
c) iii-ii-i-iv
d) i-ii-iii-iv
Answer: a
Explanation: The order of the design flow of VLSI circuit is market requirement, architecture design, logic design, HDL coding and then verification.
8. ______ is used in logic design of VLSI.
a) LIFO
b) FIFO
c) FILO
d) LILO
Answer: b
Explanation: First in first out technique and finite state machine technique is used in the logic design of the VLSI circuits.
9. Which provides higher integration density?
a) switch transistor logic
b) transistor buffer logic
c) transistor transistor logic
d) circuit level logic
Answer: c
Explanation: Transistor-transistor logic offers higher integration density and it became the first integrated circuit revolution.
10. Physical and electrical specification is given in ____________
a) architectural design
b) logic design
c) system design
d) functional design
Answer: d
Explanation: Functional design defines the major functional units of the system, interconnections, physical and electrical specifications.
11. Which is the high level representation of VLSI design?
a) problem statement
b) logic design
c) HDL program
d) functional design
Answer: a
Explanation: Problem statement is a high level representation of the system. Performance, functionality and physical dimensions are considered here.
12. Gate minimization technique is used to simplify the logic.
a) true
b) false
Answer: a
Explanation: Gate minimization technique is used to find the simplest, smallest and effective implementation of the logic.
This set of VLSI Multiple Choice Questions & Answers focuses on “nMOS Fabrication”.
1. nMOS fabrication process is carried out in ____________
a) thin wafer of a single crystal
b) thin wafer of multiple crystals
c) thick wafer of a single crystal
d) thick wafer of multiple crystals
Answer: a
Explanation: nMOS fabrication process is carried out in thin wafer of a single crystal with high purity.
2. ______________ impurities are added to the wafer of the crystal.
a) n impurities
b) p impurities
c) siicon
d) crystal
Answer: b
Explanation: p impurities are introduced as the crystal is grown. This increases the hole concentration in the device.
3. What kind of substrate is provided above the barrier to dopants?
a) insulating
b) conducting
c) silicon
d) semiconducting
Answer: a
Explanation: Above a layer of silicon dioxide which acts as a barrier, an insulating layer is provided upon which other layers may be deposited and patterned.
4. The photoresist layer is exposed to ____________
a) Visible light
b) Ultraviolet light
c) Infra red light
d) LED
Answer: b
Explanation: The photoresist layer is exposed to ultraviolet light to mark the regions where diffusion is to take place.
5. In nMOS device, gate material could be ____________
a) silicon
b) polysilicon
c) boron
d) phosphorus
Answer: b
Explanation: In nMOS device, the gate material could be metal or polysilicon. This polysilicon layer has heavily doped polysilicon deposited by CVD.
6. Which is the commonly used bulk substrate in nMOS fabrication?
a) silicon crystal
b) silicon-on-sapphire
c) phosphorus
d) silicon-di-oxide
Answer: c
Explanation: In nMOS fabrication, the bulk substrate used can be either bulk silicon or silicon-on-sapphire.
7. In nMOS fabrication, etching is done using ____________
a) plasma
b) hydrochloric acid
c) sulphuric acid
d) sodium chloride
Answer: a
Explanation: In nMOS fabrication, etching is done using hydrofluoric acid or plasma. Etching is a process used to remove layers from the surface.
8. Heavily doped polysilicon is deposited using ____________
a) chemical vapour decomposition
b) chemical vapour deposition
c) chemical deposition
d) dry deposition
Answer: b
Explanation: The polysilicon layer consists of heavily doped polysilicon deposited by chemical vapour deposition.
9. In diffusion process ______ impurity is desired.
a) n type
b) p type
c) np type
d) none of the mentioned
Answer: a
Explanation: Diffusion is carried out by heating the wafer to high temperature and passing a gas containing the desired ntype impurity.
10. Contact cuts are made in ____________
a) source
b) drain
c) metal layer
d) diffusion layer
Answer: a
Explanation: Contact cuts are made in the desired polysilicon area, source and gate. COntact cuts are those places where connection has to be made.
11. Interconnection pattern is made on ____________
a) polysilicon layer
b) silicon-di-oxide layer
c) metal layer
d) diffusion layer
Answer: c
Explanation: The metal layer is masked and etched to form interconnection pattern. The metal layer was formed using aluminium deposited over the formed surface.
12. SIlicon-di-oxide is a good insulator.
a) true
b) false
Answer: a
Explanation: SIlicon-di-oxide is a very good insulator so a very thin layer is required in the fabrication of MOS transistor.
13. _______ is used to suppress unwanted conduction.
a) phosphorus
b) boron
c) silicon
d) oxygen
Answer: b
Explanation: Boron is used to suppress the unwanted conduction between transistor sites. It is implanted in the exposed regions.
14. Which is used for the interconnection?
a) boron
b) oxygen
c) aluminium
d) silicon
Answer: c
Explanation: Aluminium is the suitable material used for the circuit interconnection or connecting two layers.
This set of VLSI Multiple Choice Questions & Answers focuses on “CMOS Fabrication”.
1. CMOS technology is used in developing which of the following?
a) microprocessors
b) microcontrollers
c) digital logic circuits
d) all of the mentioned
Answer: d
Explanation: CMOS technology is used in developing microcontrollers, microprocessors, digital logic circuits and other integrated circuits.
2. CMOS has __________
a) high noise margin
b) high packing density
c) high power dissipation
d) high complexity
Answer: b
Explanation: Some of the properties of CMOS are that it has low power dissipation, high packing density and low noise margin.
3. In CMOS fabrication, nMOS and pMOS are integrated in same substrate.
a) true
b) false
Answer: a
Explanation: In CMOS fabrication, nMOS and pMOS are integrated in the same chip substrate. n-type and p-type devices are formed in the same structure.
4. P-well is created on __________
a) p substrate
b) n substrate
c) p & n substrate
d) none of the mentioned
Answer: b
Explanation: P-well is created on n substrate to accommodate n-type devices whereas p-type devices are formed in the ntype substrate.
5. Oxidation process is carried out using __________
a) hydrogen
b) low purity oxygen
c) sulphur
d) nitrogen
Answer: a
Explanation: Oxidation process is carried out using high purity oxygen and hydrogen. Oxidation is a process of oxidizing or being oxidised.
6. Photoresist layer is formed using __________
a) high sensitive polymer
b) light sensitive polymer
c) polysilicon
d) silicon di oxide
Answer: b
Explanation: Light sensitive polymer is used to form the photoresist layer. Photoresist is a light sensitive material used to form patterned coating on a surface.
7. In CMOS fabrication, the photoresist layer is exposed to __________
a) visible light
b) ultraviolet light
c) infra red light
d) fluorescent
Answer: b
Explanation: The photoresist layer is exposed to ultraviolet light to mark the regions where diffusion is to take place.
8. Few parts of photoresist layer is removed by using __________
a) acidic solution
b) neutral solution
c) pure water
d) diluted water
Answer: a
Explanation: Few parts of photoresist layer is removed by treating the wafer with basic or acidic solution. Acidic solutions are those which have pH less than 7 and basic solutions have greater than 7.
9. P-well doping concentration and depth will affect the __________
a) threshold voltage
b) Vss
c) Vdd
d) Vgs
Answer: a
Explanation: Diffusion should be carried out very carefully, as doping concentration and depth will affect both threshold voltage and breakdown voltage.
10. Which type of CMOS circuits are good and better?
a) p well
b) n well
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: N-well CMOS circuits are better than p-well CMOS circuits because of lower substrate bias effect.
11. N-well is formed by __________
a) decomposition
b) diffusion
c) dispersion
d) filtering
Answer: b
Explanation: N-well is formed by using ion implantation or diffusion. Ion implantation is a process by which ions of a material are accelerated in an electrical field and impacted into a solid. Diffusion is a process in which net movement of ions or molecules plays a major role.
12. _______ is sputtered on the whole wafer.
a) silicon
b) calcium
c) potassium
d) aluminium
Answer: d
Explanation: Aluminium is sputtered on the whole wafer before removing the excess metal from the wafer.
This set of VLSI Multiple Choice Questions & Answers focuses on “BiCMOS Technology”.
1. MOS technology has more load driving capability.
a) true
b) false
Answer: b
Explanation: One of the disadvantages of MOS technology is it has limited load driving capabilities.
2. What is the disadvantage of the MOS device?
a) limited current sourcing
b) limited voltage sinking
c) limited voltage sourcing
d) unlimited current sinking
Answer: a
Explanation: MOS devices have limited current sourcing and current sinking abilities.
3. What are the advantages of BiCMOS?
a) higher gain
b) high frequency characteristics
c) better noise characteristics
d) all of the mentioned
Answer: d
Explanation: BiCMOS provides higher gain, better noise and high frequency characteristics than MOS transistors.
4. What are the features of BiCMOS?
a) low input impedance
b) high packing density
c) high input impedance
d) bidirectional
Answer: a
Explanation: Some of the features of BiCMOS are low input impedance, low packing density, unidirectional, high output drive current, etc.
5. BiCMOS has low power dissipation.
a) true
b) false
Answer: b
Explanation: BiCMOS has high power dissipation and CMOS has low power dissipation.
6. CMOS is __________
a) unidirectional
b) bidirectional
c) directional
d) none of the mentioned
Answer: a
Explanation: BiCMOS is unidirectional and CMOS is bidirectional.
7. In bipolar transistor, its quality can be improved by __________
a) increasing collector resistance
b) decreasing collector resistance
c) collector resistance does not affect the quality
d) decreasing gate resistance
Answer: b
Explanation: The quality of bipolar transistor can be improved by reducing the collector resistance, which can be done by using the additional layer of n+ subcollector.
8. BiCMOS can be used in __________
a) amplifyig circuit
b) driver circuits
c) divider circuit
d) multiplier circuit
Answer: b
Explanation: BiCMOS is more advantageous and improved than CMOS and it can be used in I/O and driver circuits.
9. What are the advantages of E-beam masks?
a) small feature size
b) larger feature size
c) looser layer
d) complex design
Answer: a
Explanation: The advantages of E-beam masks are it has tighter layer to layer registration and it has smaller feature sizes.
10. Which process is used in E-beam machines?
a) raster scanning
b) vector scanning
c) raster & vector scanning
d) none of the mentioned
Answer: c
Explanation: The two approaches to the design of E-beam machines are raster scanning and vector scanning.
11. What is the feature of vector scanning?
a) faster
b) slow
c) easy handling
d) very simple design
Answer: a
Explanation: Vector scanning is faster but data handling involved is more complex. Vector scanning is done between the end points.
12. Which has high input resistance?
a) nMOS
b) CMOS
c) pMOS
d) BiCMOS
Answer: b
Explanation: CMOS technology has high input resistance and is best for constructing simple low-power logic gates.
13. BiCMOS has lower standby leakage current.
a) true
b) false
Answer: b
Explanation: BiCMOS has the potential for high standby leakage current and has high power consumption compared to CMOS.
This set of VLSI Multiple Choice Questions & Answers focuses on “nMOS and CMOS Fabrication”.
1. What is Lithography?
a) Process used to transfer a pattern to a layer on the chip
b) Process used to develop an oxidation layer on the chip
c) Process used to develop a metal layer on the chip
d) Process used to produce the chip
Answer: a
Explanation: Lithography is the process used to develop a pattern to a layer on the chip.
2. Silicon oxide is patterned on a substrate using ____________
a) Physical lithography
b) Photolithography
c) Chemical lithography
d) Mechanical lithography
Answer: b
Explanation: Silicon oxide is patterned on a substrate using Photolithography.
3. Positive photo resists are used more than negative photo resists because ___________
a) Negative photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the positive photo resists
b) Positive photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the negative photo resists
c) Negative photo resists are less sensitive to light
d) Positive photo resists are less sensitive to light
Answer: a
Explanation: Negative photo resists are more sensitive to light, but their photo lithographic resolution is not as high as that of the positive photo resists. Therefore, negative photo resists are-used less commonly in the manufacturing of high-density integrated circuits.
4. The ______ is used to reduce the resistivity of poly silicon.
a) Photo resist
b) Etching
c) Doping impurities
d) None of the mentioned
Answer: c
Explanation: The resistivity of poly silicon is reduced by Doping impurities.
5. The isolated active areas are created by technique known as ___________
a) Etched field-oxide isolation
b) Local Oxidation of Silicon
c) Etched field-oxide isolation or Local Oxidation of Silicon
d) None of the mentioned
Answer: c
Explanation: To create isolated active areas both the techniques can be used. Among them Local Oxidation of Silicon is most efficient.
6. The chemical used for shielding the active areas to achieve selective oxide growth is?
a) Silver Nitride
b) Silicon Nitride
c) Hydrofluoric acid
d) Polysilicon
Answer: b
Explanation: Selective oxide growth is achieved by shielding the active areas. Silicon nitride (Si 3 N 4 ) is used for shielding the active areas during oxidation, which effectively inhibits oxide growth.
7. The dopants are introduced in the active areas of silicon by using which process?
a) Diffusion process
b) Ion Implantation process
c) Chemical Vapour Deposition
d) Either Diffusion or Ion Implantation Process
Answer: d
Explanation: Two ways to add dopants are diffusion and ion implantation.
8. To grow the polysilicon gate layer, which of the following chemical is used for chemical vapour deposition?
a) Silicon Nitride(Si 3 N 4 )
b) Silane gas(SiH 4 )
c) Silicon oxide
d) None of the mentioned
Answer: b
Explanation: Silicon Wafer is placed in a reactor with silane gas (SiH 4 ), and they are heated again to grow the polysilicon layer by chemical vapor deposition.
9. The process by which Aluminium is grown over the entire wafer, also filling the contact cuts is?
a) Sputtering
b) Chemical vapour deposition
c) Epitaxial growth
d) Ion Implantation
Answer: a
Explanation: Aluminum is sputtered over the entire wafer, it also fills the contact cuts.
10. Which process is involved in growing the shaded region?
vlsi-questions-answers-nmos-cmos-fabrication-q10
a) Chemical vapor deposition
b) Sputtering and patterned by etching
c) Chemical vapor deposition and patterned by HF acid etching
d) Chemical vapor deposition and patterned by dry etching
Answer: d
Explanation: The poly silicon layer is produced using chemical vapor deposition and it is patterned by dry etching.
11. Chemical Mechanical Polishing is used to ___________
a) Remove silicon oxide
b) Remove silicon nitride and pad oxide
c) Remove polysilicon gate layer
d) Reduce the size of the layout
Answer: b
Explanation: The pad oxide and nitride are removed using a Chemical Mechanical Polishing step.
12. Gate oxide layer consists of ___________
vlsi-questions-answers-nmos-cmos-fabrication-q12
a) SiO 2 layer, overlaid with a few layers of an oxynitrided oxide
b) Only SiO 2 Layer
c) SiO 2 layer with Polysilicon Layer
d) SiO 2 layer and stack of epitaxial layers of Polysilicon
Answer: a
Explanation: Current processes seldom use a pure SiO 2 gate oxide, but prefer to produce a stack that consists of a few atomic layers, each 3–4 Ă… thick, of SiO 2 for reliability, overlaid with a few layers of oxy-nitrided oxide .
13. What is Piranha Solution?
a) It is a 3:1 to 5:1 mix of nitric acid and hydrogen peroxide that is used to develop the oxide layer on silicon substrate
b) It is a 3:1 to 5:1 mix of sulphuric acid and hydrofluoric acid that is used to clean silicon wafers removing organic and metal contaminants or photo resist after metal patterning
c) It is a 3:1 to 5:1 mix of sulphuric acid and hydrogen peroxide that is used to grow the oxide layer on the silicon
d) It is a 3:1 to 5:1 mix of sulphuric acid and hydrogen peroxide that is used to clean wafers of organic and metal contaminants or photo resist after metal patterning
Answer: d
Explanation: Piranha solution is a 3:1 to 5:1 mix of sulfuric acid and hydrogen peroxide that is used to clean silicon wafers of metal and organic contaminants or photo-resist after metal patterning.
This set of VLSI Multiple Choice Questions & Answers focuses on “Ids versus Vds Relationships”.
1. Ids depends on ___________
a) Vg
b) Vds
c) Vdd
d) Vss
Answer: b
Explanation: Ids depends on both Vgs and Vds. The charge induced is dependent on the gate to source voltage Vgs also charge can be moved from source to drain under influence of electric field created by Vds.
2. Ids can be given by __________
a) Qc x Ć®
b) Qc / Ć®
c) Ć® / Qc
d) Qc / 2Ć®
Answer: b
Explanation: Ids can be given as charge induced in the channel divided by transit time Ć®. Ids is equivalent to .
3. Transit time can be given by __________
a) L / v
b) v / L
c) v x L
d) v x d
Answer: a
Explanation: Transit time Ć® can be given by lenght of channel by velocity. Transit time is the time required for an electron to travel between two electrodes.
4. Velocity can be given as __________
a) µ / Vds
b) µ / Eds
c) µ x Eds
d) Eds / µ
Answer: b
Explanation: Velocity can be given as the product of electron or hole mobilityµ and electric field. It gives the flow velocity which an electron attains due to electric field.
5. Eds is given by __________
a) Vds / L
b) L / Vds
c) Vds x L
d) Vdd / L
Answer: a
Explanation: Electric field can be given as the ratio of Vds and L. Eds is the electric field created from drain to source due to volta Vds.
6. What is the mobility of proton or hole at room temperature?
a) 650 cm 2 /V sec
b) 260 cm 2 /V sec
c) 240 cm 2 /V sec
d) 500 cm 2 /V sec
Answer: c
Explanation: The value of mobility of proton or hole at room temperature is 240 cm 2 /V sec. This gives the measure of how fast an electron can move.
7. In resistive region __________
a) Vds greater than
b) Vds lesser than
c) Vgs greater than
d) Vgs lesser than
Answer: b
Explanation: In non saturated or resistive region, Vds lesser than Vgs – Vt where Vds is the voltage between drain and source, Vgs is the gate-source voltage and Vt is the threshold voltage.
8. What is the condition for saturation?
a) Vgs = Vds
b) Vds = Vgs – Vt
c) Vgs = Vds – Vt
d) Vds > Vgs – Vt
Answer: b
Explanation: The condition for saturation is Vds = Vgs – Vt since at this point IR drop in the channel equals the effective gate to channel voltage at the drain.
9. Threshold voltage is negative for __________
a) nMOS depletion
b) nMOS enhancement
c) pMOS depletion
d) pMOS enhancement
Answer: a
Explanation: The threshold voltage for nMOS depletion denoted as Vtd is negative.
10. The current Ids _______ as Vds increases.
a) increases
b) decreases
c) remains fairly constant
d) exponentially increases
Answer: c
Explanation: The current Ids remains fairly constant as Vds increases in the saturation region.
11. In linear region ______ channel exists.
a) uniform
b) non-uniform
c) wide
d) uniform and wide
Answer: a
Explanation: In linear region of MOSFET, the channel is uniform and narrow. This is the concentration distribution.
12. When the channel pinches off?
a) Vgs > Vds
b) Vds > Vgs
c) Vds >
d) Vgs >
Answer: c
Explanation: In MOSFET, in saturation region, when Vds > , the channel pinches off that is the channel current at the drain spreads out.
13. When the threshold voltage is more, leakage current will be?
a) more
b) less
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: Increasing the threshold voltage, leads to small leakage current when turned off and reduces current flow when turned on.
14. MOSFET is used as ___________
a) current source
b) voltage source
c) buffer
d) divider
Answer: a
Explanation: MOSFET is used as current source. Bipolar junction transistor also acts as good current source.
This set of VLSI Multiple Choice Questions & Answers focuses on “Parameters of MOS Transistors”.
1. The work function difference is negative for ____________
a) silicon substrate
b) polysilicon gate
c) silicon substrate & polysilicon gate
d) none of the mentioned
Answer: c
Explanation: The work function difference between gate and Si is negative for silicon substrate and polysilicon gate.
2. Substrate bias voltage is positive for nMOS.
a) true
b) false
Answer: b
Explanation: Substrate bias voltage Vsb is positive for pMOS and negative for nMOS.
3. According to body effect, substrate is biased with respect to ___________
a) source
b) drain
c) gate
d) Vss
Answer: a
Explanation: According to body effect, the substrate is biased with respect to the source. Body effect can be seen as a change in the threshold voltage.
4. Increasing Vsb _______ the threshold voltage.
a) does not effect
b) decreases
c) increases
d) exponentially increases
Answer: c
Explanation: Increasing the substrate bias voltage Vsb, increases the threshold voltage because it depletes the channel of charge carriers.
5. Transconductance gives the relationship between ___________
a) input current and output voltage
b) output current and input voltage
c) input current and input voltage
d) output current and output voltage
Answer: b
Explanation: Transconductance expresses the relationship between output current Ids and input voltage Vgs.
6. Transconductance can be increased by ___________
a) decreasing the width
b) increasing the width
c) increasing the length
d) decreasing the length
Answer: b
Explanation: Transconductance gm of a MOS device can be increased by increasing its width and it does not depend on length.
7. Increasing the transconductance ___________
a) increases input capacitance
b) decreasing area occupied
c) decreasing input capacitance
d) decrease in output capacitance
Answer: a
Explanation: Increasing the transconductance gm results in an increase in input capacitance and area occupied as it is directly proportional.
8. Ids is _______ to length L of the channel.
a) directly proportional
b) inversely proportional
c) not related
d) logarithmically related
Answer: b
Explanation: Ids is inversely proportional to the length L of the channel and using this relationship strong dependence of output conductance on channel length can be demonstrated.
9. Switching speed of a MOS device depends on ___________
a) gate voltage above a threshold
b) carrier mobility
c) length channel
d) all of the mentioned
Answer: d
Explanation: Switching speed of a MOS device depends on gate voltage above a threshold and on carrier mobility and inversely as the square of channel length.
10. A fast circuit requires ___________
a) high gm
b) low gm
c) does not depend on gm
d) low cost
Answer: a
Explanation: A fast circuit requires gm as high as possible as the switching speed depends on gate voltage above threshold and on carrier mobility and inversely to square of channel length.
11. Surface mobility depends on ___________
a) effective drain voltage
b) effective gate voltage
c) channel length
d) effective source voltage
Answer: b
Explanation: Surface mobility is dependent on the effective gate voltage . Electron mobility on oriented n-type inversion layer surface is larger than that on an oriented surface.
12. What is a MOS transistor?
a) minority carrier device
b) majority carrier device
c) majority & minority carrier device
d) none of the mentioned
Answer: b
Explanation: MOS transistor is a majority carrier device, in which current in a conducting channel between the source and drain is modulated by a voltage.
13. The MOS transistor is non conducting when?
a) zero source bias
b) zero threshold voltage
c) zero gate bias
d) zero drain bias
Answer: c
Explanation: The MOS transistor normally is at cut-off or becomes non-conducting with zero gate bias .
This set of VLSI Multiple Choice Questions & Answers focuses on “nMOS Inverter”.
1. Inverters are essential for ________
a) NAND gates
b) NOR gates
c) sequential circuits
d) all of the mentioned
Answer: d
Explanation: Inverters are needed for restoring logic levels for NAND and NOR gates, sequential and memory circuits.
2. In basic inverter circuit _____________ is connected to ground.
a) source
b) gates
c) drain
d) resistance
Answer: a
Explanation: A basic inverter circuit consists of transistor with a source connected to ground and a load resistor connected from drain to positive supply rail Vdd.
3. In inverter circuit ________ transistors is used as load
a) enhancement mode
b) depletion mode
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: Depletion mode transistors are preferred to be used as load in inverter circuits as it occupies a lesser area and are produced on silicon substrate unlike resistors.
4. For depletion mode transistor, gate should be connected to ________
a) source
b) drain
c) ground
d) positive voltage rail
Answer: a
Explanation: For the depletion mode transistor, gate is connected to source so it is always on and only the characteristic curve Vgs=0 is relevant.
5. In nMOS inverter configuration depletion mode device is called as ________
a) pull up
b) pull down
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: In nMOS inverter configuration, depletion mode devices are called as pull up and enhancement mode devices are called as pull down transistor.
6. How is nMOS inverter represented?
a) vlsi-questions-answers-nmos-inverter-q6a
b) vlsi-questions-answers-nmos-inverter-q6b
c) vlsi-questions-answers-nmos-inverter-q6c
d) vlsi-questions-answers-nmos-inverter-q6d
Answer: b
Explanation: nMOS inverter can be represented using two transistors, depletion mode pMOS transistor followed by nMOS transistor. Input is given to the nMOS.
7. What is the ratio of Zp.u/Zp.d?
a) 1/4
b) 4/1
c) 1/2
d) 2/1
Answer: b
Explanation: The ratio of Zp.u/Zp.d, where Z is determined by the length to width ratio of the transistor, is given by 4/1.
8. Pass transistors are transistors used as ________
a) switches connected in series
b) switches connected in parallel
c) inverters used in series
d) inverter used in parallel
Answer: a
Explanation: Pass transistors are transistor used as switches in series with lines carrying logic levels due to its isolated nature of the gate.
9. An inverter driven through one or more pass transistors has Zp.u/Zp.d ratio of ________
a) 1/4
b) 4/1
c) 1/8
d) 8/1
Answer: d
Explanation: An inverter driven directly from output of another has the ratio of 4/1 and if driven through one or more pass transistors has the ratio of 8/1.
10. In depletion mode pull-up, dissipation is high since current flows when?
a) Vin = 1
b) Vin = 0
c) Vout = 1
d) Vout = 0
Answer: a
Explanation: In nMOS depletion mode pull-up, dissipation is high since current flows Vin = logical 1.
11. In complementary transistor pull-up, current flows when?
a) Vin = 1
b) Vin = 0
c) current doesn’t flow
d) Vout = Vin
Answer: c
Explanation: In complementary transistor pull-up no current flows either for logical 1 or 0, full logical 1 and 0 levels are presented at the output.
This set of VLSI Multiple Choice Questions & Answers focuses on “CMOS Inverter”.
1. CMOS inverter has ______ regions of operation.
a) three
b) four
c) two
d) five
Answer: d
Explanation: CMOS inverter has five distinct regions of operation which can be determined by plotting CMOS inverter current versus Vin.
2. If n-transistor conducts and has large voltage between source and drain, then it is said to be in _____ region.
a) linear
b) saturation
c) non saturation
d) cut-off
Answer: b
Explanation: If n-transistor conducts and has large voltage between source and drain, then it is in saturation.
3. If p-transistor is conducting and has small voltage between source and drain, then it is said to work in ________
a) linear region
b) saturation region
c) non saturation resistive region
d) cut-off region
Answer: c
Explanation: If p-transistor is conducting and has small voltage between source and drain, then it is said to be in unsaturated resistive region.
4. In the region where inverter exhibits gain, the two transistors are in _______ region.
a) linear
b) cut-off
c) non saturation
d) saturation
Answer: d
Explanation: In the region where the inverter exhibits gain, the two transistors n and p operates in saturation region.
5. If both the transistors are in saturation, then they act as ________
a) current source
b) voltage source
c) divider
d) buffer
Answer: a
Explanation: When both the transistors are in saturation, then act as current sources so that the equivalent circuit is two current sources between Vdd and Vss.
6. If βn = βp, then Vin is equal to ________
a) Vdd
b) Vss
c) 2Vdd
d) 0.5Vdd
Answer: d
Explanation: If βn = βp, then Vin = 0.5Vdd which implies that the changeover between logic levels is symmetrically disposed about the point.
7. Mobility depends on ________
a) Transverse electric field
b) Vg
c) Vdd
d) Channel length
Answer: a
Explanation: Mobility is affected by the transverse electric field and thus also depends on Vgs and the mobility of p-device and n-device are inherently unequal.
8. In CMOS inverter, transistor is a switch having ________
a) infinite on resistance
b) finite off resistance
c) buffer
d) infinite off resistance
Answer: b
Explanation: In CMOS inverter, transistor is a switch having finite on resistance and infinite off resistance.
9. CMOS inverter has ______ output impedance.
a) low
b) high
c) very high
d) none of the mentioned
Answer: a
Explanation: CMOS inverter has low output impedance and this makes it less prone to noise and disturbance.
10. What is the input resistance of CMOS inverter?
a) high
b) low
c) very low
d) none of the mentioned
Answer: a
Explanation: Input resistance of CMOS inverter is extremely high as it is a perfect insulator and draws no dc input source.
11. Increasing fan-out ____________ the propagation delay.
a) increases
b) decreases
c) does not affect
d) exponentially decreases
Answer: a
Explanation: In CMOS inverter, increasing the fan-out also increases the propagation delay. Fan-out is a term that defines the maximum number of digital inputs that the output of a single logic gate can feed.
12. Fast gate can be built by keeping ________
a) low output capacitance
b) high on resistance
c) high output capacitance
d) input capacitance does not affect speed of the gate
Answer: a
Explanation: Fast gate can be built by keeping the output capacitance small and by decreasing the on resistance of the transistor.
This set of VLSI Multiple Choice Questions & Answers focuses on “Characteristics of npn Bipolar Transistors”.
1. The transconductance of a bipolar is given by ______________
a) /Ic
b) Ic/
c) /Ic
d) Ic/
Answer: b
Explanation: Transconductance gm of a bipolar transistor is given by gm = Ic/. Transconductance is the electrical characteristic relating the current through the output of a device to the voltage across the input of a device.
2. Transconductance depends on the process.
a) true
b) false
Answer: b
Explanation: Transconductance gm is independent of process.
3. gm is ______ on input voltage Vbe.
a) inversely proportional
b) proportional
c) exponentially dependent
d) is not dependent
Answer: c
Explanation: Transconductance gm is exponentially dependent on input voltage Vbe .
4. gm is _______ to Ic.
a) directly proportional
b) inversely proportional
c) not dependent
d) exponentially proportional
Answer: a
Explanation: Transconductance gm is directly proportional to Ic, collector current.
5. Transconductance is a __________
a) weak function
b) strong function
c) weak and strong function
d) none of the mentioned
Answer: a
Explanation: Transconductance gm is a weak function of transistor size.
6. gm of bipolar is less than gm of MOS.
a) true
b) false
Answer: b
Explanation: Transconductance gm of bipolar is greater than gm of MOS if inputs are controlled by equal amounts of charge.
7. Which of the following is true when inputs are controlled by equal amounts of charge?
a) Cg = Cbase
b) Cg greater than Cbase
c) Cg lesser than Cbase
d) Cs lesser than Cbase
Answer: a
Explanation: Cg = Cbase when inputs are controlled by equal amounts of charge, and then gm >> gm.
8. Which has better I/A?
a) CMOS
b) bipolar
c) nMOS
d) pMOS
Answer: b
Explanation: Current/Area of bipolar is five times better than CMOS and this can be calculated using base resistance and base transit time.
9. Bipolar transistor exhibits _______ delay.
a) turn on
b) turn off
c) storage
d) all of the mentioned
Answer: d
Explanation: Bipolar transistors exhibits turn-on, turn-off, storage delays.
10. In bipolar transistor, which is heavily doped?
a) base region
b) emitter region
c) collector region
d) base and emitter
Answer: b
Explanation: In bipolar transistor, emitter region is heavily doped and the base region is lightly doped.
11. Bipolar transistor is a symmetrical device.
a) true
b) false
Answer: b
Explanation: Bipolar transistor is not symmetrical like other transistors.
This set of VLSI Multiple Choice Questions & Answers focuses on “BiCMOS Inverters”.
1. In BiCMOS, bipolar transistors are used to ___________
a) drive input loads
b) drive output loads
c) to perform logic functions
d) to amplify the input voltage
Answer: b
Explanation: In BiCMOS, bipolar transistors are used to drive output loads. Bipolar transistor can also be used as amplifier, switch or as an oscillator.
2. In BiCMOS, MOS switches are used to __________
a) drive input loads
b) drive output loads
c) to perform logic functions
d) to amplify the input voltage
Answer: c
Explanation: In BiCMOS circuits, MOS switches are used to perform logic functions. The ability to turn the power MOS “ON” and “OFF” allows the device to be used as a very efficient switch with switching speeds much faster than standard bipolar junction transistors.
3. The nMOS and pMOS transistors used in BiCMOS is ____________
a) depletion mode
b) enhancement mode
c) only pMOS
d) only nMOS
Answer: b
Explanation: The nMOS and pMOS transistors used in BiCMOS device operates in enhancement mode. Enhancement mode devices are mostly common switching elements in MOS.
4. The inverter has __________
a) low input impedance
b) high input impedance
c) high output impedance
d) high input and output impedance
Answer: a
Explanation: The inverter has low input impedance. The basic inverter circuit requires a transistor with source connected to ground and a load resistor connected from the drain to positive supply Vdd.
5. The inverter has __________
a) low output impedance
b) low input impedance
c) low power dissipation
d) high input and output impedance
Answer: a
Explanation: The inverter has low output impedance and low input impedance. These are some of the properties of a BiCMOS inverter.
6. The inverter has __________
a) high current driving capability
b) occupies smaller area
c) high noise margin
d) all of the mentioned
Answer: d
Explanation: The inverter has high current driving capability, occupies smaller area and has high noise margins.
7. Output voltage swing should be reduced for a better performance of BiCMOS circuit.
a) true
b) false
Answer: a
Explanation: For a better performance BiCMOS circuit, the output voltage swing should be reduced. The possible maximum output peak-to-peak voltage obtained without clipping is called as output voltage swing.
8. BiCMOS inverter requires high load current sourcing.
a) true
b) false
Answer: a
Explanation: BiCMOS inverter needs high load current sinking and sourcing. Sinking provides a grounded connection to the load, whereas sourcing provides a voltage source to the load.
9. BiCMOS has _______ standby leakage current.
a) higher
b) lower
c) very low
d) none of the mentioned
Answer: a
Explanation: BiCMOS has higher standby leakage current and thus has high power consumption.
10. For improved base current discharge ________ enhancement type nMOS devices have to be added.
a) two
b) three
c) one
d) four
Answer: a
Explanation: For improved base current discharge, two enhancement type nMOS transistors have to be added.
11. The BJTs in the BICMOS circuit is in _____________ configuration.
a) Push-pull
b) Totem pole
c) Active high
d) Active low
Answer: b
Explanation: In BiCMOS circuit, the BJT transistors are in Totem pole configuration.
12. The MOSFETS are arranged in this configuration to provide __________
a) Zero static power dissipation
b) High Input impedance
c) Both zero static power dissipation and high input impedance
d) None of the mentioned
Answer: c
Explanation: MOSFETs provide zero static power dissipation and high input impedance.
This set of VLSI Multiple Choice Questions & Answers focuses on “Latch-up in CMOS”.
1. In latch-up condition, parasitic component gives rise to __________ conducting path.
a) low resistance
b) high resistance
c) low capacitance
d) high capacitance
Answer: a
Explanation: In latch-up condition, the parasitic component gives rise to low resistance conducting path between Vdd and Vss with disastrous results. Careful control during fabrication is necessary to avoid this problem.
2. Latch-up can be induced by __________
a) incident radiation
b) reflected radiation
c) etching
d) diffracted radiation
Answer: a
Explanation: Latch-up can be induced by glitches on the supply rail or by incident radiation.
3. How many transistors might bring up latch up effect in p-well structure?
a) two
b) three
c) one
d) four
Answer: a
Explanation: Two transistors and two resistances might bring up the latch-up effect in p-well structure. These are associated with p-well and with regions of the substrate.
4. Substrate doping level should be decreased to avoid the latch-up effect.
a) true
b) false
Answer: b
Explanation: An increase in substrate doping level with a consequent drop in the value of Rs can be used as a remedy for latch-up problem.
5. What can be introduced to reduce the latch-up effect?
a) latch-up rings
b) guard rings
c) latch guard rings
d) substrate rings
Answer: b
Explanation: The introduction of guard rings can reduce the effect of latch-up problem. Guard rings are diffusions which decouple the parasitic bipolar transistors.
6. Which process produces a circuit which is less prone to latch-up effect?
a) CMOS
b) nMOS
c) pMOS
d) BiCMOS
Answer: d
Explanation: BiCMOS process produces circuits that are less likely to suffer from latch-up problems where as CMOS circuits are very highly prone to latch-up problems.
7. Which one of the following is the main factor for reducing the latch-up effect?
a) reduced p-well resistance
b) reduced n-well resistance
c) increased n-well resistance
d) increased p-well resistance
Answer: b
Explanation: One of the main factors in reducing the latch-up effect is reduced n-well resistance Rw. Reduction in Rw means that a larger lateral current is necessary to invite latch-up and higher value of holding current is also required.
8. The parasitic PNP transistor has the effect of _______ carrier lifetime.
a) increasing
b) decreasing
c) exponentially decreasing
d) exponentially increasing
Answer: b
Explanation: The parasitic PNP transistor has the effect of reducing carrier lifetime in the n-base region.
9. The reduction in carrier lifetime brings about __________
a) reduction in alpha
b) reduction in beta
c) reduction in current
d) reduction in voltage
Answer: b
Explanation: The parasitic PNP transistor has the effect of reducing carrier lifetime in the n-base region which results in radiation in beta.
10. To reduce latch-up effect substrate resistance should be high.
a) true
b) false
Answer: b
Explanation: To reduce the latch-up effect, substrate resistance Rs should be low. Reduction of Rs and Rw means that larger lateral current is necessary to invite latch-up.
11. Latch-up is the generation of __________
a) low impedance path
b) high impedance path
c) low resistance path
d) high resistance path
Answer: a
Explanation: Latch-up is the generation of low-impedance path in CMOS chips between the power supply and ground rails.
12. Latch-up is brought about by BJTs __________
a) with positive feedback
b) with negative feedback
c) with no feedback
d) without BJT
Answer: a
Explanation: Latch-up occurs due to BJTs for silicon-controlled rectifiers with positive feedback and virtually short circuit the power and ground rail.
13. Sudden transient in power can cause latch-up.
a) true
b) false
Answer: a
Explanation: Sudden transient in power and ground buses are also among the reason which causes latch-up effect.
14. BJT gain should be ______ to avoid latch-up effect.
a) increased
b) decreased
c) should be maintained constant
d) changed randomly
Answer: b
Explanation: BJT gain should be reduced by lowering the minority carrier lifetime through doping of the substrate to lower the latch-up effect.
This set of VLSI Multiple Choice Questions & Answers focuses on “BiCMOS Logic Gates”.
1. The BiCMOS are preferred over CMOS due to ______________
a) Switching speed is more compared to CMOS
b) Sensitivity is less with respect to the load capacitance
c) High current drive capability
d) All of the mentioned
Answer: d
Explanation: These are the 3 advantages of BiCMOS over CMOS.
2. The transistors used in BiCMOS are __________
a) BJT
b) MOSFET
c) Both BJT and MOSFETs
d) JFET
Answer: c
Explanation: BiCMOS is a combination of both MOSFET and BJT.
3. The high current driving capability of the BiCMOS is due to __________
a) NMOS in saturation mode
b) PMOS in saturation mode
c) CMOS
d) BJT
Answer: d
Explanation: BJT has the high current driving capability.
4. In BiCMOS inverter, the BJT used are __________
a) Only Npn BJT
b) Only Pnp BJT
c) Both npn and pnp BJT
d) Multi emitter npn BJT
Answer: a
Explanation: npn BJTs are used in BiCMOS inverter.
5. Which of the following is the drawback of the BiCMOS circuits?
a) Sensitivity is less load capacitance
b) Bipolar transistors are used for driving current to the load capacitance but not for the logic operations
c) Increased fabrication Complexity
d) All of the mentioned
Answer: c
Explanation: The other 2 are the merits of BiCMOS, Increased fabrication Complexity is a demerit of BiCMOS circuits.
6. The Bipolar Transistor is fabricated on __________
a) Same substrate of nMOS
b) N-well in p Substrate
c) P-well in n Substrate
d) Same substrate of pMOS
Answer: a
Explanation: BiCMOS is fabricated on the same substrate of nMOS.
7. The n-well created for Bipolar Transistor in BiCMOS is used as __________
a) Substrate
b) Collector
c) Emitter
d) None of the mentioned
Answer: b
Explanation: The created nWell is used as Collector region for BiCMOS.
8. The n-well collector is formed by __________
a) Lightly doped n-type epitaxial layer on p-Substrate
b) Heavily doped n-type epitaxial layer on p-Substrate
c) Lightly doped n-type diffused layer on p-Substrate
d) Heavily doped n-type diffused layer on p-Substrate
Answer: a
Explanation: To make the doping concentration less than the emitter.
9. The collector contact region is doped with higher concentration of n-type impurities due to __________
a) It creates a depletion region at the contact surface
b) It creates a low conductivity path between collector region and contact
c) It reduces contact resistance
d) It can withstand high voltages as compared to collector region
Answer: c
Explanation: The collector contact region is doped with higher concentration of n-type impurities reduces contact resistance.
10. Which is the proper BiCMOS inverter circuit?
a) vlsi-questions-answers-bicmos-logic-gates-q10a
b) vlsi-questions-answers-bicmos-logic-gates-q10b
c) vlsi-questions-answers-bicmos-logic-gates-q10c
d) vlsi-questions-answers-bicmos-logic-gates-q10d
Answer: c
Explanation: None.
11. In the following diagram of BiCMOS, the labels a, b, c, d denote?
vlsi-questions-answers-bicmos-logic-gates-q11
a) A = Collector, B = Base, C = Source, D = Drain
b) A = Emitter, B = Base, C = Drain, D = Source
c) A = Emitter, B = Collector, C = Source, D = Drain
d) A = Collector, B = Emitter, C = Drain, D = Source
Answer: c
Explanation: None.
12. What is the work of BJT in BiCMOS?
a) Current controlled Voltage source
b) Voltage controlled Current source
c) Current controlled current source
d) Voltage controlled current source
Answer: b
Explanation: The Current Ic and Ie are controlled by base emitter bias voltage.
13. In BiCMOS, the analysis of the operation of BJT is well explained by ___________
a) RC Model
b) Emitter resister model
c) Ebers Moll Model
d) Hybrid model
Answer: c
Explanation: None.
14. The Ebers Moll equivalent circuit of BJT operating in forward active region is?
a) vlsi-questions-answers-bicmos-logic-gates-q14a
b) vlsi-questions-answers-bicmos-logic-gates-q14b
c) vlsi-questions-answers-bicmos-logic-gates-q14c
d) None of the mentioned
Answer: b
Explanation: None.
15. The transfer characteristics of BiCMOS inverter is?
a) vlsi-questions-answers-bicmos-logic-gates-q15a
b) vlsi-questions-answers-bicmos-logic-gates-q15b
c) vlsi-questions-answers-bicmos-logic-gates-q15c
d) None of the mentioned
Answer: a
Explanation: None.
This set of VLSI Multiple Choice Questions & Answers focuses on “Stick Diagram”.
1. Stick diagrams are those which convey layer information through?
a) thickness
b) color
c) shapes
d) layers
Answer: b
Explanation: Stick diagrams are those which convey layer information through color codes. Thickness is not considered in this stick diagram representation.
2. Which color is used for n-diffusion?
a) red
b) blue
c) green
d) yellow
Answer: c
Explanation: Green color is used to show the presence of n-diffusion layer. The n-type diffusion will dope the source or drain region in the p-well region.
3. Which color is used for implant?
a) red
b) blue
c) green
d) yellow
Answer: d
Explanation: Yellow color is used to represent implant layer.
4. Which color is used for contact areas?
a) red
b) brown
c) black
d) blue
Answer: c
Explanation: Black color is used to represent contact areas. This is the part where two different touch or cross each other.
5. Which color is used for polysilicon?
a) brown
b) red
c) white
d) orange
Answer: b
Explanation: Red is used to represent polysilicon layers. It is a semi-conductor like material and is a hyper pure form of silicon.
6. Which color is used for polysilicon 2?
a) blue
b) brown
c) orange
d) white
Answer: c
Explanation: Orange color is used to represent polysilicon-2 layer.
7. Which color is used for buried contact?
a) black
b) white
c) green
d) brown
Answer: d
Explanation: Brown color is used to represent buried contact. Buried contact is most widely used, subject to fewer design rule restrictions are smaller in area.
8. n and p transistors are separated by using __________
a) differentiation line
b) separation line
c) demarcation line
d) black line
Answer: c
Explanation: Demarcation line separates n and p transistors. Demarcation line is similar to dotted line in brown.
9. _______ layer should be over ______ layer.
a) ntype, polysilicon
b) polysilicon, ntype
c) ptype, ntype
d) ntype, ptype
Answer: b
Explanation: Polysilicon layer should be over n-type layer. This is the standard pattern used in stick diagram representation.
10. How is nMOS depletion mode transistor represented?
a) vlsi-questions-answers-stick-diagram-q10a
b) vlsi-questions-answers-stick-diagram-q10b
c) vlsi-questions-answers-stick-diagram-q10c
d) vlsi-questions-answers-stick-diagram-q10d
Answer: c
Explanation: nMOS depletion mode transistor can be represented by using polysilicon over ntype layer and with an implant.
11. Implant is represented using ___________
a) black, dark line
b) black, dotted line
c) yellow, dark line
d) yellow, dotted line
Answer: d
Explanation: Implant is represented using yellow color dotted lines. It is drawn in the middle of the nMOS or pMOS wherever the implant is used.
12. Stick diagram gives the position of placement of the element.
a) true
b) false
Answer: b
Explanation: Stick diagram does not show exact placement of components, transistor length, wire length and width, tub boundaries, etc.
13. When two or more cuts of same type cross or touch each other, that represents ____________
a) contact cut
b) electrical contact
c) like contact
d) cross contact
Answer: b
Explanation: When two or more sticks of same type cross or touch each other, then that forms a contact called electrical contact.
This set of VLSI Multiple Choice Questions & Answers focuses on “Design Rules and Layout-1”.
1. Circuit design concepts can also be represented using a symbolic diagram.
a) true
b) false
Answer: a
Explanation: Circuit design concepts can be represented using stick diagrams and symbolic diagrams. Stick diagrams represents different layers with color codes. Symbolic diagram represents the structure with symbols with color codes.
2. Circuit designers need _______ circuits.
a) tighter
b) smaller layout
c) decreased silicon area
d) all of the mentioned
Answer: d
Explanation: Circuit designers in general prefer tighter, smaller layouts for improved performance and decreased silicon area.
3. Process engineers want ______ process.
a) smaller
b) tighter
c) reproducible
d) non reproducible
Answer: c
Explanation: Process engineers want design rules which are controllable and reproducible process.
4. Maturity level of the process line affects design rules.
a) true
b) false
Answer: a
Explanation: Yes, the maturity level of the process line affects design rules.
5. Design rules does not specify __________
a) linewidths
b) separations
c) extensions
d) colours
Answer: d
Explanation: Design rules specify line widths, separations and extensions in terms of lambda.
6. The width of n-diffusion and p-diffusion layer should be?
a) 3λ
b) 2λ
c) λ
d) 4λ
Answer: b
Explanation: The width of n-diffusion and p-diffusion should be 2λ according to design rules.
7. What should be the spacing between two diffusion layers?
a) 4λ
b) λ
c) 3λ
d) 2λ
Answer: c
Explanation: The spacing between two diffusion layers should be 3λ according to design rules and standards.
8. What should be the width of metal 1 and metal 2 layers?
a) 3λ, 3λ
b) 2λ, 3λ
c) 3λ, 4λ
d) 4λ, 3λ
Answer: c
Explanation: The width of the metal 1 layer should be 3λ and metal 2 should be 4λ.
9. Implant should extend _______ from all the channels.
a) 2λ
b) 3λ
c) 4λ
d) λ
Answer: a
Explanation: Implant for a n-mos depletion mode transistor should extend minimum of 2λ from the channel in all the directions.
10. Which type of contact cuts are better?
a) buried contacts
b) butted contacts
c) butted & buried contacts
d) none of the mentioned
Answer: a
Explanation: Buried contacts are much better than butted contacts. In butted contacts the two layers are joined together or binded together using adhesive type of material where as in buried contact one layer is interconcted or fitted into another.
11. Which design method occupies or uses lesser area?
a) lambda rules
b) micron rules
c) layer rule
d) source rule
Answer: b
Explanation: Micron rules occupies or consumes lesser area. 50% of the area usage can be reduced by using micron rules over lambda rules.
12. Which gives scalable design rules?
a) lambda rules
b) micron rules
c) layer rules
d) thickness rules
Answer: a
Explanation: Lambda rules gives scalable design rules and micron rules gives absolute dimensions.
13. Devices designed with lambda design rules are prone to shorts and opens.
a) true
b) false
Answers: b
Explanation: Lambda design rules prevent shorting, opens, contact from slipping out of the area to be contacted.
This set of VLSI Questions and Answers for Freshers focuses on “Design Rules and Layout-2”.
1. Diffusion and polysilicon layers are connected together using __________
a) butting contact
b) buried contact
c) separate contact
d) cannot be connected
Answer: a
Explanation: Diffusion and polysilicon layer are joined together using butting contact. In butting contact the two layers are joined or binded together.
2. Which is a more complex process?
a) buried contact
b) butting contact
c) buried & butting contact
d) none of the mentioned
Answer: a
Explanation: Butting contact is a complex process whereas buried contact is simple process because butting contact should be done more carefully to serve well and be strong.
3. Which contact cut occupies smaller area?
a) buried contact
b) butting contact
c) buried & butting contact
d) none of the mentioned
Answer: a
Explanation: Buried contact occupies smaller area than butting contact as in buried contacts one layer will be completely within or almost within the another layer.
4. Isolation layer between two metal layers must be thinner.
a) true
b) false
Answer: b
Explanation: Isolation layer between two metal layers should be thicker. Metal to metal separation is large and is brought about mainly by difficulties in defining metal edges accurately.
5. The oxide layer below the first metal layer is deposited using __________
a) diffusion method
b) chemical vapour deposition
c) solid deposition
d) scattering method
Answer: b
Explanation: The oxide layer below the first metal layer is depostied using chemical vapour deposition method. This is a chemical process used to produce high quality high performance solid materials.
6. Which layer is used for power and signal lines?
a) metal
b) polysilicon
c) n-diffusion
d) p-diffusion
Answer: a
Explanation: Metal layers are used for power and signal lines as metals has good thermal and electrical conductivity.
7. Minimum feature size for thick oxide is?
a) 2λ
b) 3λ
c) 4λ
d) λ
Answer: b
Explanation: The minimum feature size for thick oxide is 3λ and minimum separation between thin oxide regions is also 3λ.
8. Hatching is compatible with __________
a) monochrome encoding
b) bicode encoding
c) tricode encoding
d) not compatible with any encoding
Answer: a
Explanation: Hatching is compatible with monochrome encoding and also may be added to color mask coding. It is designed using closely spaced lines or sticks.
9. Minimum n-well width should be ____________ micro meter.
a) 2
b) 3
c) 4
d) 6
Answer: b
Explanation: The minimum width of n-well is 3 micro meter because n-well should be with little thickness and in it p-type devices are formed.
10. The minimum spacing between two n-well is _____ micro meter.
a) 4
b) 5
c) 8
d) 8.5
Answer: d
Explanation: The minimum spacing between two n-well is 8.5 micro meter according to the lambda based design rules.
11. Which can bring about variations in threshold voltage?
a) oxide thickness
b) ion implantation
c) poly variations
d) all of the mentioned
Answer: d
Explanation: One of the problems in the manufacture using design rule is that variation in threshold voltage occurs. And this is caused by oxide thickness, ion implantation and poly variations.
12. What are the advantages of design rules?
a) durable
b) scalable
c) portable
d) all of the mentioned
Answer: d
Explanation: Some of the advantages of generalised design rules are those are durable, scalable, portable, increases designer efficiency and automatic translation to final layout can be done.
13. Minimum diffusion space is __________
a) 2λ
b) 3λ
c) 4λ
d) λ
Answer: b
Explanation: Minimum diffusion space is 3λ to avoid the possibility of their associated regions overlapping and conducting current.
14. Contact cuts should be ____ apart.
a) 2λ
b) 3λ
c) 4λ
d) λ
Answer: a
Explanation: Two contact cuts should be 2λ apart to prevent holes from merging.
This set of VLSI Multiple Choice Questions & Answers focuses on “Sheet Resistance”.
1. Area A of a slab can be given as ____________
a) t * W
b) t / W
c) L * W
d) L * t
Answer: a
Explanation: Area A of a uniform slab is given as the product of thickness t and width W of the slab. Its unit is 2 .
2. For 5 micron technology, What is the Rs value for a metal?
a) 0.03
b) 0.04
c) 0.02
d) 0.01
Answer: a
Explanation: For a 5 micron technology, the Rs value for a metal is 0.03. It is the standard typical sheet resistance values.
3. For 2 micron technology, what is the Rs value for polysilicon?
a) 10-40
b) 20-50
c) 15-30
d) 15-100
Answer: c
Explanation: For 2 micron technology, the Rs value for polysilicon is 15-30.
4. Which has higher Rs values?
a) n-diffusion
b) p-diffusion
c) n-diffusion & p-diffusion
d) none of the mentioned
Answer: b
Explanation: The Rs values for p-diffusion is 2.5 times greater than that of the n-diffusion.
5. For 1.2 micron technology, what is the Rs value for diffusion?
a) 20-40
b) 20-45
c) 15-30
d) 25-50
Answer: b
Explanation: For 1.2 micron technology, the Rs value for diffusion is 20-45.
6. What is the relationship between channel resistance and sheet resistance?
a) R = Rs
b) R = Z*Rs
c) R = Z/Rs
d) R = Rs/Z
Answer: b
Explanation: The relationship between channel resistance and sheet resistance can be given as R = Z*Rs. Sheet resistance is a measure of the resistance of thin films that are nominally uniform in thickness.
7. Z can be given as the ration of ___________
a) lower channel by upper channel
b) upper channel by lower channel
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: Z ratio can be given as the ratio of upper channel to lower channel. It is just a numerical quantity and has no unit.
8. Deposition of metal or silicon alloy can be done by ___________
a) sputtering
b) evaporation
c) sputtering and evaporation
d) deposition should not be made
Answer: c
Explanation: Deposition of metal or silicon alloy can be done by either sputtering or evaporation. Sputtering is a process whereby particles are ejected from a solid target material due to bombardment of the target by energetic particles.
9. Deposition of metal can be done by co-evaporation.
a) true
b) false
Answer: a
Explanation: Deposition of metal or silicon alloy can also be done by co-evaporation from the elements.
10. Processing of the device is better using ___________
a) polysilicon
b) silicides
c) polysilicon & silicides
d) none of the mentioned
Answer: a
Explanation: Processing of the device is better using polysilicon than silicides even though the properties of silicides are better than polysilicon.
This set of VLSI Multiple Choice Questions & Answers focuses on “Area Capacitance”.
1. Conducting layer is separated from substrate using ____________
a) dielectric layer
b) silicon layer
c) metal layer
d) diffusion layer
Answer: a
Explanation: Conducting layer is separated from the substrate by using dielectric or insulating layer as both are electrical insulators that can be polarized by an applied electric field.
2. Gate to channel capacitance of 5 micron technology is _____ pF X 10 2 .
a) 1
b) 2
c) 4
d) 0.4
Answer: c
Explanation: Gate to channel capacitance of 5 micron technology is 4 pF X 10 2 . It is the standard typical calculated value.
3. Area capacitance of diffusion region of 2 micron technology is _____ pF X 10 2 .
a) 2
b) 2.75
c) 3.75
d) 4.75
Answer: c
Explanation: Area capacitane of diffusion region of 2 micron technology is 3.75 pF X 10 2 .
4. What is the relative capacitance of diffusion region of 5 micron technology?
a) 1
b) 0.25
c) 1.25
d) 2
Answer: b
Explanation: The relative capacitance of diffusion region of 5 micron technology is 0.25. The relative value is calculated by comparing two values of same type.
5. A feature size square has ___________
a) L > W
b) W > L
c) L = W
d) L > d
Answer: c
Explanation: A feature size square has L = W and its gate to channel capacitance value is called as square Cg.
6. What is the standard square Cg value of a 5 micron technology?
a) 0.01 pF
b) 0.1 pF
c) 1 pF
d) 10 pF
Answer: a
Explanation: The standard square Cg value of a 5 micron technology is 0.01 pF. This standard square Cg value can be calculated by using the area of standard square value and the capacitance value.
7. What is the standard square Cg value of a 1.2 micron technology?
a) 0.01 pF
b) 0.0023 pF
c) 0.023 pF
d) 0.23 pF
Answer: b
Explanation: The standard square Cg value of a 1.2 micron technology is 0.0023 pF.
8. Relative area for L = 20λ and W = 3λ is?
a) 10
b) 15
c) 1/15
d) 1/10
Answer: b
Explanation: Relative area for L = 20λ and W = 3λ is = / = 15. Relative area has no unit as two quantities of same type have been used.
9. What is the value of gate capacitance?
a) 0.25 square Cg
b) 1 square Cg
c) 1.25 square Cg
d) 1.5 square Cg
Answer: b
Explanation: The value of gate capacitance is one square Cg. This is the standard value.
10. What is the delay unit of 5 micron technology?
a) 1 nsec
b) 0.1 nsec
c) 0.01 nsec
d) 1 sec
Answer: b
Explanation: Delay unit of 5 micron technology is 0.1 nsec.
11. What is the delay unit of 1.2 micron technology?
a) 0.064 nsec
b) 0.0064 nsec
c) 0.046 nsec
d) 0.0046 nsec
Answer: c
Explanation: The delay unit of 1.2 micron technology is 0.046 nsec.
12. What is the transition point of an inverter?
a) Vdd
b) 0.5 Vdd
c) 0.25 Vdd
d) 2 Vdd
Answer: b
Explanation: The transition point of an inverter is 0.5 Vdd. The transition point is the point where different phases of same substance can be obtained in equilibrium.
13. What is the desired or safe delay value for 5 micron technology?
a) 0.3 nsec
b) 0.5 nsec
c) 0.1 nsec
d) 0.2 nsec
Answer: a
Explanation: The desired or safe delay value for 5 micron technology is 0.3 nsec.
This set of VLSI Multiple Choice Questions & Answers focuses on “Inverter Delays”.
1. The resistance value associated with Rp.u is?
a) 2Rs
b) Rs
c) 4Rs
d) Rs/2
Answer: c
Explanation: The resistance value associated with Rp.u. is 4Rs. Resistance is the measure of difficulty to pass an electric current through that material.
2. The resistance value associated with Rp.d. is?
a) 2Rs
b) Rs
c) 4Rs
d) Rs/2
Answer: b
Explanation: The resistance value associated with Rp.d. is 1Rs. This is the measure of difficulty to pass current through the pull-down device.
3. The overall delay of nMOS inverter pair is?
a) 4Ć®
b) Ć®
c) 5Ć®
d) 2Ć®
Answer: c
Explanation: The overall delay of nMOS inverter pair is Ć®+4Ć® = 5Ć®. This delay is the time taken for the input signal to get inverted and arrive at the output.
4. The inverter pair delay for inverters having 4:1 ratio is?
a) 4Ć®
b) Ć®
c) 5Ć®
d) 2Ć®
Answer: c
Explanation: The inverter pair delay for inverters having 4:1 ratio is 5Ć®. This measure of delay is for two inverters, in which the output of the first is given as the input for the second inverter.
5. The asymmetry of resistance value can be eliminated by ____________
a) decreasing the width
b) increasing the width
c) increasing the length
d) increasing the width
Answer: b
Explanation: The asymmetry of resistance value can be eliminated by increasing the width of the p-device channel.
6. The ratio of rise time to fall time can be equated to ___________
a) βn/βp
b) βp/βn
c) βp*βn
d) βp/2βn
Answer: a
Explanation: The ratio of rise time to fall time can be equated to βn/βp. Rise time is the time taken by a signal to change from a specified low value to a specified high value. Fall time is the time taken for the amplitude of a pulse to decrease from a specified value to another specified value.
7. The value µn is equal to ___________
a) µp
b) 0.5µp
c) 1.5µp
d) 2.5µp
Answer: d
Explanation: The value of µn = 2.5 µp. This shows that µn value is greater than that of the µp.
8. Which quantity is slower?
a) rise time
b) fall time
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: Rise time is slower by a factor of 2.5 than fall time.
9. Condition for achieving symmetrical operation is ___________
a) Wp = Wn
b) Wp greater than Wn
c) Wp lesser than Wn
d) Wp lesser than 2Wn
Answer: b
Explanation: The condition for achieving symmetrical operation is Wp = 2.5 Wn.
10. Rise time and fall time is _____ to load capacitance CL.
a) directly proportional
b) inversely proportional
c) exponentially equal
d) not related
Answer: a
Explanation: Rise time and fall time is directly proportional to load capacitance CL.
11. Rise time and fall time is ________ to Vdd.
a) directly proportional
b) inversely proportional
c) exponentially equal
d) not related
Answer: b
Explanation: Rise time and fall time are inversely proportional to Vdd. This shows that if Vdd is reduced fall time and rise time increase.
This set of VLSI Multiple Choice Questions & Answers focuses on “Drivers”.
1. For shorter delays ______ resistance should be used.
a) smaller
b) larger
c) does not depend on resistance
d) very large
Answer: a
Explanation: For shorter delays low resistance should be used as delay is directly proportional or related to resistance.
2. To reduce resistance value of inverters, channels must be made __________
a) wider
b) narrower
c) lenghthier
d) shorter
Answer: a
Explanation: Channels must be made wider to reduce the resistance value that is low resistance values for Zp.u. ad Zp.d. imply low L:W ratios and thus consequently an inverter to meet this need occupies a larger area.
3. As width increases, capacitive load __________
a) increases
b) decreases
c) does not change
d) exponentially increases
Answer: a
Explanation: As width of the channel increases, capacitive load also increases and with this the area occupied also increases. The rate at which the width increases affects the stages N and load capacitance.
4. Delay per stage for logic 0 to 1 transition can be given as __________
a) fĆ®
b) 2fĆ®
c) 3fĆ®
d) 4fĆ®
Answer: a
Explanation: Delay per stage for logic 0 to 1 transition can be given as fĆ®. With large f, N decreases but delay per stage increases.
5. Delay per stage for logic 1 to 0 transition can be given as __________
a) fĆ®
b) 2fĆ®
c) 3fĆ®
d) 4fĆ®
Answer: d
Explanation: Delay per stage for logic 1 to 0 transition can be given as 4fĆ®. Using the delay for transition from 1 to 0 and 0 to 1 total nMOS delay can be obtained.
6. What is the total delay of an nMOS pair?
a) fĆ®
b) 2fĆ®
c) 5fĆ®
d) 4fĆ®
Answer: c
Explanation: Total delay of an nMOS pair is equal to 5fĆ®. This can be calculated by knowing delay per stage, that is for two different transitions from 0 to 1 and vice versa.
7. What is the total delay of a CMOS pair?
a) 5fĆ®
b) 7fĆ®
c) 8fĆ®
d) 4fĆ®
Answer: b
Explanation: Total delay of an CMOS pair is equal to 7fĆ®. This can be calculated by knowing thee delay per stage of CMOS.
8. The number of stages N can be given as ___________
a) ln*ln
b) ln/ln
c) ln/ln
d) ln/ln
Answer: b
Explanation: The number of stages N can be given as ln/ln. By knowing whether the number of stages N is even or odd we can calculate the total delay for nMOS, CMOS etc.
9. When number of stages N is even, the total delay for nMOS can be?
a) 1.5NfĆ®
b) 2.5NfĆ®
c) 3.5NfĆ®
d) 4.5NfĆ®
Answer: b
Explanation: When number of stages N is even, the total delay for nMOS can be given as 2.5NfĆ®. This is calculated by using the formula *5fĆ®.
10. When number of stages N is even, the total delay for CMOS can be?
a) 1.5NfĆ®
b) 2.5NfĆ®
c) 3.5NfĆ®
d) 4.5NfĆ®
Answer: c
Explanation: When the number of stages N is even, the total delay for CMOS can be given as 3.5NfĆ®. This is calculated by using the formula *7fĆ®.
11. In BiCMOS drivers, the input voltage Vbe is _______ on base width.
a) directly proportional
b) inversely proportional
c) logarithmically proportional
d) exponentially proportional
Answer: c
Explanation: In BiCMOS driver, the input voltage Vbe is logarithmically proportional to the base width Wb and on electron mobility.
12. Which has a larger value?
a) Tin
b) TL
c) Rc
d) None of the mentioned
Answer: a
Explanation: In BiCMOS drivers, the initial time Tin necessary to charge base emitter junction is larger than the time TL requires to charge the output load capacitance.
13. In BiCMOS driver, a good bipolar transistor should have ___________
a) low Rc
b) high hfe
c) high gm
d) all of the mentioned
Answer: d
Explanation: In BiCMOS drivers, a good bipolar transistor should have low Rc, high hfe, high gm, etc.
This set of VLSI Multiple Choice Questions & Answers focuses on “Propagation Delays”.
1. Propagation time is directly proportional to ____________
a) x
b) 1/x
c) x 2
d) 1/x 2
Answer: c
Explanation: Propagation time is directly proportional to square of the Propagation distance (x 2 ). It is the time taken by the signal to move from input port to output port.
2. The total resistance can be given as ___________
a) nRs
b) nrRs
c) rRs
d) Rs
Answer: b
Explanation: The total resistance can be given as the product of nrRs where r is the relative resistance per section in terms of Rs.
3. Total capacitance can be given as ___________
a) n
b) nc
c) c
d) square Cg
Answer: b
Explanation: Total capacitance can be given as the product of nc where c is the relative capacitance per section in terms of square Cg.
4. Overall delay is directly proportional to ___________
a) n
b) 1/n
c) n 2
d) 1/n 2
Answer: c
Explanation: The overall delay is directly proportional to n 2 , where n is the number of pass transistors in series.
5. The number of pass transistors connected in series can be increased if ___________
a) compressor is connected
b) buffer is connected
c) ground is connected
d) voltage regulator is connected
Answer: b
Explanation: The number of pass transistors connected in series can be increased by connecting buffer in between.
6. Buffer is used because ___________
a) it increases the speed
b) decreases sensitivity to noise
c) decreases speed
d) does not affect speed
Answer: a
Explanation: Buffer is used for long polysilicon runs because it increases the speed and reduces the sensitivity to noise.
7. The overall delay is ______ to the relative resistance r.
a) directly proportional
b) inversely proportional
c) exponentially proportional
d) not dependent
Answer: a
Explanation: The overall delay is directly proportional to the relative resistance r. Overall delay is given as product of n^2rcĆ®.
8. Small disturbances of noise ___________
a) decreases the inverter voltage
b) increases the output voltage
c) switches the inverter stage between 0 to 1
d) does not switch the stage and keeps it stable
Answer: c
Explanation: Small disturbances of noise switches the inverter stage between 0 and 1 or vice versa. It disturbs the normal operation or behaviour.
9. The buffer speeds up the ___________
a) rise time
b) fall time
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: The buffer speeds up the rise time of propogated signal edge. A buffer is the combination of two inverters in which one output is fed to the other as the input.
10. Overall delay increases as n ___________
a) increases
b) decreases
c) exponentially decreases
d) logarithmically decreases
Answer: a
Explanation: Overall delay increases as n increases where n is the number of pass transistors connected in series.
This set of VLSI Multiple Choice Questions & Answers focuses on “Wiring Capacitances”.
1. Which contributes to the wiring capacitance?
a) fringing fields
b) interlayer capacitance
c) peripheral capacitance
d) all of the mentioned
Answer: d
Explanation: The sources of capacitances that contribute to the total wiring capacitance are fringing field capacitance, interlayer capacitance and peripheral capacitance.
2. What does the value d in fringing field capacitance measures?
a) thickness of wire
b) length of the wire
c) wire to substrate separation
d) wire to wire separation
Answer: c
Explanation: The quantity d in fringing field capacitance measures the wire to substrate separation. It is the distance between the wire and the substrate used in the device.
3. Total wire capacitance is equal to ___________
a) area capacitance
b) fringing field capacitance
c) area capacitance + fringing field capacitance
d) peripheral capacitance
Answer: c
Explanation: Total wire capacitance can be given as the sum of area capacitance and fringing field capacitance.
4. Interlayer capacitance occurs due to ___________
a) separation between plates
b) electric field between plates
c) charges between plates
d) parallel plate effect
Answer: d
Explanation: Interlayer capacitance occurs due to a parallel plate effect between one layer and another. When one capacitance value comes closer to another they create some combined effects.
5. Which capacitance must be higher?
a) metal to polysilicon capacitance
b) metal to substrate capacitance
c) metal to metal capacitance
d) diffusion capacitance
Answer: a
Explanation: Metal to polysilicon capacitance should be higher than metal to substrate capacitance. This is due to that when one layer underlies the other and in consequence interlayer capacitance is highly dependent on layout.
6. Peripheral capacitance is given in _________ eper unit length.
a) nano farad
b) pico farad
c) micro farad
d) farad
Answer: b
Explanation: Peripheral capacitance is given in picofarads per unit length. This is the sidewall capacitance. Each diode has this side wall capacitance.
7. For greater relative value of peripheral capacitance ___________ should be small.
a) source area
b) drain area
c) source & drain area
d) none of the mentioned
Answer: c
Explanation: The smaller the source or drain area, the greater the relative value of peripheral capacitance as they are both inversely related.
8. Diffusion capacitance is equal to ___________
a) area capacitance
b) peripheral capacitance
c) fringing field capacitance
d) area capacitance + peripheral capacitance
Answer: d
Explanation: Diffusion capacitance is given by the sum of area capacitance and peripheral capacitance.
9. Polysilicon is suitable for ___________
a) small distance
b) large distance
c) all of the mentioned’
d) none of the mentioned
Answer: a
Explanation: Polysilicon is unsuitable for routing Vdd or Vss other than for very small distance because of the relatively high Rs value of the polysilicon layer.
10. Which has a high voltage drop?
a) metal layer
b) polysilicon layer
c) diffusion layer
d) silicide layer
Answer: b
Explanation: Polysilicon layer has high voltage drop. It has a moderate RC product.
11. Which layer has high capacitance value?
a) metal
b) diffusion
c) silicide
d) polysilicon
Answer: b
Explanation: Diffusion or active layer has high capacitance value due to which it has low or moderate IR drop.
12. Which layer has high resistance value?
a) polysilicon
b) silicide
c) diffusion
d) metal
Answer: a
Explanation: Polysilicon layer has high resistance value and due to this it has high IR drop.
13. While measuring the output load capacitance Cgs, n and Cgs, p is not considered. Why?
a) Because Cgs, n and Cgs, p are the capacitances at the input nodes
b) Because Cgs, n and Cgs, p does not exist during the operation of CMOS inverter
c) Because Cgs, n and Cgs, p are storing opposite charges and cancel out each other during the calculation of load capacitance
d) None of the mentioned
Answer: a
Explanation: Cgs, n and Cgs, p are gate to source capacitances of nMOS and pMOS transistors in CMOS inverter. They are measured at input node. Therefore they are not considered for calculation of load capacitance.
14. During the calculation of load capacitance of a 1st stage CMOS inverter, the input node capacitances, Cgs, n and Cgs, p of the 2nd stage CMOS inverter is also considered.
a) True
b) False
Answer: b
Explanation: Instead thin oxide capacitance over the gate area is used for calculation.
This set of VLSI Multiple Choice Questions & Answers focuses on “Sheet Resistance of MOS Transistors and Inverters”.
1. The resistance of uniform slab of the conducting material is?
a) Linear with length
b) Inversely proportional to thickness
c) Inversely proportional to width
d) All of the mentioned
Answer: d
Explanation: The resistance of a uniform slab of conducting material can be expressed as
R = /.
2. The sheet resistance of the conducting material is?
a) RS = resistivity/length
b) RS = resistivity/width
c) RS = resistivity/thickness
d) None of the mentioned
Answer: c
Explanation: The sheet resistance of the conducting material is given by RS = resistivity/thickness.
3. In CMOS manufacturing process Sheet resistance is used instead of resistivity because _______________
a) Resistivity is same for all doped regions
b) Resistivity and thickness are characteristics which cannot be controlled by the circuit designer, and it is expressed as the single sheet resistance parameter
c) Sheet resistance is dimensionless quantity
d) Sheet resistance is equal to resistivity
Answer: b
Explanation: It is convenient to use Sheet resistance instead of resistivity because Resistivity and thickness are characteristics which cannot be controlled by the circuit designer, and it is expressed as the single sheet resistance parameter.
4. Compute the sheet resistance of a 0.17 µm thick Cu wire if resistivity of Cu wire is 1.7 µΩ-cm.
a) 0.01 Ω/square
b) 0.001 Ω/square
c) 10.0 Ω/square
d) 0.10 Ω/square
Answer: d
Explanation: Sheet resistance of copper is = (1.7*10 -8 )/(0.17*10 -6 )=0.10 Ω/square.
5. For semiconductors doped through diffusion or through surface peaked ion implantation we derive the sheet resistance as ___________
a) Average resistivity of semiconductor/thickness
b) Resistivity/thickness
c) Conductivity/thickness
d) None of the mentioned
Answer: a
Explanation: For semiconductors doped through diffusion or through surface peaked ion implantation we derive the sheet resistance using the average resistivity of the material.
6. Sheet resistance of a semiconductor is ___________
a) Inherent property of the material
b) Function of thickness of the material
c) Also called as Specific Resistance
d) All of the mentioned
Answer: b
Explanation: Resistivity is the inherent property of any conducting material. It is also called Specific Resistance. Sheet resistance is function of thickness as resistivity for a material is fixed.
7. Sheet resistance of semiconductor is directly measured using ___________
a) Ohmmeter
b) Four point probe measurement
c) Non-contact eddy current based testing device
d) Any of the mentioned
Answer: b
Explanation: Sheet resistance of semiconductor is directly measured using Four point probe measurement.
8. The resistance of the semiconductor material is 800Ω. The sheet resistance if the dimensions of the material is 0.125µm wide and 1 mm long is?
a) 10 Ω/square
b) 0.01 Ω/square
c) 0.10 Ω/square
d) 1 Ω/square
Answer: c
Explanation: We know that R=Rs.
Therefore Rs=R x W/L
Substituting the values of R, W and L, Rs is found to be 0.10 Ω/square.
9. The typical values of sheet resistance for the n-well semiconductor is ____________
a) 1-5 KΩ/square
b) 10-50 KΩ/square
c) 1-5 Ω/square
d) 100-500 Ω/square
Answer: a
Explanation: The n-well semiconductors have high sheet resistance in the range of 1-5 KΩ/square.
10. The typical values of sheet resistance for polysilicon semiconductor is?
a) 15-30 Ω/square
b) 150-300 Ω/square
c) 1.5-3 KΩ/square
d) 0.15-0.3 Ω/square
Answer: a
Explanation: The typical values of polysilicon semiconductor is 15-30 Ω/square.
11. For λ based design, what is the standard unit of capacitance, µ?
a) 0.01pF
b) 0.0032pF
c) 0.0023pF
d) All of the mentioned
Answer: a
Explanation: 5 µm x 5 µm x 4 pF x 10 -4 /µm 2 = 0.01pF.
12. If standard area is 2λ x 2λ, then the standard capacitance of a gate of length 30λ and width 6λ is?
a) 180 o Cg
b) 45 o Cg
c) 90 o Cg
d) 4 o Cg
Answer: b
Explanation: 30λ x 6λ/2λ x 2λ = 45 o Cg.
This set of VLSI Multiple Choice Questions & Answers focuses on “MOS Circuits Area Capacitance and Delay Unit”.
1. Which of the following mainly constitutes the output node capacitance?
a) Inter electrode capacitance
b) Stray capacitance
c) Junction Parasitic capacitance
d) All of the mentioned
Answer: c
Explanation: Output node capacitance mainly consists of junction parasitic capacitance.
2. The junction parasitic capacitance are produced due to ____________
a) Source diffusion regions
b) Gate diffusion regions
c) Drain diffusion region
d) All of the mentioned
Answer: c
Explanation: The junction parasitic capacitance are produced due to drain diffusion capacitance.
3. The amount of parasitic capacitance at the output node is determined by __________
a) Concentration of the impurity doped
b) Size of the total drain diffusion area
c) Charges stored in the capacitor
d) None of the mentioned
Answer: b
Explanation: The amount of parasitic capacitance is a linear function of drain diffusion area.
4. The dominant component of the total output capacitance in submicron technology is?
a) Drain diffusion capacitance
b) Gate oxide capacitance
c) Interconnect capacitance
d) Junction parasitic capacitance
Answer: c
Explanation: Interconnect capacitance becomes dominant component in submicron technology.
5. Which of the following is dominant component in input capacitance?
a) Gate diffusion capacitance
b) Gate parasitic capacitance
c) Gate oxide capacitance
d) All of the mentioned
Answer: c
Explanation: For input capacitance, gate oxide capacitance is the main component.
6. The total load capacitance is calculated as the sum of __________
a) Drain capacitance in series with input capacitance
b) Drain capacitance + interconnect capacitance +input capacitance
c) Drain capacitance + interconnect capacitance – input capacitance
d) Drain capacitance in parallel with input capacitance
Answer: b
Explanation: Total load capacitance = Drain capacitance + interconnect capacitance +input capacitance.
7. The interconnect capacitance is formed by __________
a) Area between the interconnect lines
b) Interconnect lines between the gates
c) Inter electrode capacitance of interconnect lines
d) None of the mentioned
Answer: b
Explanation: Interconnect line between the gates form interconnect capacitance.
8. The amount of gate oxide capacitance is determined by __________
a) Charges present on the gate
b) Polarity of the gate
c) Charges present on the substrate
d) Area of the gate
Answer: d
Explanation: The amount of gate oxide capacitance is determined by the area of the gate.
9. By what amount is Sidewall doping larger than substrate doping concentration.
a) 5
b) 2
c) 1
d) 10
Answer: d
Explanation: The sidewall doping is 10 times larger.
10. Zero bias depletion capacitance per unit length at sidewall junctions is given by, .
a) .Cj.xj
b) .Cj.xj
c) .Cj.xj 2
d) .Cj.xj 3
Answer: a
Explanation: Since the doping concentration is 10 times larger.
11. The typical value of capacitance in pF x 10 -4 /µm 2 for gate to channel in λ based design is?
a) 1
b) 0.4
c) 0.2
d) 4
Answer: d
Explanation: The gate to channel capacitance in λ based design is 4 pF x 10 -4 /µm 2 .
12. The active capacitance is also called as __________
a) Parasitic capacitance
b) Interconnect capacitance
c) Junction capacitance
d) Diffusion capacitance
Answer: d
Explanation: Diffusion capacitance is also called as active capacitance.
13. The value of diffusion capacitance in pF x 10 -4 /µm 2 in 2 µm design is?
a) 1.75
b) 4
c) 8
d) 16
Answer: c
Explanation: Diffusion capacitance has a value of 8 pF x 10 -4 /µm 2 .
14. The value of standard unit of capacitance is?
a) 0.01pF
b) 0.0032pF
c) 0.0023pF
d) All of the mentioned
Answer: d
Explanation: The value of standard unit of capacitance depends on the design style used.
15. The standard unit of capacitance is defined as?
a) Capacitance of gate to channel of MOS transistor having W = L dimensions
b) Capacitance of gate to channel of n-MOS transistor having W = 3L dimensions
c) Capacitance of gate to channel of p-MOS transistor having 3W = L dimensions
d) Capacitance of gate to channel of n-MOS transistor having W = L dimensions and p-MOS having W=3L dimensions
Answer: a
Explanation: Standard capacitance is capacitance of gate to channel with standard area.
This set of VLSI Multiple Choice Questions & Answers focuses on “Capacitive Loads and Wiring Capacitances”.
1. The capacitances in MOSFET occurs due to _____________
a) Interconnects
b) Difference in Doping concentration
c) Difference in dopant materials
d) All of the mentioned
Answer: d
Explanation: The on-chip capacitances found in MOS circuits are due to interconnects, difference in Doping concentration, difference in dopant materials.
2. The parasitic capacitances found in MOSFET are ___________
a) Oxide related capacitances
b) Inter electrode capacitance
c) Electrolytic capacitance
d) All of the mentioned
Answer: a
Explanation: The parasitic device capacitances can be classified into two major groups: oxide-related
capacitances and junction capacitances.
3. The proper DC model of MOSFET with capacitances is?
a) vlsi-questions-answers-load-wiring-capacitance-q3a
b) vlsi-questions-answers-load-wiring-capacitance-q3b
c) vlsi-questions-answers-load-wiring-capacitance-q3c
d) None of the mentioned
Answer: c
Explanation: The capacitances exist between all the regions of the MOSFET.
4. The capacitance that exist between Gate and Bulk is called as ___________
a) Oxide parasitic capacitance
b) Metal oxide capacitance
c) MOS capacitance
d) None of the mentioned
Answer: a
Explanation: The capacitance that exist between Gate and Bulk is called as an oxide parasitic capacitance.
5. In Cut-off Mode, the capacitance Cgs will be equal to ___________
a) 2Cgd
b) 0
c) Cgb
d) All of the mentioned
Answer: b
Explanation: In cut-off mode, the conducting channel does not exist, so gate-to-source and the gate-to-drain capacitances are both equal to zero.
6. In cut-off mode, the value of gate to substrate capacitance is equal to ___________
a) Cox .
b) Cox W/ L
c) Cox* W*L
d) 0
Answer: c
Explanation: In Cut-off mode, the conducting channel does not exist, so gate-to-source and the gate-to-drain capacitances are both equal to zero. Therefore, the gate to substrate capacitance is equal to Cox* W*L.
7. In linear mode operation, the parasitic capacitances that exists are ___________
a) Nonzero Gate to source capacitance
b) Nonzero Gate to drain capacitance
c) Zero gate to substrate capacitance
d) All of the mentioned
Answer: d
Explanation: In linear-mode operation, the conducting channel exists, therefore there will be a finite amount of gate to source and gate to drain capacitances. Since the conducting channel exists, gate to substrate capacitance is reduced to zero.
8. In saturation mode operation, gate to drain capacitance is zero due to ___________
a) Gate and drain are interconnected
b) Channel length is reduced
c) Inversion layer doesn’t exist
d) Drain is connected to ground
Answer: b
Explanation: Due to the pinched off channel, the capacitance between source to drain is reduced to zero.
9. When MOSFET is operating in saturation region, the gate to source capacitance is?
a) 1/2*Cox*W*L
b) 2/3*Cox*W*L
c) Cox*W*L
d) 1/3*Cox*W*L
Answer: b
Explanation: Due to the reduction in channel length, gate to drain and gate to substrate capacitance are zero, the gate to channel capacitance as seen between the gate and the source is approximately defined as 2/3*Cox*W*L.
10. In the below graph, the regions marked as A,B,C are?
vlsi-questions-answers-load-wiring-capacitance-q10
a) A : Saturation, B : Linear, C : Cut-off
b) A :Cut-off, B : Linear, C : Saturation
c) A : Linear, B : Saturation, C : Cut-off
d) None of the mentioned
Answer: b
Explanation: The gate to substrate capacitance exists only in cut-off region, and gate to drain capacitance exist only in saturation region.
Hint: the graph can be analyzed from the gate to source voltage on x axis and regions can be determined.
11. The load capacitance is measured between ___________
a) Output node and input node
b) Output node and Vcc
c) Output node and ground
d) Input node and ground
Answer: c
Explanation: The load capacitance is measured at output node and ground.
12. The load capacitance is equivalent to ___________
a) Sum of all lumped linear capacitances between input and output node
b) Sum of all junction capacitance between Vcc and ground
c) Sum of all junction capacitance between input and output
d) Sum of all lumped linear capacitances between output node and ground
Answer: a
Explanation: The load capacitance is measured by sum of all lumped linear capacitances between input and output node.
13. Interconnect capacitance contributes to the load capacitance when the CMOS inverters are connected in cascade configuration.
a) True
b) False
Answer: a
Explanation: In cascade configuration the load capacitance is measured by sum of all the lumped capacitances and interconnect capacitance.
14. Interconnect capacitance is formed due to ___________
a) Junction capacitance between gate and substrate
b) Wire connecting the gates of 2 different inverters
c) Parasitic capacitance existing between metal and polysilicon connection between 2 inverters
d) All of the mentioned
Answer: c
Explanation: Parasitic capacitance existing between metal and polysilicon connection between 2 inverters causes the interconnect capacitance.
15. Which of the following parameters are found using load capacitance?
a) Delay time
b) Power consumption
c) Speed of the CMOS logic
d) All of the mentioned
Answer: d
Explanation: Using load capacitance, delay time, power consumption, speed of the CMOS logic can be measured.
This set of VLSI Multiple Choice Questions & Answers focuses on “Differential Amplifier”.
1. The difference output of the basic differential amplifier is taken at ___________
a) At X and ground
b) At Y and ground
c) Difference of the voltages at the gates of M1 and M2
d) Difference of the voltages between X and Y
Answer: d
Explanation: None.
2. The Differential output of the difference amplifier is the amplification of __________
a) Difference between the voltages of input signals
b) Difference between the output of the each transistor
c) Difference between the supply and the output of the each transistor
d) All of the mentioned
Answer: a
Explanation: None.
3. The inputs to the differential amplifier are applied at __________
a) At X and Y
b) At the gates of M1 and M2
c) All of the mentioned
d) None of the mentioned
Answer: b
Explanation: None.
4. The Maximum and minimum output of the Differential amplifiers is defined as:
a) Vmax = VDD, Vmin = -VDD
b) Vmax = VDD, Vmin = Rd.Iss
c) Vmax = VDD, Vmin = VDD – Rd.Iss
d) None of the mentioned
Answer: c
Explanation: None.
5. In Common Mode Differential Amplifier, the outputs Vout1 and Vout2 are related as:
a) Vout2 is in out of phase with Vout1 with same amplitude
b) Vout2 and Vout1 have same amplitude but the phase difference is 90 degrees
c) Vout1 and Vout2 have same amplitude and are in phase with each other and their respective inputs
d) Vout1 and Vout2 have same amplitude and are in phase with each other but out of phase with their respective inputs
Answer: d
Explanation: None.
6. In a small signal differential gain vs input CM level graph, the gain decreases after V2 due to:
a) As the input voltage increases, the output will be clipped
b) When the input voltage to the transistors are high, the transistor enters saturation region and increases the current, which inturn decreases the output voltage = VDD – Rd.Iss
c) When Common Mode voltage is greater than or equal to V2, the input transistors enter triode region, the gain begins to fall
d) Increasing the input voltage beyond V2 causes the gate oxide to conduct and the gain is reduced
Answer: c
Explanation: None.
This set of VLSI Multiple Choice Questions & Answers focuses on “Single Stage Amplifiers”.
1. The input output characteristic of an amplifier is
a) Linear function
b) Non Linear function
c) Sinusoidal function with change of phase
d) None of the mentioned
Answer: b
Explanation: The input output characteristic of an amplifier is non linear function. It is given by y = a0 + a1x + a2x^2…..
2. The amplifier works as a linear system for:
a) High frequency signals
b) Low frequency signals
c) Small signals
d) Large signals
Answer: c
Explanation: The amplifier works as linear system for small signals and the output y = a0+a1x.
3. In MOSFET amplifier, the input is applied as:
a) Voltage across gate and source
b) Voltage across drain and source
c) Current at gate
d) Current at Drain
Answer: a
Explanation: The input to MOSFET amplifier is gate to source voltage.
4. In MOSFET amplifier, the parameter that changes due to the changes in input is:
a) Small signal drain current
b) Large signal drain current
c) Voltage across substrate and source
d) None of the mentioned
Answer: a
Explanation: Due to the transconductance, drain current changes as input changes.
5. Input impedance of MOSFET amplifier in Common Source configuration is:
a) Very high at high frequencies
b) Very high at low frequencies
c) Very low at high frequencies
d) Very low at low frequencies
Answer: b
Explanation: Input impedance of MOSFET amplifier in Common Source configuration is very high at low frequencies.
6. In the below input output characteristic of MOSFET amplifier, if Vin > Vin1, the MOSFET is said to operate in:
vlsi-questions-answers-single-stage-amplifiers-q6
a) Saturation region
b) Cutoff region
c) Triode region
d) None of the mentioned
Answer: c
Explanation: When Vin>Vin1, then the transistor is said to operate in triode region.
7. The voltage gain of the MOSFET is given by:
a) Av = -βRd
b) Av = ÎłRd
c) Av = -gmRd
d) None of the mentioned
Answer: c
Explanation: The voltage gain is equal to negative of product of transconductance and resistance.
8. The MOSFET is said to be in diode connected configuration if:
a) A diode is placed between supply and drain
b) A diode is placed between source and ground
c) Source and gate are connected
d) Drain and gate are connected
Answer: d
Explanation: A MOSFET connected in such a way that both gate and drain are connected to supply, then it is said to be in Diode connected condition.
9. The diode connected MOSFET acts as:
a) Active element for amplification
b) Voltage source
c) Current Source
d) Load Impedance
Answer: d
Explanation: The diode connected configuration of MOSFET acts as Load impedance.
10. In the below circuit, if the levels of input and output vary, the gain is found to:
vlsi-questions-answers-single-stage-amplifiers-q10
a) Increase linearly as input level increases
b) Decrease linearly as output level decreases
c) Remain constant
d) Vary non linearly
Answer: c
Explanation: The gain remains relatively constant for variations in the input and output levels.
11. In the below circuit of Common Source amplifier, the transistor M2 operates as:
vlsi-questions-answers-single-stage-amplifiers-q11
a) Load impedance
b) Voltage source
c) Current Source
d) None of the mentioned
Answer: c
Explanation: The transistor M2 operates as current source in Common source amplifier for providing large voltage gain.
12. The advantage of using source degeneration resistor in Common source amplifier is to provide:
a) Huge gain
b) Non Linearity behaviour of amplifier
c) Linearity behaviour of amplifier
d) Less gain
Answer: c
Explanation: Introducing degenerative resistor makes the amplifier to operate in linear condition.
13. The graph corresponding to Common source amplifier with source degeneration resistor is:
a) vlsi-questions-answers-single-stage-amplifiers-q13a
b) vlsi-questions-answers-single-stage-amplifiers-q13b
c) vlsi-questions-answers-single-stage-amplifiers-q13c
d) None of the mentioned
Answer: a
Explanation: Gain remains constant in source degeneration configuration.
14. In the below circuit if the current source is ideal, the voltage gain is:
vlsi-questions-answers-single-stage-amplifiers-q14
a) Av = -gm.Rs
b) Av = -Io.Rs
c) Av = -gm.Ron
d) None of the mentioned
Answer: c
Explanation: Since the current source is ideal, current through Rs cannot change and hence small signal voltage drop across it is zero, making the gain constant and depend on Ron.
15. The input output characteristic of common drain amplifier is:
a) vlsi-questions-answers-single-stage-amplifiers-q15a
b) vlsi-questions-answers-single-stage-amplifiers-q15b
c) vlsi-questions-answers-bicmos-logic-gates-q15c
d) All of the mentioned
Answer: a
Explanation: None.
This set of VLSI Multiple Choice Questions & Answers focuses on “Scaling Factors -1”.
1. Microelectronic technology cannot be characterized by
a) minimum feature size
b) power dissipation
c) production cost
d) designing cost
Answer: d
Explanation: Microelectronic technology can be characterized by minimum feature size, number of gates on one chip, power dissipation, die size, production cost, etc and not by designing cost.
2. Which model is used for scaling?
a) constant electric scaling
b) constant voltage scaling
c) costant electric and voltage scaling
d) costant current model
Answer: c
Explanation: Constant electric scaling model and constant voltage scaling model is used for scaling.
3. α is used for scaling
a) linear dimensions
b) vdd
c) oxide thickness
d) non linear
Answer: a
Explanation: α is used as the scaling factor for linear dimensions where as β is used for supply voltage Vdd, gate oxide thickness etc.
4. For constant voltage model,
a) α = β
b) α = 1
c) α = 1/β
d) β = 1
Answer: d
Explanation: For constant voltage model, β = 1 and 1/β is chosen for the scaling for all voltages.
5. For constant electric field model,
a) β = α
b) α = 1
c) α = 1/β
d) β = 1
Answer: a
Explanation: For constant voltage model, β = α.
6. Gate area can be given as
a) L/W
b) L * W
c) 2L/W
d) L/2W
Answer: b
Explanation: Gate area Ag can be given as the product of length and the width of the channel.
7. Gate area is scaled by
a) α
b) 1/α
c) 1/α 2
d) α 2
Answer: c
Explanation: Gate area is given as the product of length and width of the channel and it can be scaled by 1/α 2 .
8. Gate capacitance per unit area is scaled by
a) α
b) 1
c) 1/β
d) β
Answer: d
Explanation: Gate capacitance per unit area is scaled by β and this is given by €ox/D.
9. Parasitic capacitance is given by
a) Ax/d
b) Ax * d
c) d/Ax
d) Ax
Answer: a
Explanation: Parasitic capacitance is given by Ax/d where Ax is the area of the depletion region and d is the depletion width.
10. Parasitic capacitance is scaled by
a) β
b) 1/β
c) α
d) 1/α
Answer: d
Explanation: Parasitic capacitance is scaled by 1/α because area is scaled by 1/α 2 and d by 1/α. Thus (1/α 2 )/ we will get 1/α.
This set of VLSI Interview Questions and Answers for freshers focuses on “Scaling Factors -2”.
1. Carrier density is scaled by
a) α
b) β
c) 1
d) α 2
Answer: c
Explanation: Carrier density in channel Qon is scaled by 1. Carrier density is given by C0*Vgs where C0 is scaled by β and Vgs is scaled by 1/β.
2. Channel resistance Ron is scaled by
a) α
b) β
c) 1
d) α 2
Answer: c
Explanation: Channel resistance Ron is scaled by 1. Channel resistance is given by *µ.
3. Gate delay is given by
a) Ron/Cg
b) Ron * Cg
c) Cg/Ron
d) Cg 2 /Ron
Answer: b
Explanation: Gate delay Td is given as the product of Ron, channel resistance and Cg the gate capacitance.
4. Maximum operating frequency is scaled by
a) α/β
b) β/α
c) α 2 /β
d) β 2 /α
Answer: c
Explanation: Maximum operating frequency f0 is scaled by α 2 /β. This is given by *µ.
5. Saturation current is scaled by
a) α
b) β
c) 1/α
d) 1/β
Answer: d
Explanation: Saturation current Idss is scaled by 1/β. This is given by µ*W/L* 2 .
6. Vgs is scaled by
a) α
b) β
c) 1/α
d) 1/β
Answer: d
Explanation: Gate to source voltage Vgs is scaled by 1/β. All voltages are scaled by 1/β.
7. Current density J is scaled by
a) α/β
b) β/α
c) α 2 /β
d) β 2 /α
Answer: c
Explanation: Current density J is scaled by α^2/β. Current density is given by Idss/A where Idss is scaled by 1/β and area A by 1/α^2.
8. Power dissipation per gate is scaled by
a) 1/α
b) 1/β
c) 1/α 2
d) 1/β 2
Answer: d
Explanation: Power dissipation per gate is scaled by 1/β^2. This is the sum of static component Pgs and dynamic component Pgd.
9. Power dissipation per unit area is scaled by
a) 1/α
b) 1/β
c) β 2 /α 2
d) α 2 /β 2
Answer: d
Explanation: Power dissipation per unit area Pa is scaled by α 2 /β 2 . This is given by Pg/Ag where Pg is scaled by 1/β 2 and Ag by 1/α 2 .
10. In constant voltage model, the saturation current is scaled by
a) α
b) β
c) 1
d) β 2
Answer: c
Explanation: Saturation current is scaled by 1 in constant voltage model. This is because saturation current is scaled by 1/β and here in constant voltage model β is 1.
11. In constant field model, maximum operationg frequency is scaled by
a) α
b) β
c) α 2
d) β 2
Answer: a
Explanation: In constant field model, maximum operating frequency is scaled by α. Maximum operating frequency is scaled by α 2 /β and here in this model β = α.
12. In constant electric field model, power dissipation per unit area is scaled by
a) α
b) β
c) 1
d) β 2
Answer: c
Explanation: Power dissipation per unit area is scaled by 1 in constant electric field model. This is scaled by α 2 /β 2 and here in constant electric field model β = α.
This set of VLSI Multiple Choice Questions & Answers focuses on “Limitations of Scaling -1”.
1. Built-in junction potential Vb depends on
a) Vdd
b) Vgs
c) substrate doping level
d) oxide thickness
Answer: c
Explanation: Built-in junction potential Vb depends on the substrate doping level and this will be acceptable so long as Vb is small compared with Vdd.
2. As the channel length is reduced in a MOS transistor, depletion region width must be
a) increased
b) decreased
c) must not vary
d) exponentially decreased
Answer: b
Explanation: As the channel length is reduced in a MOS transistor, depletion width must also be scaled down to prevent the source and drain depletion regions from meeting.
3. Vdd is scaled by
a) α
b) β
c) 1/α
d) 1/β
Answer: d
Explanation: Supply voltage Vdd is scaled by 1/β. All voltages are scaled by 1/β.
4. If doping level of substrate Nb increases then depletion width
a) increases
b) decreases
c) does not change
d) increases and then decreases
Answer: b
Explanation: If the substrate doping length Nb increases then depletion width decreases because depletion width is inversely proportional to Nb.
5. Maximum electric field can be given as
a) V/d
b) d/V
c) 2V/d
d) d/2V
Answer: c
Explanation: Maximum electric field can be given by 2V/d and this is induced in one-sided step junction.
6. The size of a transistor is usually defined in terms of its
a) channel length
b) feature size
c) width
d) thickness ‘d’
Answer: a
Explanation: The size of a transistor is usually defined in terms of its channel length L because feature size only gives area capacitance etc.
7. What is the minimum value of L to maintain transistor action?
a) d
b) d/2
c) 2d
d) d 2
Answer: c
Explanation: The channel length L should be atleast 2d to maintain the transistor action and to prevent punch-through.
8. L depends on
a) substrate concentration
b) Vgs
c) Vt
d) Vds
Answer: a
Explanation: Channel length L depends on the supply voltage Vdd and substrate concentration Nb.
9. Drift velocity can be given as
a) E/µ
b) µ/E
c) µ * E
d) E
Answer: c
Explanation: Carrier drift velocity can be given as the product of µ and E and the maximum carrier drift velocity is approximately equal to Vsat regardless of the supply voltage.
10. The transit time can be given as
a) 2d
b) 2d/µE
c) µE/d
d) µE/2d
Answer: b
Explanation: The transit time can be given by L/Vdrift which is equivalent to 2d/µE as L = 2d and Vdrift is µE.
This set of VLSI Questions and Answers for Experienced people focuses on “Limitations of Scaling -2”.
1. Maximum transit time occurs when the size of the transistor is
a) minimum
b) maximum
c) does not depend on size
d) double
Answer: a
Explanation: Maximum transit time occurs when the size of the transistor is minimum when Va is approximately 0.
2. The spacing of interconnect is scaled by
a) α
b) 1/α
c) α 2
d) 1/α 2
Answer: b
Explanation: Spacing of interconnect, width and thickness are scaled by 1/α as they are linear dimensions.
3. Cross section area is scaled by
a) α
b) 1/α
c) α 2
d) 1/α 2
Answer: d
Explanation: Cross section area is scaled by 1/α 2 as area is the product of length and width which are scaled by 1/α.
4. The decrease in device dimension ______ the die size.
a) increases
b) decreases
c) does not affect
d) decreases and then increases
Answer: a
Explanation: The decrease in device dimension increases the die size and also the levels of integration.
5. The reduction in die size reduces
a) R
b) d
c) L
d) W
Answer: a
Explanation: The reduction in die size also reduces R and C. Die size depends on both resistor and capacitor.
6. The propogation delay along the optical fiber interconnect can be given as
a) n/Lx
b) nL/c
c) c/nL
d) nc/L
Answer: b
Explanation: The propogation delay along the optical fiber interconnect can be given as nL/c where n is the refractive index, L is the length of the fiber and c is the speed of light.
7. The breakdown voltage can be reduced by _____ electric field strength.
a) increasing
b) decreasing
c) does not depend
d) exponentially decreasing
Answer: a
Explanation: The increase in electric field strength lowers the breakdown voltages. Electric field is inversely proportional to the voltage.
8. Greater the switching speed _____ is the more.
a) low
b) more
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: Increase in switching speed increases the noise problems. Switching speed is the rate a which the logic level varies.
9. Substrate concentration is scaled by
a) α
b) 1/α
c) α 2
d) 1/α 2
Answer: a
Explanation: Substrate concentration Nb which gives the doping level of substrate is scaled by α.
10. The increase in operating frequency results in ______ in cross-talk noise.
a) increase
b) decrease
c) no change
d) doubling
Answer: a
Explanation: The increase in operating frequency and reduction in rise time tr results in the increase of cross-talk noise.
11. Flicker noise is scaled by
a) 1/α 2
b) α 2 /β 2
c) 1/β 2
d) β 2 /α 2
Answer: b
Explanation: Flicker noise occurs due to fluctuations of carriers trapped in the channel by surface states. It is scaled by α 2 /β 2 .
12. Scaling affects _____ generated noise.
a) internally
b) externally
c) internally and externally
d) does not generate
Answer: c
Explanation: Scaling affects both internally and externally generated noise and this degrades both the production yeild and the reliability of high density chip layouts.
This set of VLSI Multiple Choice Questions & Answers focuses on “MOS Circuit Scaling – 1”.
1. The basic figures of merit for MOS devices are
a) Minimum Feature size
b) Low Power dissipation
c) Maximum operational frequency
d) All of the mentioned
Answer: d
Explanation: All the mentioned are the basic figures of merit for MOS devices.
2. For the constant field model, the scaling factors β and α are related as:
a) β = α
b) α = 2β
c) β = 1
d) β = α = 0
Answer: a
Explanation: In Constant field model, β = α.
3. In Constant Voltage model, the scaling factors β and α are related as:
a) β = α
b) α = 2β
c) β = 1
d) β = α = 1
Answer: c
Explanation: In Constant Voltage model, β = 1.
4. The scaling factor for the supply voltage VDD is:
a) 1
b) 0
c) 1/α
d) 1/β
Answer: d
Explanation: The supply voltage VDD has the scaling factor of 1/β.
5. The scaling factor of length and width of the channel are:
a) 1, 1
b) 1/α, 1/β
c) 1/α, 1/α
d) 1/β, 1/β
Answer: c
Explanation: The scaling factor of length is 1/α, and scaling factor for width is 1/α.
6. The third type of scaling model is:
a) λ-based model
b) µm based model
c) combined voltage and dimension model
d) combined voltage and electric field model
Answer: c
Explanation: The third model is known as the combined voltage and dimensions model proposed by Bergmann in 1991.
7. The scaling factor of gate area in constant voltage model is:
a) 1/α 2
b) 1/β 2
c) 1
d) All of the mentioned
Answer: a
Explanation: The gate area = L.W, therefore scaling factor = 1/α 2 .
8. The scaling factor of Gate Capacitance per unit area is:
a) 1/β
b) 1/α
c) β
d) α
Answer: c
Explanation: Gate capacitance per unit area has the scaling factor of β.
9. The scaling factor of Gate capacitance is:
a) 1/β
b) 1/α
c) β/α 2
d) α/β 2
Answer: c
Explanation: The scaling factor of Gate capacitance is β/α 2 .
10. In Constant voltage model the gate capacitance is scaled by a factor of:
a) 1/β 2
b) 1/α 2
c) β/α 2
d) α/β 2
Answer: b
Explanation: Since β is 1.
11. The parasitic Capacitance has the scaling factor:
a) Equal to gate capacitance
b) 1/α 2
c) 1/α
d) 1/β
Answer: c
Explanation: Parasitic capacitance is scaled by 1/α.
12. The carrier density in channel in constant voltage model is scaled as:
a) 1/β
b) 1
c) β
d) All of the mentioned
Answer: d
Explanation: Carrier density is scaled as 1, since in constant voltage model β = 1, therefore all are correct.
13. Carrier density is measured as:
a) Average charge per unit area in the channel in ‘OFF’ state
b) Average charge per unit area in the channel in ‘ON’state
c) Average charge per unit area in the gate oxide
d) None of the mentioned
Answer: b
Explanation: Carrier density is the Average charge per unit area in the channel in ‘ON’ state.
14. Channel resistance is scaled as:
a) 1/α 2
b) 1/β
c) 1/α
d) 1
Answer: d
Explanation: Channel resistance is scaled by the factor of 1.
15. The scaling factor of Gate delay in Constant field model is:
a) 1/α 2
b) 1
c) 1/α
d) β/α
Answer: c
Explanation: In Constant field model the scaling factor of gate delay is 1/α.
This set of VLSI Multiple Choice Questions & Answers focuses on “MOS Circuit Scaling – 2”.
1. The gate delay is proportional to:
a) Ron .Cg
b) Rs.Cds
c) Rd.Cgs
d) Ron.Cox
Answer: a
Explanation: The gate delay is proportional to channel resistance and gate capacitance
2. The maximum operating frequency is scaled by:
a) 1/α 2
b) β/α 2
c) α 2 /β
d) 1
Answer: c
Explanation: Maximum operating frequency s inversely proportional to the gate delay. It is scaled by α 2 /β
3. The saturation current is scaled by the factor of:
a) 1
b) 1/α 2
c) 1/β
d) 1/α
Answer: c
Explanation: The saturation current is scaled by the factor of 1/β
4. The scaling factor of current density in constant voltage model is:
a) 1/α 2
b) 1
c) α 2
d) α 2 /β
Answer: c
Explanation: Current density is scaled by a factor of α 2 /β and since it is in Constant voltage model, β = 1, therefore α 2 is correct answer
5. Switching energy per gate is scaled by the factor of:
a) 1
b) α 2 /β
c) 1/ β.α 2
d) α 2
Answer: c
Explanation: Switching energy per gate is scaled by a factor of 1/ β.α 2
6. In Constant field model, the scaling factor of switching energy per gate would be:
a) 1/ β.α 2
b) 1/ α 3
c) 1/ α 2
d) All of the mentioned
Answer: b
Explanation: Since in constant field model α = β
7. The power dissipation per gate is scaled as:
a) 1
b) 1/ β.α 2
c) α 2 /β
d) 1/ β 2
Answer: d
Explanation: Power dissipation per gate is scaled by the factor of 1/β 2
8. The dynamic component of power dissipation is given by:
a) P = I 2 .Rd
b) P = Vdd 2 /Rd
c) P = Eg.fo
d) All of the mentioned
Answer: c
Explanation: The dynamic component is the product of energy per gate and maximum operating frequency.
9. The static component of power dsssipation is given by:
a) P = I 2 .Rd
b) P = Vdd 2 /Ron
c) P = Eg.fo
d) All of the mentioned
Answer: b
Explanation: The static component is the power dissipated across transistor when it is in ON state
10. The scaling factor of power dissipation per unit area is:
a) 1
b) 1/α 2
c) 1/ β.α 2
d) α 2 /β 2
Answer: d
Explanation: The scaling factor of power dissipation per unit area is α 2 /β 2
11. The power speed product has the scaling factor of:
a) 1
b) 1/α 2
c) 1/ β.α 2
d) None of the mentioned
Answer: c
Explanation: The power speed product has the scaling factor of 1/ β.α 2
12. The scaling factor of power dissipation per unit area in constant field model is:
a) 1
b) 1/α 2
c) 1/ β.α 2
d) α 2 /β 2
Answer: a
Explanation: In constant field model α = β
13. The scaling factor of Logic Level 1 in constant field model is:
a) 1
b) 1/β
c) 1/α
d) α/β
Answer: c
Explanation: The logic level 1 is scaled as 1/β. Since we are using constant field model, the scaling factor will be 1/α
14. The scaling factor similar to scaling factor of power speed product is:
a) Power dissipation per unit area
b) Switching Energy
c) Power dissipation per gate
d) All of the mentioned
Answer: b
Explanation: Switching energy has the same scaling factor as that of power speed products.
15. The parameter which is not scaled to any factor is:
a) Power speed product
b) Switching energy
c) Channel resistance
d) All of the mentioned
Answer: c
Explanation: Channel resistance is scaled by 1. Therefore there are no factors like α or β.
This set of VLSI Multiple Choice Questions & Answers focuses on “Switch Logic”.
1. The subsystem of the circuits should have ______ interdependence.
a) minimum
b) maximum
c) no
d) more
Answer: a
Explanation: The subsystem of the circuit or system to be designed should have minimum interdependence and complexity.
2. Switch logic is based on
a) pass transistors
b) transmission gates
c) pass transistors and transmission gates
d) design rules
Answer: c
Explanation: Switch logic is based on pass transistors or transmission gates. Pass transistor describes several logic families used in the design of integrated circuits. This logic reduces the count of transistors used to make different logic gates, by eliminating redundant transistors.
3. The switch logic approach takes _____ static current.
a) low
b) more
c) no
d) very less
Answer: c
Explanation: The switch logic approach takes no static current from the supply rails and is faster for small arrays.
4. Power dissipation in switch logic is
a) less
b) more
c) high
d) very less
Answer: a
Explanation: Power dissipation is small in switch logic approach since current only flows on switching.
5. Features of switch logic approach
a) occupies more area
b) no undesirable threshold voltage
c) low power dissipation
d) all of the mentioned
Answer: d
Explanation: Some of the features of switch logic approach are that it occupies more area, eliminates undesirable threshold voltage and has low power dissipation.
6. Pass transistor can be driven through _____ pass transistors.
a) one
b) no
c) more
d) two
Answer: b
Explanation: Pass transistor input should not be driven through any other pass transistors because there occurs loss in logic levels.
7. Basic AND and OR gate combinations are used in switch logic.
a) true
b) false
Answer: a
Explanation: Basic AND and OR combination of switches are possible and are used in switch logic. It is simple to design and easier.
8. When one pass transistor is driven using another, threshold voltage
a) affects
b) does not affect
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: When logic levels are propogated through pass transistors are degraded by threshold voltage.
9. Switch logic approach is fast for
a) large arrays
b) small arrays
c) very large arrays
d) not at all fast for any type
Answer: b
Explanation: Switch logic approach is fast for smaller arrays and as the arrays becomes larger more switches and gates are requires which makes it a bit slower and complex.
10. Switch logic is designed using
a) complementary switches
b) silicon plates
c) conductors
d) resistors
Answer: a
Explanation: Switch logic is designed using n or p pass transistors or from complementary switches.
This set of VLSI Multiple Choice Questions & Answers focuses on “Gate Logic”.
1. Gate logic is also called as
a) transistor logic
b) switch logic
c) complementary logic
d) restoring logic
Answer: d
Explanation: Gate logic is also called as restoring logic. This is a logic circuitry designed so that even with an imperfect input pulse a standard output occurs at the exit of each successive logic gate.
2. Both NAND and NOR gates can be used in gate logic.
a) true
b) false
Answer: a
Explanation: Both NAND and NOR gates can be used in gate logic along with CMOS and AND and OR logic can be used in switch logic.
3. The CMOS inverter has _____ power dissipation.
a) low
b) more
c) no
d) very less
Answer: c
Explanation: The CMOS inverter has no static current and no power dissipation. Static charge remains until it is able to move away by means of electric discharge.
4. As the number of inputs increases, the NAND gate delay
a) increases
b) decreases
c) does not vary
d) exponentially decreases
Answer: a
Explanation: As the number of inputs increases, the NAND gate delay also increases because computation considering or using each input additional time is needed.
5. NAND gate delay can be given as
a) Ʈint
b) Ʈint/n
c) n*Ʈint
d) 2n*Ʈint
Answer: c
Explanation: NAND gate delay can be given as the product of number of inputs n and the nMOS inverter delay Ʈint.
6. In CMOS NAND gate, p transistors are connected in
a) series
b) parallel
c) cascade
d) random
Answer: b
Explanation: In CMOS NAND gate, p transistors are connected in parallel but once again the geometries may require thought when several inputs are required.
7. BiCMOS is used for ____ fan-out.
a) less
b) more
c) no
d) very less
Answer: b
Explanation: BiCMOS NAND can be used when large fan-out is necessary. Fan-out is a term that defines the maximum number of digital inputs that the output of a single logic gate can feed.
8. Which can handle high capacitance load?
a) NAND
b) nMOS NAND
c) CMOS NAND
d) BiCMOS NAND
Answer: d
Explanation: BiCMOS NAND can handle high capacitance load. It is more complex and it can handle high capacitance load such as in the I/O region of a chip.
9. Which gate is faster?
a) AND
b) NAND
c) NOR
d) OR
Answer: c
Explanation: NOR gate is faster. NAND is more complex than NOR and thus NOR is faster and efficient.
10. For a pseudo nMOS design the impedance of pull up and pull down ratio is
a) 4:1
b) 1:4
c) 3:1
d) 1:3
Answer: c
Explanation: For a pseudo nMOS design, the ratio of Zp.u. and Zp.d. is 3:1.
This set of VLSI Multiple Choice Questions & Answers focuses on “CMOS Logics”.
1. In Pseudo-nMOS logic, n transistor operates in
a) cut off region
b) saturation region
c) resistive region
d) non saturation region
Answer: b
Explanation: In Pseudo-nMOS logic, n transistor operates in a saturation region and p transistor operates in resistive region.
2. The power dissipation in Pseudo-nMOS is reduced to about ________ compared to nMOS device.
a) 50%
b) 30%
c) 60%
d) 70%
Answer: c
Explanation: The power dissipation in Pseudo-nMOS is reduced to about 60% compared to nMOS device.
3. Pseudo-nMOS has higher pull-up resistance than nMOS device.
a) true
b) false
Answer: a
Explanation: Pseudo-nMOS has higher pull-up resistance than nMOS device and thus inverter pair delay is larger.
4. In dynamic CMOS logic _____ is used.
a) two phase clock
b) three phase clock
c) one phase clock
d) four phase clock
Answer: d
Explanation: In dynamic CMOS logic, four phase clock is used in which actual signals are used to derive the clocks.
5. In clocked CMOS logic, output in evaluated in
a) on period
b) off period
c) both periods
d) half of on period
Answer: a
Explanation: In clocked CMOS logic, the logic is evaluated only in the on period of the clock. And owing to the extra transistor in series, slower rise time and fall times are expected.
6. In clocked CMOS logic, rise time and fall time are
a) faster
b) slower
c) faster first and then slows down
d) slower first and then speeds up
Answer: b
Explanation: In clocked CMOS logic, rise time and fall time are slower because of more number of transistors in series.
7. In CMOS domino logic _____ is used.
a) two phase clock
b) three phase clock
c) one phase clock
d) four phase clock
Answer: c
Explanation: In CMOS domino logic, single phase clock is used. Clock signals distributed on one wire is called as single or one phase clock.
8. CMOS domino logic is same as ______ with inverter at the output line.
a) clocked CMOS logic
b) dynamic CMOS logic
c) gate logic
d) switch logic
Answer: b
Explanation: CMOS domino logic is same as that of the dynamic CMOS logic with inverter at the output line.
9. CMOS domino logic occupies
a) smaller area
b) larger area
c) smaller & larger area
d) none of the mentioned
Answer: a
Explanation: CMOS domino logic structure occupies smaller area than conventional CMOS logic as only n-block is used.
10. CMOS domino logic has
a) smaller parasitic capacitance
b) larger parasitic capacitance
c) low operating speed
d) very large parasitic capacitance
Answer: a
Explanation: CMOS domino logic has smaller parasitic capacitance and higher operating speed.
11. In CMOS domino logic _______ is possible.
a) inverting structure
b) non inverting structure
c) inverting and non inverting structure
d) very complex design
Answer: b
Explanation: In CMOS domino logic, only non inverting structures are possible because of the presence of the inverting buffer.
12. CMOS domino logic can be expressed diagramatically as
a) vlsi-questions-answers-cmos-logics-q12a
b) vlsi-questions-answers-cmos-logics-q12b
c) vlsi-questions-answers-cmos-logics-q12c
d) vlsi-questions-answers-cmos-logics-q12d
Answer: a
Explanation: The correct form of CMOS domino logic representation is as given in the answer.
This set of VLSI Multiple Choice Questions & Answers focuses on “Clocked Sequential Circuits”.
1. Clocked sequential circuits are
a) two phase overlapping clock
b) two phase non overlapping clock
c) four phase overlapping clock
d) four phase non overlapping clock
Answer: b
Explanation: Clocked sequential circuits are two phase non overlapping clock signals. Clock signals are distributed in two wires and it is non overlapping.
2. Which are easier to design?
a) clocked circuits
b) asynchronous sequential circuits
c) clocked circuits with buffer
d) asynchronous sequential circuits with buffers
Answer: a
Explanation: Clocked circuitry are easier to design than the asynchronous sequential circuits. But it is slower than the asynchronous sequential circuit.
3. ___________ is used to drive high capacitance load.
a) single polar capability
b) bipolar capability
c) tripolar capability
d) bi and tri polar capability
Answer: b
Explanation: Bipolar capability is used to drive high capacitance load. It can handle high loads as it is done by BiCMOS NAND gate logic.
4. As the temperature is increased, storage time ____________
a) halved
b) doubled
c) does not change
d) tripled
Answer: a
Explanation: As the temperature is increased, storage time is halved. It is inversely proportional to the storage time.
5. Inverting dynamic register element consists of __________ transistors for nMOS and _________ for CMOS.
a) two, three
b) three, two
c) three, four
d) four, three
Answer: c
Explanation: Dynamic register element consists of three transistors for nMOS and four for CMOS.
6. Non inverting dynamic register storage cell consists of _________ transistors for nMOS and _________ for CMOS.
a) six, eight
b) eight, six
c) five, six
d) six, five
Answer: a
Explanation: Non inverting dynamic register storage cell consists of six transistors for nMOS and eight for CMOS.
7. Register cell consists of
a) inverter
b) pass transistor
c) inverter & pass transistor
d) none of the mentioned
Answer: c
Explanation: Register cell consists of an inverter and a pass transistor or a transmission gate. Dynamic register cell consists of stick/circuit notation.
8. In a four bit dynamic shift register basic nMOS transistor or inverters are connected in
a) series
b) cascade
c) parallel
d) series and parallel
Answer: b
Explanation: The basic inverters or nMOS transistors are connected in cascade to obtain four bit dynamic shift register.
9. In four bit dynamic shift register output is obtained
a) parallel output at inverters 1, 3, 5, 7
b) parallel output at inverters 1, 5, 8
c) parallel output at all inverters
d) parallel output at inverter 2, 4, 6, 8
Answer: d
Explanation: In four bit dynamic shift register, output is obtained parallelly at inverters 2, 4, 6, 8.
10. For signals which are updated frequently _____ is used.
a) static storage
b) dynamic storage
c) static and dynamic storage
d) buffer
Answer: b
Explanation: For signals which are updated frequently dynamic storage elements are used. It can be done at < 0.25 msec interval.
This set of VLSI Multiple Choice Questions & Answers focuses on “System Considerations”.
1. Clock line drivers has ____________ source of drive.
a) one
b) two
c) three
d) none
Answer: a
Explanation: Clock line drivers have one source of drive. The speed of bipolar drivers is not fully realized with bus lines.
2. Bus structures carry ____________
a) data signals
b) control signals
c) data and control signals
d) in and out signals
Answer: c
Explanation: Bus structures carry both data and control signals. They are generally long and connected to and through a significant number of circuits and subsystems.
3. Bus has _______ different classes.
a) two
b) three
c) four
d) five
Answer: b
Explanation: Bus has three different classes and those are passive, active and precharged.
4. In passive bus, drivers are connected through
a) series switches
b) parallel switches
c) cascade switches
d) wires
Answer: a
Explanation: In passive bus, drivers are connected through series switches. It is a floating rail to which signals may be connected from drivers through series switches.
5. The bus rail in active bus has ________
a) NAND connection
b) AND connection
c) NOR connection
d) OR connection
Answer: c
Explanation: The bus rail in active bus has NOR connection which has a common pull up and ntype pull down transistors.
6. Low L:W ratio results in ____ transistors.
a) smaller
b) bigger
c) size doesnt depend on ratio
d) less effective
Answer: b
Explanation: The size of the transistor can be made large by small L:W ratio and thus it has a low resistance.
7. Features which does not affect bus design are ________
a) cross-talk
b) delay factors
c) non delay factors
d) cross talk and delay factors
Answer: c
Explanation: Cross-talk and delay factors are of significance in bus design. This occurs when many signals on chip is propogated.
8. Which device is frequency dependent?
a) nMOS
b) CMOS
c) BiCMOS
d) pMOS
Answer: b
Explanation: CMOS is frequency dependent where as BiCMOS is not and it exhibits constant value for power dissipation.
9. If the current density exceeds a threshold value then metal atoms moves in
a) direction of the current
b) opposite direction of the current
c) doesnt depend on direction of current
d) direction of the voltage
Answer: a
Explanation: If the current density exceeds a threshold value then metal atoms starts to move in the direction of current.
10. At narrowing or constriction point current density is ________
a) minimum
b) maximum
c) remains low after going to high point
d) becomes high from low
Answer: b
Explanation: At narrowing or constriction point, current density is at its highest. At these points, metal is transported from the constricted regions become even more constricted and eventually may blow like a fuse.
11. During relaxation effect, electron flow occurs in
a) short pulses
b) at steady state level
c) large pulses
d) very large pulses
Answer: a
Explanation: During relaxation effect, electron flow occurs in short pulses rather than at steady state level.
12. Line impedance is given by
a) 2
b) 2
c) 1/2
d) 1/2
Answer: c
Explanation: The line impedance Zo is given by 1/2 where L and C are values per unit length of the bus.
13. IR drops brings ______ in noise margin.
a) increase
b) decrease
c) does not affect
d) stabilisation
Answer: b
Explanation: IR drops bring about deterioration in noise margins. Transient voltages induced in either Vdd or Vss rail may lead to noise margin problems.
This set of VLSI Multiple Choice Questions & Answers focuses on “CMOS Logic Gates”.
1. In negative logic convention, the Boolean Logic [1] is equivalent to:
a) +VDD
b) 0 V
c) -VDD
d) None of the mentioned
Answer: b
Explanation: In negative logic convention, the Boolean Logic [1] is equivalent to 0 V and Logic ‘0’ is equivalent to +VDD.
2. In positive logic convention, the true state is represented as:
a) 1
b) 0
c) -1
d) -0
Answer: a
Explanation: In positive logic convention, the Boolean logic ‘1’ is known to be representing true state.
3. The CMOS gate circuit of NOT gate is:
a) vlsi-questions-answers-cmos-logic-gates-q3a
b) vlsi-questions-answers-cmos-logic-gates-q3b
c) vlsi-questions-answers-cmos-logic-gates-q3c
d) vlsi-questions-answers-cmos-logic-gates-q3d
Answer: d
Explanation: The CMOS logic circuit for NOT gate has a p-MOS as a pull up transistor and n-MOS as driver transistor which is represented accurately in the below figure vlsi-questions-answers-cmos-logic-gates-q3d
4. The truth table which accurately explains the operation of CMOS not gate is:
a) vlsi-questions-answers-cmos-logic-gates-q4a
b) vlsi-questions-answers-cmos-logic-gates-q4b
c) vlsi-questions-answers-cmos-logic-gates-q4c
d) vlsi-questions-answers-cmos-logic-gates-q4d
Answer: d
Explanation: The output of CMOS depends on the state of nMOS and pMOS transistor.The correct truth table is: vlsi-questions-answers-cmos-logic-gates-q4d
5. The CMOS logic circuit for NAND gate is:
a) vlsi-questions-answers-cmos-logic-gates-q5a
b) vlsi-questions-answers-cmos-logic-gates-q5b
c) vlsi-questions-answers-cmos-logic-gates-q5c
d) None of the mentioned
Answer: a
Explanation: The accurate cmos logic circuit for NAND gate is: vlsi-questions-answers-cmos-logic-gates-q5a
6. In CMOS logic circuit the n-MOS transistor acts as:
a) Load
b) Pull up network
c) Pull down network
d) Not used in CMOS circuits
Answer: c
Explanation: A static CMOS gate has an nMOS pull-down network to connect the output to 0 .
7. In CMOS logic circuit the p-MOS transistor acts as:
a) Pull down network
b) Pull up network
c) Load
d) Short to ground
Answer: b
Explanation: A static CMOS gate has a pMOS pull-up network to connect the output to VDD .
8. In CMOS logic circuit, the switching operation occurs because:
a) Both n-MOSFET and p-MOSFET turns OFF simultaneously for input ‘0’ and turns ON simultaneously for input ‘1’
b) Both n-MOSFET and p-MOSFET turns ON simultaneously for input ‘0’ and turns OFF simultaneously for input ‘1’
c) N-MOSFET transistor turns ON, and p-MOSFET transistor turns OFF for input ‘1’ and N-MOS transistor turns OFF, and p-MOS transistor turns ON for input ‘0’
d) None of the mentioned
Answer: c
Explanation: In CMOS logic circuit, the switching operation occurs because N-MOS transistor turns ON, and p-MOS transistor turns OFF for input ‘1’ and N-MOS transistor turns OFF, and p-MOS transistor turns ON for input ‘0’. The networks are arranged such that one is ON and the other OFF for any input pattern.
9. The CMOS logic circuit for NOR gate is:
a) vlsi-questions-answers-cmos-logic-gates-q9a
b) vlsi-questions-answers-cmos-logic-gates-q9b
c) vlsi-questions-answers-cmos-logic-gates-q9c
d) vlsi-questions-answers-cmos-logic-gates-q9d
Answer: a
Explanation: vlsi-questions-answers-cmos-logic-gates-q9a
10. When both nMOS and pMOS transistors of CMOS logic design are in OFF condition, the output is:
a) 1 or Vdd or HIGH state
b) 0 or ground or LOW state
c) High impedance or floating
d) None of the mentioned
Answer: c
Explanation: When both pull up and pull down transistors are OFF, the high impedance for floating Z output state results.
11. When both nMOS and pMOS transistors of CMOS logic gates are ON, the output is:
a) 1 or Vdd or HIGH state
b) 0 or ground or LOW state
c) Crowbarred or Contention
d) None of the mentioned
Answer: c
Explanation: The crowbarred X level exists when both pull up and pull down transistors are simultaneously turned ON. Contention between the two networks results in an indeterminate output level and dissipates static power.
This set of VLSI Multiple Choice Questions & Answers focuses on “Phase Lock Loop”.
1. The PLL device is:
a) Feedback system that compares output frequency and input frequency
b) Feedback system that compares output phase and input phase
c) Linear system that compares output resistance and input resistance
d) Non Linear system that compares output current and input current
Answer: b
Explanation: The PLL device is a feedback system that compares output phase and input phase.
2. The Logic gate that works similar to phase detector is:
a) AND gate
b) OR gate
c) XOR gate
d) NOT gate
Answer: c
Explanation: 2 input XOR gate works similar to Phase detector.
3. What is the input at the phase detector?
vlsi-questions-answers-phase-lock-loops-q3
a) V1 – V2
b) Phase + Phase
c) Phase – Phase
d) V1 + V2
Answer: c
Explanation: None.
4. What is the relation between input and output in the following circuit?
vlsi-questions-answers-phase-lock-loops-q3
a) Exponential
b) Linear
c) Sinusoidal
d) None of the mentioned
Answer: b
Explanation: None.
5. The correct input output waveform when the phase difference between 2 input voltages is 90 degrees
vlsi-questions-answers-phase-lock-loops-q5
a) vlsi-questions-answers-phase-lock-loops-q5a
b) vlsi-questions-answers-phase-lock-loops-q5b
c) vlsi-questions-answers-phase-lock-loops-q5c
d) vlsi-questions-answers-phase-lock-loops-q5d
Answer: b
Explanation: None.
6. The aligning of output phase of voltage controlled oscillator with reference is called:
a) Phase compensation
b) Phase alignment
c) Phase Locking
d) Phase detecting
Answer: c
Explanation: The aligning of output phase of voltage controlled oscillator with reference is called Phase Locking.
7. The block diagram of basic PLL consists of:
a) vlsi-questions-answers-phase-lock-loops-q3
b) vlsi-questions-answers-phase-lock-loops-q7b
c) vlsi-questions-answers-phase-lock-loops-q7c
d) None of the Mentioned
Answer: c
Explanation: None.
8. What is the function of LPF in the following block diagram?
vlsi-questions-answers-phase-lock-loops-q7c
a) Suppress high frequency components of VCO output and presenting low frequency AC signal to PD
b) Suppress high frequency components of PD output and presenting low frequency AC signal to VCO
c) Suppress high frequency components of PD output and presenting DC signal to VCO
d) None of the mentioned
Answer: c
Explanation: The function of LPF in PLL is to suppress high frequency components of PD output and presenting DC signal to VCO.
9. Instead of Phase detection, if Frequency detector is used the drawback PLL would face is:
a) Finite difference between input and output frequency
b) Equality cannot be established if PLL compared input and output frequency rather than pulses
c) Error between Vin and Vout cannot be removed
d) All of the mentioned
Answer: d
Explanation: None.
10. If the input of type 1 PLL is a frequency step of Δw at t = 0, the change in phase at t = infinity is:
a) Δw
b) Δw/Kpd
c) Δw/Kpd.Kvco
d) None of the mentioned
Answer: c
Explanation: None.
11. The correct input-output waveforms of Frequency detector:
a) vlsi-questions-answers-phase-lock-loops-q11a
b) vlsi-questions-answers-phase-lock-loops-q11b
c) vlsi-questions-answers-phase-lock-loops-q11c
d) vlsi-questions-answers-phase-lock-loops-q11d
Answer: b
Explanation: None.
12. The D Flip Flop implementation for PFD is:
a) vlsi-questions-answers-phase-lock-loops-q12a
b) vlsi-questions-answers-phase-lock-loops-q12b
c) vlsi-questions-answers-phase-lock-loops-q12c
d) None of the mentioned
Answer: c
Explanation: None.
13. If high pass filter is used instead of Low pass filter in the PLL the response of PLL would be:
a) Output Voltage is not a square wave
b) Output Voltage contains many high frequency waves
c) VCO will be unstable due to variations in control voltage
d) All of the mentioned
Answer: b
Explanation: None.
14. Number of poles in Type 1 PLL is:
a) 0
b) 1
c) 2
d) None of the mentioned
Answer: c
Explanation: None.
15. The transfer function of PD is :
a) Constant
b) Varies with frequency
c) Varies with voltage
d) None of the Mentioned
Answer: a
Explanation: None.
This set of VLSI Multiple Choice Questions & Answers focuses on “Design Processes”.
1. Microprocessor has __________ major architectural blocks.
a) two
b) three
c) four
d) five
Answer: c
Explanation: MIcropocessor has four major architectural blocks – ALU, control unit, I/O unit and memory.
2. High level of system integration __________ interconnections.
a) reduces
b) increases
c) does not affect
d) doubles
Answer: a
Explanation: High level of system integration usually greatly reduces interconnections which is a weak spot in any system.
3. Some important features of system are
a) lower weight
b) lower volume
c) lower power dissipation
d) all of the mentioned
Answer: d
Explanation: Lower power dissipation, lower weight, lower volume are some of the important features of system.
4. Performance is better if power speed product is
a) low
b) high
c) very low
d) very high
Answer: b
Explanation: Performance is better if power speed product is high. Performance is analysed using this speed power product.
5. VLSI design is done in _________ approach.
a) top-down
b) bottom-up
c) random
d) semi random
Answer: a
Explanation: VLSI design is done in top-down manner with adequate computer aided tools to do the job. Partitioning, generating or building and verification is done.
6. Components operating in high frequency should be
a) far apart
b) closely spaced
c) randomly spaced
d) can be placed in straight manner
Answer: b
Explanation: Components operating in high frequency should be at physically proximate, since one may pay severe penalties for long, high bandwidth interconnects.
7. Approach used for design process are
a) circuit symbols
b) logic symbols
c) stick diagrams
d) all of the mentioned
Answer: d
Explanation: Several approaches used for design process are conventional circuit symbols, logic symbols, stick diagrams, mask layouts, architectural block diagrams and floor plans.
8. Which approach is used to show the relative disposition of subunits?
a) architectural block diagram
b) stick diagram
c) layout diagram
d) floor plan
Answer: d
Explanation: Floor plan is used to show the planned relative disposition of the subunits on the chip and thus on mask layouts.
9. When polysilicon crosses a diffusion __________ will be formed.
a) via
b) transistor
c) switch
d) short circuit
Answer: b
Explanation: When and where ever the polysilicon crosses the diffusion, transistor will be formed.
10. Two metal layers can be joined by using
a) contact cut
b) wire
c) via
d) glass
Answer: c
Explanation: The first metal layer can be joined with the second one using via. Via is an electrical connection between layers in a physical electronic circuit.
11. The bottom subfunction is called as
a) lower function
b) low cell
c) leaf cell
d) bottom cell
Answer: c
Explanation: The complex function is divided into many subfunctions and the bottom level of these sub functions are called as leaf cells.
12. Which must be given the highest priority in design process?
a) architecture
b) communication
c) colour
d) thickness
Answer: b
Explanation: Communication must be given highest priority in the design process as interconnections pose the most acute problems in the design of large systems.
This set of VLSI Multiple Choice Questions & Answers focuses on “Design of ALU Subsystem “.
1. Design gives a detailed
a) logic circuit design
b) topology of communication
c) colour codes of the layers
d) functions of layers
Answer: b
Explanation: Design is largely a matter of topology of communication rather than the detailed logic circuit design.
2. To minimize the design effort, regularity should be
a) low
b) high
c) very low
d) very high
Answer: b
Explanation: Regularity is a qualitative parameter and it should be high as possible to minimize the design effort required for any system.
3. Regularity is the ratio of
a) total transistors in the chip to total transistors that must be designed in detail
b) total transistors that must be designed in detail to total transistors in a chip
c) total transistors to total components
d) total charge storage components to charge dissipating components
Answer: a
Explanation: Regularity is the ratio of total transistors in the chip to total transistors that must be designed in detail.
4. Good design system has regularity in the range of
a) 25-50
b) 50-75
c) 50-100
d) 25-50
Answer: c
Explanation: Good design system must have regularity in the range of 50 to 100 or more and regular structures such as memories achieve very high figures.
5. In the adder, sum is stored in
a) series
b) cascade
c) parallel
d) registers
Answer: c
Explanation: The sum is stored in parallel at the output of the adder from where it may be fed through the shifter and back to the register array.
6. The shifter must be connected to
a) 2-shift data line
b) 2-shift control line
c) 4-shift data line
d) 4-shift control line
Answer: d
Explanation: The shifter is unclocked but must be connected to 4 shift control lines. Carry out and Carry in signal must also be connected.
7. What is the sum and carry if the two bit number is 1 1 and the previous carry is 0?
a) 0, 0
b) 0, 1
c) 1, 0
d) 1, 1
Answer: b
Explanation: If the two bit number is 1 1 and the previous carry is 0 the sum is 0 and carry is 1. This can be obtained by first adding the two numbers 1 and 1. Sum will be 0 and carry is 1. Later add the previous carry 0 to it. Now the sum is finally 0 and final carry will be 1.
8. Which design is preferred in n-bit adder?
a) many pass transistors in series
b) many pass transistors with suitable buffer
c) many pass transistors without suitable buffer
d) many pass transistors in parallel
Answer: b
Explanation: In n-bit adder, n adder elements must be cascaded with carry out connecting to carry in. This carry chain will have more pass transistors connected in series which will give slow response. Thus suitable buffer can be used in between.
9. In adders, the previous carry can also be given by
a) propagate signal pk
b) generate signal gk
c) pk and gk
d) sk
Answer: c
Explanation: In adders, the previous carry signal can also be given using propagate signal pk which is ex-or of two bits ak and bk and also using generate signal gk which is ‘and’ of ak and bk.
10. Adder using _______ technology can be used for speed improvement.
a) CMOS
b) BiCMOS
c) nMOS
d) pMOS
Answer: b
Explanation: Using BiCMOS technology, speed improvement can be obtained by a factor of two over CMOS technology. This arrangement works will lower input voltage swings to achieve higher speed.
11. For carry skip adder, the minimum total propogation delay can be obtained when m is
a) sqrt
b) sqrt
c) sqrt
d) sqrt
Answer: b
Explanation: For carry skip adder the total propogation delay T is given by 2-1)k1 + k2. The minimum value of T can be obtained when m is sqrt.
12. Multiple output domino logic has
a) two cell manchester carry chain
b) three cell manchester carry chain
c) four cell manchester carry chain
d) four cell manchester carry look ahead
Answer: c
Explanation: To reduce the complexity of the carry look ahead adder, a dynamic logic technique called multiple output domino logic is used. This approach consists of four cell manchester carry chain.
This set of VLSI Multiple Choice Questions & Answers focuses on “Multiplier Systems”.
1. Multipliers are built using
a) binary adders
b) binary subtractors
c) dividers
d) multiplexers
Answer: a
Explanation: A multiplier is an electronic circuit used to multiply two bianry numbers. It is built using binary adders that are full adders.
2. Which method uses reduced number of partial products?
a) Baugh-wooley algorithm
b) Wallace trees
c) Dadda multipliers
d) Modified booth encoding
Answer: d
Explanation: Multiplication in multipliers is done by obtaining partial products and then summing it up. Modified booth encoding reduces the number of partial products that must be summed.
3. Which method is easier to manipulate accumulator content?
a) left shifting
b) right shifting
c) serial shifting
d) parallel shifting
Answer: b
Explanation: It is easier to right shift the contents of the accumulator than to left shift. This can be used to eliminate the least significant bits of the product.
4. Which multiplier is very well suited for twos-complement numbers?
a) Baugh-wooley algorithm
b) Wallace trees
c) Dadda multipliers
d) Modified booth encoding
Answer: a
Explanation: Baugh-wooley method is used to design multipliers that are regular in structure and is very well suited for twos complement numbers.
5. What is the delay required to perform a single operation in a pipelined structure?
a) 2n
b) 3n
c) 4n
d) n
Answer: b
Explanation: The delay of one operation through the pipeline is 3n that is it takes 3n clock cycles to obtain a product after X and Y are input.
6. Latches choosen are
a) static shift registers
b) any flipflop
c) dynamic shift register
d) multiplexers
Answer: c
Explanation: The latches choosen are dynamic shift register as the structure will be continuously clocked.
7. Which method reduces number of cycles of operation?
a) Baugh-wooley algorithm
b) Wallace trees
c) Dadda multipliers
d) Modified booth encoding
Answer: d
Explanation: Modified booth encoding algorithm avoids many idle cells in a cellular multiplier as well as reduces the number of cycles compared with the serial-parallel multiplier.
8. The completion time for multiplication time in baugh-wooley method is
a) n
b) 2n
c) 3n
d) 4n
Answer: b
Explanation: The completion time for multiplication in Braun or Baugh-wooley is proportional to 2n where as completion time in Wallace tree method is proportional to log.
9. In which method minimum number of adder cells are used?
a) Baugh-wooley algorithm
b) Wallace trees
c) Dadda multipliers
d) Modified booth encoding
Answer: c
Explanation: Dadda multipliers are similar to Wallace trees but it has a reduced number of adder cells. This is a technique developed from Wallace tree but with an improvement.
10. Which method is suitable for larger operands?
a) Baugh-wooley algorithm
b) Wallace trees
c) Dadda multipliers
d) Modified booth encoding
Answer: b
Explanation: Wallace tree multipliers should be used for larger operands and where the performance is critical.
This set of VLSI Multiple Choice Questions & Answers focuses on “Storage Elements-1”.
1. Which clock is preferred in storage devices?
a) single phase overlapping clock signal
b) single phase non overlapping clock signal
c) two phase overlapping clock signal
d) two phase non overlapping clock signal
Answer: d
Explanation: Two phase non-overlapping clock signal is easily available and works better and effectively and this clock will be used throughout storage system.
2. Clock signal Φ2 is to
a) write data
b) read data
c) refresh data
d) store data
Answer: c
Explanation: Bits or data written into storage elements may be assumed to be settled before the immediately following signal Φ2 refreshes stored data where appropriate.
3. Data is read
a) before Φ1
b) after Φ1
c) before Φ2
d) after Φ2
Answer: b
Explanation: Bits or data may be read from storage elements on the next of Φ1 clock signal that is read signals RD are Anded with Φ1.
4. Factor for assessment of storage elements are
a) volatility
b) non volatility
c) number of bits
d) data repeatability
Answer: a
Explanation: Some of the comparative assessment factor for storage elements are area requirement, estimated dissipation per bit stored and volatility.
5. Which occupies lesser area?
a) nMOS
b) pMOS
c) CMOS
d) BiCMOS
Answer: a
Explanation: nMOS design with buried contacts needs lesser area than CMOS design and this can be estimated by calculating space stored by each bit in register cell.
6. In which design, dissipation is less?
a) nMOS
b) pMOS
c) CMOS
d) BiCMOS
Answer: c
Explanation: In CMOS design, static dissipation is very small since only the switching dissipation will be significant particularly at high speeds.
7. The impedance of pull down transistor in nMOS can be given as
a) 2Rs
b) 4Rs
c) 1/2 Rs
d) 1/4 Rs
Answer: c
Explanation: Each inverter stage has 8:1 ratio and in nMOS register cell, atleast one inverter should always be on and Zp.u. is given as 4Rs and Zp.d. is given as 1/2Rs.
8. Data storage time is
a) 1 milli second
b) 1 second
c) 1 minute
d) 10 seconds
Answer: a
Explanation: Data is stored by the charge on the gate capacitance of each inverter stage, so that data storage time is limited to 1 msec or less.
9. A bit is read at T1 when
a) RD is low, WR is low
b) RD is high, WR is low
c) RD is low, WR is high
d) RD is high, WR is high
Answer: c
Explanation: With RD control line low, a bit can be read through clock period T1 when WR is made high. After reading the bit WR is made low.
10. A bit can be stored when
a) RD is low, WR is low
b) RD is high, WR is low
c) RD is low, WR is high
d) RD is high, WR is high
Answer: a
Explanation: A bit value is stored for some time by Cg of time period T2 while both RD and WR are made low.
11. Current flows only when
a) RD is low
b) RD is high
c) RD raises exponentially high
d) RD comes exponentially down
Answer: b
Explanation: Current flows only when RD is high and 1 is stored. Thus static dissipating is nil.
This set of VLSI Interview Questions and Answers for Experienced people focuses on “Storage Elements-2”.
1. Overhead bits are used for sensing.
a) true
b) false
Answer: a
Explanation: Overhead bits are used for sensing. Some amount of over head bits are used in one transistor dynamic memory cell.
2. Reading a cell is a _______ operation.
a) constructive
b) destructive
c) semi constructive
d) semi destructive
Answer: b
Explanation: Reading a cell is a destructive operation and the stored bit must be rewritten everytime it is read.
3. RAM is a _____ cell.
a) dynamic
b) partially dynamic
c) static
d) pseudo static
Answer: d
Explanation: RAM is a pseudo static cell. It stores data indefinitely and refreshing is not necessary.
4. Pseudo static RAM cell is built using
a) one inverter
b) two inverters
c) three inverters
d) four inverters
Answer: b
Explanation: Pseudo static RAM cell is built using two inverters and data can be stored in these two inverters by connecting it in parallel and using feedback.
5. Cells must be non stackable in RAM storage cell.
a) true
b) false
Answer: b
Explanation: Cells must be stackable, both side by side and from top to bottom. This must be carefully considered when layout is made.
6. Which cell is non volatile?
a) one transistor dynamic cell
b) two transistor dymanic cell
c) four transistor dynamic cell
d) pseudo static RAM cell
Answer: d
Explanation: Pseudo static RAM cell is a non volatile cell. It is used for long time storage. Non volatile memory is also called as long term memory.
7. In RAM arrays, the transistor is of
a) minimum size
b) maximum size
c) of any size
d) size doesn’t play a role
Answer: a
Explanation: In RAM arrays, the transistor is of minimum size and thus it is incapable of sinking large charges quickly.
8. Which implementation is slower?
a) NAND gate
b) NOR gate
c) AND gate
d) OR gate
Answer: b
Explanation: NOR gate implementation is slower even though both NAND and NOR gate implementation is suitable for CMOS.
9. FOR nMOS which implementation is not suitable?
a) NAND gate
b) NOR gate
c) AND gate
d) OR gate
Answer: a
Explanation: In nMOS, NAND gate implementation is impractical because of the large number of gate requiring three or more inputs.
10. Realization of JK flipflop is based on
a) n-pass transistor
b) p-pass transistor
c) CMOS
d) BiCMOS
Answer: a
Explanation: The realization of JK flip flop is based on n-pass transistor and on inverters only.
11. Static RAM uses ____________ transistors.
a) four
b) five
c) six
d) seven
Answer: c
Explanation: Static RAM uses six transistors. In this RAM cell, read and write operations use the same port.
This set of VLSI Multiple Choice Questions & Answers focuses on “Memory Cells”.
1. Which method is used to determine structural defects?
a) deterministic test pattern
b) algorithmic test pattern
c) random test pattern
d) exhaustive test pattern
Answer: a
Explanation: Deterministic test patterns are used to detect specific faults or structural faults for a circuit under test.
2. Which is known as the stored test pattern method?
a) deterministic test pattern
b) algorithmic test pattern
c) random test pattern
d) exhaustive test pattern
Answer: a
Explanation: Deterministic test pattern method is also known as the stored test pattern method in the context of BIST applications.
3. Which method uses finite state machine for developing the test pattern?
a) deterministic test pattern
b) algorithmic test pattern
c) random test pattern
d) exhaustive test pattern
Answer: b
Explanation: Algorithmic test pattern method uses the hardware finite state machine for generating algorithmic test vectors for the circuit under test.
4. A n-bit counter produces ______ number of total input combinations.
a) 2
b) 2
c) 2 n
d) 2n
Answer: c
Explanation: A n-bit counter produces totally 2 n number of all possible input combinations for testing the circuit under test and it is called an exhaustive test pattern method.
5. Exhaustive test pattern determines
a) gate level faults
b) logic level faults
c) functional faults
d) structural faults
Answer: a
Explanation: Exhaustive test pattern method detects all gate level struck-at fault and also bridging fault.
6. Exhaustive test pattern also detects delay faults.
a) true
b) false
Answer: b
Explanation: Exhaustive test pattern method does not detect all transistor level faults or delay faults since those faults needs specific ordering.
7. Which is not suitable for circuits having large N values?
a) exhaustive test pattern method
b) pseudo-exhaustive test pattern method
c) random test pattern method
d) deterministic test pattern method
Answer: a
Explanation: Exhaustive test pattern method is not suitable for circuit having large N values since there is a limit for fault coverage.
8. Which method needs fault simulation?
a) exhaustive test pattern method
b) pseudo-exhaustive test pattern method
c) random test pattern method
d) deterministic test pattern method
Answer: a
Explanation: Exhaustive test pattern method needs fault simulation for determining fault coverage where as pseudo-exhaustive test pattern method does not need fault simulation.
9. In which method sequences are repeatable?
a) exhaustive test pattern method
b) pseudo-exhaustive test pattern method
c) random test pattern method
d) pseudo-random test pattern method
Answer: d
Explanation: Pseudo-random test pattern method have properties similar to random pattern sequence but the sequence are repeatable.
10. Which method is used for external functional testing?
a) exhaustive test pattern method
b) pseudo-exhaustive test pattern method
c) random test pattern method
d) pseudo-random test pattern method
Answer: c
Explanation: Random test pattern method is used for external functional testing of microprocessors as well as in ATPG software.
This set of VLSI Multiple Choice Questions & Answers focuses on “Flash memory “.
1. Flash memory is a non-volatile storage device in which data
a) can be erased physically
b) can be erased magnetically
c) can be erased electrically
d) cannot be erased
Answer: c
Explanation: Flash memory is an electronic, solid state, non-volatile memory storage device which can be electrically erased and reprogrammed.
2. NOR type flash allows ______ to be read or written independently.
a) one machine cycle
b) one machine word
c) one machine sentence
d) one bit
Answer: b
Explanation: NOR type flash allows a single machine word that is one byte to be written to an erased location or read independently.
3. NAND type flash memories are used in
a) Memory cards
b) USB
c) Solid state drivers
d) All of the mentioned
Answer: d
Explanation: NAND type flash memories operates primarily in memory cards, USB flash drives and solid state drivers.
4. Which is a comparatively slower device?
a) ROM
b) RAM
c) flash memory
d) SRAM
Answer: c
Explanation: Flash memory has fast read access time, but static RAM or ROM are comparatively faster than flash memory.
5. Floating gate transistor in flash memory has
a) two gates
b) one gate
c) two sources
d) two drains
Answer: a
Explanation: Floating gate transistor in flash memory has two gates. These two gates are – floating gate and control gate.
6. In NOR type flash memory, each cell has one end connected to
a) source
b) drain
c) gate
d) ground
Answer: d
Explanation: In NOR type flash memory, each cell has one end connected directly to ground and other end connected to the bit line.
7. In NOR type flash memory, data is erased
a) bitwise
b) bytewise
c) blockwise
d) sentence wise
Answer: c
Explanation: In NOR type flash memory the data can be erased only blockwise basis. all the cells in an erase segment must be erased together.
8. The transistors in NAND type flash are connected in
a) series
b) parallel
c) cascade
d) randomly
Answer: a
Explanation: The NAND type flash memory also uses floating gate transistors and it is connected to form NAND gate. The transistors are connected in series.
9. In NAND type flash, memory can be addressed bit-wise.
a) true
b) false
Answer: a
Explanation: In NAND type flash, memory can be addressed by word, page or even bit wise. In NOR type flash, memory can be addressed by page then a word.
10. The program erase cycle in flash memory is
a) finite
b) infinite
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: One disadvantage of flash memory is that it has finite number of program-erase cycles. This limits the usage of flash memory.
11. NOR type flash needs error correcting code.
a) true
b) false
Answer: b
Explanation: NOR flash memory is a storage device. It has slow write speed compared to NAND type flash. Typical NOR type flash does not need error correcting codes.
12. Which allows random access to read?
a) NOR type flash
b) NAND type flash
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: The interface provided for reading and writing is different. NOR type flash provides random access for reading whereas NAND type flash provides page access.
13. Which has high storage capacity?
a) NOR type flash
b) NAND type flash
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: NAND type flash memory has different connections and interface when compared to NOR type flash. Storage capacity is more in NAND type flash than NOR type flash memory.
This set of VLSI Multiple Choice Questions & Answers focuses on “Optimization of Inverters-1”.
1. Reduction in power dissipation can be brought by
a) increasing transistor area
b) decreasing transistor area
c) increasing transistor feature size
d) decreasing transistor feature size
Answer: a
Explanation: The 3:1 reduction in power dissipation can be brought at the expense of increasing the transistor area by 50%.
2. When does the longest delay occur in 8:1 inverters?
a) during 1 to 0 transition
b) during 0 to 1 transition
c) during faster speed
d) delays are always short
Answer: b
Explanation: In 8:1 inverters, the longest delay will occur when the output of the first stage is changing from logic 0 to 1 and capacitance must charge through pull-up resistance.
3. In inverter during logic 1 to 0 transition, capacitance discharges at
a) pull-up resistance
b) pull-down resistance
c) both pull-up and pull-down
d) at gate
Answer: b
Explanation: During the logic 1 to 0 transition, the capacitance which is charged through pull-up must always discharge through pull-down transistor at first stage.
4. In minimum size nMOS 8:1 inverter, the logic 0 to 1 transition delay is given as
a) 5Ć®
b) 20Ć®
c) 40Ć®
d) 50Ć®
Answer: c
Explanation: For minimum pull-down feature size nMOS 8:1 inverter, the logic 0 to 1 transition delay can be given as 8Rs x 5 square Cg which gives 40Ć®.
5. In minimum size nMOS 8:1 inverter, the logic 1 to 0 transition delay is given as
a) 5Ć®
b) 20Ć®
c) 40Ć®
d) 50Ć®
Answer: a
Explanation: 8:1 nMOS inverter allows stray and wiring capacitance and the logic 1 to 0 transition delay can be given as 1Rs x 5 square Cg which gives 5Ć®.
6. For a regular 8:1 inverter, the transition delay is given as
a) 10Ć®
b) 20Ć®
c) 21Ć®
d) 25Ć®
Answer: c
Explanation: For 8:1 inverter the logic 0 to 1 transition delay can be given as 21Ć® and logic 1 to 0 transition delay can be given as 2Ć®.
7. The area of CMOS inverter is proportional to
a) area of n device
b) area of p device
c) total area of n and p device
d) square of minimum feature size
Answer: c
Explanation: The area of a basic CMOS inverter is proportional to the total area occupied bu the p and n devices .
8. The ratio of Wp/Wn can be given as
a) 1:2
b) 2:1
c) 1:1
d) 2:2
Answer: c
Explanation: Minimum area can be achieved by choosing minimum dimensions for Wp, Wn, Lp, Ln which is 2λ and the ratio of Wp/Wn can be given as 1:1.
9. Switching power dissipation can be given as
a) Cl x Vdd x f
b) Vdd 2 x f
c) Cl x Vdd 2
d) Cl x Vdd 2 x f
Answer: d
Explanation: Switching power dissipation Psd can be given as Cl x Vdd 2 x f where Cl is load capacitance, Vdd is power supply voltage and f is the frequency of switching.
10. Load capacitance can be minimized by
a) increasing A
b) decreasing A
c) increasing Psd
d) does not depend on A
Answer: b
Explanation: For fixed Vdd and f, minimizing Psd requires minimizing Cl which can be minimized by decreasing area A as it is directly proportional to gate area.
11. Rise time and fall time can be equalized by
a) βn = βp
b) βn = 2βp
c) βp = 2βn
d) βn = 1/2βp
Answer: a
Explanation: Rise time tr and fall time tf can be equalized by using βn = βp, which requires = µµ.
This set of VLSI test focuses on “Optimization of Inverters-2”.
1. Rise time and fall time can be also equalized by
a) Lp = Ln = λ
b) Lp = Ln = λ/2
c) Lp = Ln = 2λ
d) 2Lp = Ln = λ
Answer: c
Explanation: Rise time and fall time can be equalized by taking Lp = Ln = 2λ which implies Wp/Wn = 2 and also µn/µp = 2.
2. Equalizing of rise time and fall time is possible in
a) nMOS
b) pseudo nMOS
c) CMOS
d) pMOS
Answer: c
Explanation: Equalizing of rise time and fall time is possible only in CMOS and not possible in nMOS and pseudo nMOS because of the ratio requirement.
3. High and low noise margins can be equalized by
a) βn = βp
b) βn greater than βp
c) βn lesser than βp
d) Lp = 2Ln
Answer: a
Explanation: High and low noise margins can be equalized by choosing βn = βp, also Ln = Lp which implies Wp/Wn = 2.
4. Inverter pair delay D is given as equal to
a) tr
b) tf
c) tr-tf
d) tr+tf
Answer: d
Explanation: Inverter pair delay D is given as the sum of rise time and fall time. This is proportional to Cl where Rp and Rn are average resistances.
5. For minimum D consider
a) Ln = Lp = 2λ
b) Ln greater than Lp = 2λ
c) Lp greater than Ln
d) Lp = 2Ln
Answer: a
Explanation: D increases with Ln and Lp so for minimum D we have to choose Ln=Lp=2λ. D does not vary significantly with lesser than lesser than .
6. Different parameter optimization is easily achievable in
a) nMOS
b) pMOS
c) pseudo nMOS
d) CMOS
Answer: d
Explanation: Different parameter optimizations like noise margins equalization, rise time fall time equalization can be easily achievable in CMOS.
7. Minimizing A with respect to Wp.d. gives
a) Wp.d. = 2λ
b) Wp.d. = λ/2
c) Wp.d. = 1/2 x 2λ
d) Wp.d. = k x 1/2 x 2
Answer: c
Explanation: Minimizing A with respect to Wp.d yields a solution as Wp.d. = 1/2 x Wp.u. = 1/2 x 2λ.
8. Using Zp.u./Zp.d = k, Lp.u. can be obtained as
a) k x 2λ
b) k x λ
c) 1/2 x 2λ
d) k x 2 x 1/2
Answer: c
Explanation: Using this ratio Zp.u./Zp.d. = k, we obtain Lp.u. = 1/2 x Lp.d. = 1/2 x 2λ.
9. Minimum area can be given as
a) 4 x Ao x λ x 1/2
b) 4 x Ao x λ x k
c) 8 x Ao x λ 2 x 1/2
d) 8 x Ao x λ x 1/2
Answer: c
Explanation: Minimum area A can be given as 8 x Ao x λ 2 x 1/2 which implies Zp.u. = 1/2 and Zp.d. = 1/ 1/2 .
10. When Zp.d. or Zp.u. increases, delay
a) increases
b) decreases
c) remains the same
d) delay becomes zero
Answer: a
Explanation: Pd is minimized by increasing Zp.d.. Large Zp.d. requires large Zp.u. which results in increase in delay D of the inverter pair.
11. For minimum D which relation is choosen?
a) Zp.u. = 1/2k
b) Zp.u. = k
c) Zp.d. = 1/k
d) Zp.d. = 1
Answer: c
Explanation: For minimum D, Zp.u. is 1 and Zp.d. is equal to 1/k with Wp.u. = 2λ and Wp.d. = k x 2λ.
12. Noise margin measures the changing strength of
a) input voltage
b) output voltage
c) threshold voltage
d) supply voltage
Answer: a
Explanation: Noise margin measures by how much the input voltage can change without disturbing the present logic output state.
13. Which has better noise margins?
a) nMOS
b) pMOS
c) CMOS
d) BiCMOS
Answer: c
Explanation: CMOS has better noise margins than nMOS especially at low conditions because ratio adjustment is easier in CMOS.
This set of VLSI Multiple Choice Questions & Answers focuses on “Floor Layout”.
1. A 4-bit processor has two buses which are
a) unidirectional
b) bidirectional
c) one unidirectional and one bidirectional
d) more than two buses
Answer: c
Explanation: A 4-bit processor has two buses one is bidirectional to carry operand and output to shifter and register array and another bus unidirectional to carry input.
2. The IN and OUT bus lines relative positions are interchanged to
a) match height
b) match length
c) match width
d) match thickness
Answer: a
Explanation: The IN and OUT bus line’s relative positions are interchanged to make the cell stretchable and to match the height of the block and spacings.
3. The IN and OUT bus lines should be in
a) metal
b) polysilicon
c) diffusion
d) silicon
Answer: a
Explanation: The IN and OUT bus lines should be in metal rather than diffusion or polysilicon to mate with the bus structures of other blocks.
4. Extensions are
a) vertical
b) horizontal
c) diagonal
d) haphazard
Answer: b
Explanation: Extensions are horizontal or parallel to the stratified unit and rifts are described as extension zones.
5. Rifts and extensions should be placed in
a) minimum amount of geometry
b) maximum amount of geometry
c) in slopes
d) anywhere in the layout
Answer: a
Explanation: Rifts and extensions should be placed where they cut a minimum amount of simple geometry, one in polysilicon and one in diffusion.
6. Rifts are used for smooth flow through buses.
a) true
b) false
Answer: a
Explanation: Rifts are used for smooth flow through buses as suggested and hence one in used in polysilicon and other in diffusion.
7. Input and output pads are made up of
a) polysilicon
b) metal
c) silicon
d) carbon
Answer: b
Explanation: Input and output pads are made up of metal and it used to connect chips from one circuitry to another.
8. Bonding pads are placed
a) in the chip
b) exactly at the centre of chip
c) edge of the chip
d) above the chip
Answer: c
Explanation: Bonding pads are positioned near to the edge of the chips although there will be a Vdd bus between bonding pads and chip boundary.
9. Which pad contains Schmitt trigger circuitry?
a) Vdd pads
b) Vss pads
c) input pads
d) output pads
Answer: c
Explanation: Input pad contains over voltage protection features and also contains inverting circuitry or Schmitt trigger circuitry.
10. Which occupies lesser area?
a) Vdd pads
b) Vss pads
c) input pads
d) output pads
Answer: d
Explanation: Output pads provide large current for off-wiring and also inputs to other devices. But these pads uses minimum space.
11. Buffers are needed to drive
a) small capacitance
b) large capacitance
c) small resistance
d) large resistance
Answer: b
Explanation: Buffers are necessary in environments on and off chip. It is used to drive relatively large capacitances associated with circuits off the chip.
12. Pads must be placed generally in the periphery of the chip area.
a) true
b) false
Answer: a
Explanation: Usually pads must be placed in the periphery of the chip area otherwise bonding difficulties may be encountered.
13. How much area should be allocated for pads?
a) one third
b) two third
c) half
d) three fourth
Answer: a
Explanation: According to a thumb rule, the small system designer should allow one third of the chip area for pads.
This set of VLSI Multiple Choice Questions & Answers focuses on “System Delays”.
1. Which provides large capacitance?
a) load capacitance
b) bus wiring capacitance
c) sheet capacitance
d) area capacitance
Answer: b
Explanation: Bus wiring capacitance Cbus provides the largest capacitance for a typical bus system for example for small chips this can be as high as 0.8pF.
2. Bus wiring capacitance is driven through
a) one transistor
b) two transistors
c) three transistors
d) no transistors
Answer: a
Explanation: Bus wiring capacitance is driven through pull-up and pull-down transistors and through atleast one pass transistor or transmission gate in the series.
3. What is the delay of input pads?
a) 5Ć®
b) 10Ć®
c) 40Ć®
d) 30Ć®
Answer: d
Explanation: Input pad always contains over voltage protection circuitry and Schmitt trigger circuitry. Its total delay is 30Ć®.
4. The total delay for the select register circuit is
a) 33Ć®
b) 60Ć®
c) 55Ć®
d) 73Ć®
Answer: d
Explanation: The total delay for the select register is 73Ć®. It is the sum of delays of input pad, three pass transistors and driver inverter pair.
5. Delay for data propagation is
a) 10 nsec
b) 50 nsec
c) 100 nsec
d) 150 nsec
Answer: c
Explanation: Data is propagated through bus. Bus can be bidirectional but at data can be propagated through bus only at one direction at a time. The delay for this data propagation is 100nsec.
6. Which is the longest delay in adder process?
a) sum delay
b) carry delay
c) propagation delay
d) inverter delay
Answer: b
Explanation: The longest delay in the adder process is the carry chain delay. This is the process of forming carry out which propagates through all bits of the adder.
7. The total delay for the adder process is
a) 100 nsec
b) 200 nsec
c) 220 nsec
d) 250 nsec
Answer: c
Explanation: The total delay for the adder process is 220 nsec. The total delay is the sum of select register delay, bus delays and carry chain delays.
8. The refreshing clock period should propagate through
a) memory cell
b) wiring
c) carry chain
d) any sub unit
Answer: b
Explanation: The clock 2 which is the refreshing clock should propagate through wiring and finite rise and fall time must be allowed.
9. The value of Ć® for 5 micron technology is always constant.
a) true
b) false
Answer: b
Explanation: The range of value of Ć® for 5 micron technology was calculated to be 0.1 to 0.3 nsec but it may vary upto 0.6 nsec.
10. The total clock period for adder process is
a) 100 nsec
b) 150 nsec
c) 200 nsec
d) 250 nsec
Answer: d
Explanation: The total clock period of the adder process is 250 nsec which is the sum of all the delay and the period of different phases of the process.
This set of VLSI Multiple Choice Questions & Answers focuses on “Rules for Proper Design”.
1. The Zp.u./Zp.d. ratio for nMOS inverter is
a) 4:1
b) 3:1
c) 1:4
d) 1:3
Answer: a
Explanation: For nMOS inverters the Zp.u./Zp.d. ratio is 4:1 when driven from another inverter and 8:1 when driven through one or more pass transistors.
2. The impedance ratio for pseudo-nMOS is
a) 4:1
b) 3:1
c) 1:4
d) 1:3
Answer: b
Explanation: For pseudo-nMOS, the Zp.u./Zp.d. ratio is 3:1 and for CMOS 1:1 ratio is required for minimum area.
3. What is the value for peripheral capacitance for 5 micron technology?
a) 4 x 10 pf/µm 2
b) 5 x 10 pf/µm 2
c) 8 x 10 pf/µm 2
d) 12 x 10 pf/µm 2
Answer: c
Explanation: Peripheral capacitance is the side wall capacitance. Peripheral capacitance of 5 micron technology is 8 x 10 pf/µm 2 .
4. 1 square Cg is ___________ of MOS transistor.
a) gate to source capacitance
b) gate to drain capacitance
c) source to drain capacitance
d) gate to channel capacitance
Answer: d
Explanation: 1 square Cg is defined as the gate to channel capacitance of a MOS transistor having standard feature size .
5. What is the delay value Ć® for 1.2 micron technology?
a) 0.1 nsec
b) 0.12 nsec
c) 0.046 nsec
d) 0.064 nsec
Answer: c
Explanation: The delay Ć® is the time constant and for 1.2 micron technology its value is 0.046 nsec.
6. Which is used to increase Ć®?
a) parasitic capacitance
b) peripheral capacitance
c) area capacitance
d) load capacitance
Answer: a
Explanation: Circuit wiring and parasitic capacitance must be allowed to increase the value of Ć® by the factor of 2 or 3.
7. The inverter pair delay is given by
a) Ć®
b) Ć®
c) Ć®
d) ƮZp.u./Zp.d.
Answer: b
Explanation: The inverter delay is given by Ć®. The inverter pair delay for CMOS is 7Ć®.
8. The number of stages N is given by
a) ln/ln
b) ln/ln
c) ln/ln
d) ln/ln
Answer: a
Explanation: To calculate the value for N, where N inverters are cascaded, each one of which is larger than the preceding stage by a width factor f the formula used is ln/ln.
9. If f assumes the value e then delay is
a) maximized
b) minimized
c) does not change
d) doubled
Answer: b
Explanation: Total delay is minimized if f assumes the value of e which is the base of the natural logarithm. This applies to both nMOS and CMOS.
10. Propogation delay is given by
a) nrcĆ®
b) n 2 rcĆ®
c) nr 2 cĆ®
d) n 2 cĆ®
Answer: b
Explanation: Propogation delay through cascaded pass transistors or transmission gate can be given as n 2 rcĆ®.
11. Using _____ long wires are possible.
a) silicide
b) metal
c) polysilicon
d) diffusion
Answer: a
Explanation: Using silicide, reasonable long wires are possible. It is a modest RC product. Silicides are used in place of polysilicon in some nMOS processes.
12. One pass transistor can be driven through output of another.
a) true
b) false
Answer: b
Explanation: No pass transistor gate must be driven through the output of one or more pass transistors since logic 1 levels are degraded by the threshold voltage.
13. Pass transistors are allowed to be constructed under
a) diffusion layer
b) polysilicon layer
c) metal layer
d) silicon layer
Answer: c
Explanation: Pass transistors are allowed to be constructed under metal layers to save space and is more convenient.
14. Maximum allowable current density in aluminium is
a) 0.1 mA/µm 2
b) 0.5 mA/µm 2
c) 2 mA/µm 2
d) 1 mA/µm 2
Answer: d
Explanation: The maximum allowable current density in aluminium wire is 1 mA/µm 2 . Otherwise metal migration may occur.
This set of VLSI Multiple Choice Questions & Answers focuses on “Design Styles”.
1. In which design all circuitry and all interconnections are designed?
a) full custom design
b) semi-custom design
c) gate array design
d) transistor design
Answer: a
Explanation: Full custom design is the complete design for the implementation. It contains all circuitry and all interconnections/communication paths.
2. Which design contains only the interconnections designed?
a) full custom design
b) semi-custom design
c) gate array design
d) transistor design
Answer: c
Explanation: Gate array design which is also known as uncommitted logic array design has the design of only the interconnections/communication paths.
3. In which method regularity is used to reduce complexity?
a) random approach
b) hierarchical approach
c) algorithmic approach
d) semi-design approach
Answer: b
Explanation: Hierarchical approach is in the one in which principles of iteration or regularity can be used to reduce the complexity of the design task.
4. Size of the die is determined using
a) transistor size
b) inverter size
c) area of the circuitry
d) length of the circuitry
Answer: c
Explanation: Size of the die is determined by the area occupied by the circuitry. Large die sizes area associated with poor yields and high costs.
5. Which design is faster?
a) full custom design
b) semi-custom design
c) gate array design
d) transistor design
Answer: c
Explanation: Gate array design is faster than a prototype full-custom design and the final custom designs must be carefully optimized.
6. Which has relatively low-level capabilities?
a) hand-crafted designs
b) computer assisted textual entry
c) computer assisted graphical entry
d) silicon compiler-based design
Answer: b
Explanation: Computer-assisted textual entry has programs which may be relatively low-level capabilities and it allows the entry of rectangular boxes, wires, etc.
7. Computer-assisted graphical entry is done through
a) monochrome
b) grayscale graphics
c) bichrome
d) trichrome
Answer: a
Explanation: Computer-assisted graphical entry of mask geometry is through either monochrome or color graphics terminal.
8. Which method is used for verification along with generation?
a) hand-crafted designs
b) computer assisted textual entry
c) computer assisted graphical entry
d) silicon compiler-based design
Answer: c
Explanation: Computer-assisted graphical entry method encourages regularity and are generally used with a generate then verify design philosophy.
9. Which method uses high level programming language?
a) hand-crafted designs
b) computer assisted textual entry
c) computer assisted graphical entry
d) silicon compiler-based design
Answer: d
Explanation: Silicon compiler-based design uses high level approach and uses special languages like high level language compilers.
10. The set of design rules does not give
a) widths
b) spacing
c) colors
d) overlaps
Answer: c
Explanation: Communication between the fabrication house and the designer takes the form of a set of design rules with gives clearance, widths, spacing, overlaps, etc.
This set of VLSI Multiple Choice Questions & Answers focuses on “Design Using CIF Code”.
1. Caltech intermediate form code is a
a) low-level graphic language
b) low-level textual language
c) high-level graphic language
d) high-level textual language
Answer: a
Explanation: Caltech intermediate form code is a low-level graphic language used to specify geometry of integrated circuits.
2. CIF generates code which are
a) high-level language
b) assembly level language
c) machine readable language
d) very high-level language
Answer: c
Explanation: CIF code is to communicate chip geometry in a standard machine readable form for mask-making.
3. CIF code is compatible with
a) low system geometry
b) large system geometry
c) both low and large system geometry
d) medium system geometry
Answer: c
Explanation: CIF code is reasonable compact and can cope with both low and large system geometry. It is easily readable.
4. Design through CIF is done using
a) color codes
b) geometric shapes
c) different layer thickness
d) transistors
Answer: b
Explanation: In Caltech intermediate form code, the design is given using geometric shapes. Boxes, polygons and wires are readily defined.
5. The CIF dimensions are given in the form of
a) X,Y coordinates
b) lambda form
c) millimeter form
d) alpha form
Answer: a
Explanation: The CIF dimensions and positions are given in X, Y coordinate form but are in absolute dimension units and not in lambda form.
6. Polygons in CIF are specified in terms of
a) length
b) width
c) vertices
d) angles
Answer: c
Explanation: In CIF, polygons are specified in terms of vertices in order. An n-sided polygon needs n vertices and a connection between first and last.
7. Wires are specified in terms of
a) vertices
b) width
c) angles
d) lengths
Answer: b
Explanation: Wires are specified in terms of their width followed by the center line’s coordinates of the wire’s path.
8. CIF can also accommodate rotations and translations.
a) true
b) false
Answer: a
Explanation: CIF also accommodates cells and rotations and translations etc along with geometrical shaped designs.
9. If vector coordinate is it indicates that
a) length is parallel to y-axis
b) length is parallel to x-axis
c) width is parallel to y-axis
d) width is parallel to x-axis
Answer: b
Explanation: If the vector coordinate is , it denotes that the length will be parallel to the x-axis. The direction is always assumed parallel to the length.
10. In which layer the geometrical structures exist?
a) metal
b) silicon
c) silicide
d) diffusion
Answer: b
Explanation: In CIF design is done using geometrical structures like boxes, polygons, etc and these boxes exist in the silicon layer.
This set of VLSI Multiple Choice Questions & Answers focuses on “Design Using CAD Tools”.
1. Physical verification tools in design process include
a) circuit extractors
b) textual entry
c) graphical entry
d) simulation
Answer: a
Explanation: Physical verification tools in design process includes design rule checking, circuit extractors, ratio rule and other static checks.
2. Behavioral tools contain
a) graphical entry
b) design check
c) performance check
d) simulation
Answer: d
Explanation: Behavioral tools contain simulation at various levels. It will be required to check out the design before turning out the design in silicon.
3. Simulators are available for
a) transistor level logic
b) switch level logic
c) gate level logic
d) design level logic
Answer: b
Explanation: Simulators are available for switch level logic and timing simulation. This is used to check out the design.
4. Selection and placement is done using
a) cursor
b) shapes
c) textual
d) graphical
Answer: a
Explanation: Selection and placement geometric shapes are done using some form of cursor and it may also allow selection of menu items.
5. Cursor position is controlled using
a) mouse
b) bitpad digitizer
c) mouse and bitpad digitizer
d) keyboard
Answer: c
Explanation: Positioning of cursor may be affected from keyboard and cursor position is controlled from a bitpad digitizer or a mouse.
6. CIF code is a ______ layout language.
a) mask level
b) floor level
c) design level
d) transistor level
Answer: a
Explanation: CIF is an example of mask level layout language, which are well suited to physical layout description but not for capturing the design intent.
7. Which verification capture’s design intent and not physical layout?
a) mask level layout language
b) transistor level layout language
c) circuit description language
d) switch level layout language
Answer: c
Explanation: Circuit description language where the primitives are circuit elements such as transistors, wires and nodes. It captures the design intent and not directly the physical layout.
8. All possible errors in mask layout can be eliminated after mask making proceeds.
a) true
b) false
Answer: b
Explanation: The cost in time and the facilities in mask-making is such that all the possible errors must be eliminated before mask making proceeds.
9. The nature of physical layout verification software depends on
a) absolute design rules
b) fixed layout
c) virtual grid layout
d) all of the mentioned
Answer: d
Explanation: The nature of physical layout verification design rule checking software depends on whether the design rules are absolute or lambda-based or on whether or not the layout is on a fixed or virtual grid.
10. Which is used to interpret physical layout in circuit terms?
a) circuit converter
b) layout converter
c) circuit extractor
d) layout extractor
Answer: c
Explanation: Circuit extractor is used to convert the design information which is in the form of physical layout data to circuit terms.
This set of VLSI Multiple Choice Questions & Answers focuses on “Simulators”.
1. Simulator converts circuit information to
a) design plan
b) does verification
c) set of equations
d) floor plan
Answer: c
Explanation: The circuit description contains information about circuit components and interconnections. This is transformed using a simulator to a set of equations from which predictions of behaviour are made.
2. The electrical behaviour of a circuit is given using
a) design rules
b) floor plan
c) structures and layouts
d) mathematical modelling
Answer: d
Explanation: The electrical behaviour is defined by mathematical modelling and its accuracy is measured using the accuracy of simulation and computing power and time for simulation.
3. Which gives the main electrical behaviour of various parts of the circuit?
a) circuit simulator
b) timing simulator
c) logic level simulator
d) functional simulator
Answer: a
Explanation: Circuit simulators are concerned with the electrical behaviour of the various parts of the circuit to be implemented in silicon.
4. Which takes lots of simulating time?
a) circuit simulator
b) timing simulator
c) logic level simulator
d) functional simulator
Answer: a
Explanation: Circuit simulators takes lot of computing time to simulate even small section of system and are completely impractical for circuits of any real magnitude.
5. Timing simulator concentrates on
a) quiescent nodes
b) active nodes
c) passive nodes
d) electrical nodes
Answer: b
Explanation: Timing simulator concentrates on active nodes and ignores the quiescent nodes in simulation and improves the design accordingly.
6. The accuracy of simulation depends on accuracy of
a) fabrication house parameters
b) electrical parameters
c) active parameters
d) functional parameters
Answer: a
Explanation: The accuracy of simulation depends on accuracy of fabrication house parameters which must be fed into the simulator which is in the range of 20% or better.
7. Which is important during the design phase?
a) circuit simulator
b) timing simulator
c) logic level simulator
d) functional simulator
Answer: b
Explanation: Timing simulators are increasingly important during the design phase because of their speed and consequent interactive qualities.
8. Run times are _______ to number of devices and nodes.
a) linearly related
b) inversely related
c) exponentially equal
d) does not relate
Answer: a
Explanation: Run time is linearly related to the number of devices and nodes being simulated. The structure of timing simulator tools ensure this relationship.
9. Improvement of transistor modelling includes
a) body effect
b) channel length modulation
c) carrier velocity saturation
d) all of the mentioned
Answer: d
Explanation: To improve the transistor modelling it is possible to include body effect, channel length modulation and carrier velocity saturation.
10. Channel length modulation is for voltages
a) exceeding threshold
b) exceeding onset of saturation
c) exceeding power supply
d) exceeding onset of non saturation
Answer: b
Explanation: Channel length modulation is for voltages exceeding the onset of saturation there is an effective decrease in channel lengthof a short channel transistor.
11. The charge carriers reach _________ scattering limited velocity before pinch off.
a) maximum
b) minimum
c) less
d) equal
Answer: a
Explanation: Velocity saturation occurs when the drain to source voltage of a short channel transistor exceeds a critical value, the charge reach their maximum scattering limited velocity before pinch off.
12. Less current is available from
a) short channel transistor
b) large channel transistor
c) very large channel transistor
d) does not depend on channel transistor
Answer: a
Explanation: Less current is available from a short channel transistor than from a long channel transistor with similar width to length ratio and processing.
13. Which can cope up with large sections of layout?
a) circuit simulator
b) timing simulator
c) logic level simulator
d) functional simulator
Answer: c
Explanation: Logic level simulator can cope with large section of the layout at one time but the performance is assumed in terms of logic levels with no or little timing information.
14. Logic simulators can be replaced by simulators which operate at transistor level.
a) true
b) false
Answer: b
Explanation: Logic simulators may be replaced by simulators which operate at the register transfer level.
This set of VLSI Multiple Choice Questions & Answers focuses on “Test and Testability “.
1. Circuit nodes cannot be probed for monitoring or excitation.
a) true
b) false
Answer: a
Explanation: The entire surface of the chip other than the pads are sealed by an overglass layers and thus circuit nodes cannot be probed for monitoring and excitation.
2. The circuit should be tested at
a) design level
b) chip level
c) transistor level
d) switch level
Answer: b
Explanation: Chip design mistakes can be very costly both in terms of time and money. The circuit should be tested at chip level itself. Design for testability is essential for good design.
3. ______ of the area is dedicated for testability.
a) 20%
b) 10%
c) 30%
d) 25%
Answer: c
Explanation: Design for testability is an essential process for good design. Thus the designers dedicate around 30% or more of chip area for testing.
4. Partitioning into subsystems are done at
a) design stage
b) prototype stage
c) testing stage
d) fabrication stage
Answer: b
Explanation: At the prototype stage, partitioning into subsystems are done to solve all the complexity problem. Each of these subsystems are self contained and independent.
5. In prototype testing, the circuits are
a) open circuited
b) short circuited
c) tested as a whole circuit
d) programmed
Answer: a
Explanation: The connections are made open circuited so that one system can be divorced from another as a last resort in prototype testing.
6. The number of test vectors for exhaustive testing is calculated by
a) 2
b) 2 /2)
c) 2
d) 2 2
Answer: a
Explanation: The total number of test vectors for exhaustive testing is given by 2 . For example if m is 20 and n is 24, the resultant number of test vectors for exhaustive testing is 2 44 .
7. After partitioning, number of vectors is given by
a) 2
b) 2 /2)
c) 2 n + 2 m
d) 2 2
Answer: c
Explanation: If the system is partitioned for testing, exhaustive testing can be reduced to 2 n + 2 m a much more reasonable proportion.
8. What are the dominant faults in diffusion layers?
a) short citcuit faults
b) open circuit faults
c) short and open circuit faults
d) power supply faults
Answer: a
Explanation: In MOS circuits, short circuit and open circuit in metal layer and short circuit in diffusion layer are the dominant fault experienced.
9. Test pattern generation is assisted using
a) automatic test pattern generator
b) exhaustive pattern generator
c) repeated pattern generator
d) loop pattern generator
Answer: a
Explanation: Test pattern generation is assisted using automatic test pattern generators but they are complicated to use properly and ATPG costs tend to rise rapidly with circuit size.
10. _____ of faults are easier to detect.
a) 50%
b) 60%
c) 70%
d) 80%
Answer: d
Explanation: It is relatively easy to detect the first 80% of faults using various classical test strategies.
11. Hot carrier injection causes
a) threshold voltage shift
b) transconductance degradation
c) threshold voltage shift & transconductance degradation
d) none of the mentioned
Answer: c
Explanation: Hot carrier injection causes both threshold voltage shift and transconductance degradation due to charge accumulation in the gate oxide.
12. Oxide breakdown occurs due to
a) electrostatic charge
b) threshold voltage
c) voltage shift
d) poor input/output pad circuitry
Answer: d
Explanation: Oxide breakdown occurs due to inadequate protection against electrostatic discharge and also due to defect or poor design in input/output pad circuitry.
13. Which model is used for pc board testing?
a) stuck at
b) stuck in
c) stuck on
d) stuck through
Answer: a
Explanation: The stuck at model is used in the testing of pc boards and is not sufficient to test actual VLSI CMOS circuits.
This set of VLSI Multiple Choice Questions & Answers focuses on “Testing Combinational Logic”.
1. The input signal combination in exhaustive testing is given as
a) 2 N
b) 2 1/N
c) 2
d) 1/2 N
Answer: a
Explanation: For testing an N input circuit using exhaustive testing, the total number of input combinations can be given as 2 N .
2. Observability is the process of
a) checking all inputs
b) checking all outputs
c) checking all possible inputs
d) checking errors and performance
Answer: b
Explanation: Observability is the process of observing outputs for all the input combinations.
3. Exhaustive testing is suitable when N is
a) small
b) large
c) any value for N
d) very large
Answer: a
Explanation: Exhaustive testing is the process where all possible input combinations are used. This is suitable when N is relatively small.
4. Test vectors in sensitized path-based testing is generated
a) before enumerating faults
b) after enumerating faults
c) after designing
d) before designing
Answer: b
Explanation: In sensitized path-based testing, test vectors are generated after enumerating the possible faults because many patterns may not occur during the application of the circuit.
5. To propagate the fault along the selected path to primary output, setting _____ is done.
a) AND to 1
b) OR to 1
c) NOR to 1
d) NAND to 0
Answer: a
Explanation: Inputs of another gate is determined so as to propagate the fault signal along the selected path to primary output of the circuit. This is done by setting AND/NAND to 1 and OR/NOR to 0.
6. In consistency/ justification, tracking is done
a) forward from gate input to primary input
b) backwards from gate input to primary output
c) backwards from gate input to primary input
d) forward from gate output to primary output
Answer: c
Explanation: Consistency step finds the input patterns to realize all the necessary values. This is done by tracking backwards from gate input to primary input of the logic.
7. In D-algorithm, a particular ______ fault is detected by examining the _____ conditions.
a) internal, output
b) internal, input
c) external, output
d) external, input
Answer: a
Explanation: In a circuit comprising combinational logic, D-algorithm aims at detecting a particular internal fault by examining the output conditions.
8. D-algorithm is based on
a) existence of one fault machine
b) existence of one good machine
c) existence of one fault and one good machine
d) existence of two fault machines alone
Answer: c
Explanation: D-algorithm is based on the hypothesis of the existence of two machines – one good machine and one faulty machine.
9. The existence of fault in faulty machine causes discrepancy in behaviour of the circuit for all values on inputs.
a) true
b) false
Answer: b
Explanation: The existence of fault in faulty machine causes discrepancy in its behaviour and that of the good machine for some particular values of inputs.
10. In D-algorithm, the discrepancy is driven to _____ and observed and thus detected.
a) all inputs
b) particular inputs
c) output
d) end of the circuit
Answer: c
Explanation: In D-algorithm, a systematic means is provided to driven the discrepancy to output and it is observed and detected.
11. D-algorithm is time intensive for large circuits.
a) true
b) false
Answer: a
Explanation: D-algorithm is extremely time intensive and computing intensive for large circuits and many modifications and improvements are done.
This set of VLSI Multiple Choice Questions & Answers focuses on “Testing Sequential Logic”.
1. Sequential circuits are represented as
a) finite state machine
b) infinite state machine
c) finite synchronous circuit
d) infinite asynchronous circuit
Answer: a
Explanation: Sequential circuits are represented as finite state machine and may be modelled as combinational logic.
2. Sequential circuit includes
a) delays
b) feedback
c) delays and feedback from input to output
d) delays and feedback from output to input
Answer: d
Explanation: Sequential circuit includes a set of delays and feedback from output to input and it is known as finite state machine.
3. Which constitutes the test vectors in sequential circuits?
a) feedback variables
b) delay factors
c) test patterns
d) all input combinations
Answer: a
Explanation: The ‘m’ feedback variables constitute the state vector and determine the maximum number of finite states which may be assumed by the circuit.
4. Outputs are functions of
a) present state
b) previous state
c) next state
d) present and next state
Answer: a
Explanation: Next state and output are both functions of present state and the independent inputs.
5. Which is the delay elements for clocked system?
a) AND gates
b) OR gates
c) Flip-flops
d) Multiplexers
Answer: c
Explanation: In clocked systems, the basic delay elements are flip-flops and in asynchronous circuits, the delays may be contributed by circuit propagation delays.
6. Which contributes to the necessary delay element?
a) flip-flops
b) circuit propagation elements
c) negative feedback path
d) shift registers
Answer: b
Explanation: The circuit propagation delays contribute to the necessary delay elements. The delay in the feedback path may be non-existence.
7. In an OR gate, if A and B are two inputs and there is struck at 1 fault in B path, then output will be
a) A
b) 0
c) 1
d) B’
Answer: c
Explanation: In an OR gate, if struck at 1 fault in present in B path then output will always be 1.
8. Iterative test generation method suits for circuits with
a) no feedback loops
b) few feedback loops
c) more feedback loops
d) negative feedback loops only
Answer: b
Explanation: The iterative test generation methods are best suited to logic with few feedback loops as in control logic for example.
9. Which method is very time consuming?
a) D-algorithm
b) iterative test generation
c) pseudo exhaustive method
d) test generation pattern
Answer: b
Explanation: Iterative test generation method is time consuming for circuits of any complexity. It is necessary to describe the initial states of the circuit, which is also time consuming.
10. In this technique, a simple fault manifests into multiple N faults.
a) true
b) false
Answer: a
Explanation: The main problem in this iterative test generation technique is that a simple fault in the sequential machine is manifest as N multiple faults during test.
11. In this iterative test generation method, sequential logic is
a) used in the same pattern
b) converted to test logic
c) converted to combinational logic
d) converted to asynchronous logic
Answer: c
Explanation: In this iterative test generation method, the main approach of testing is sequential logic is converted into combinational logic by cutting the feedback lines, thus creating pesudo inputs and outputs.
12. For a NAND gate, struck-at 1 fault in second input line cannot be detected if
a) Q is 1
b) Q is 0
c) Q changes from 1 to 0
d) Q changes from 0 to 1
Answer: b
Explanation: In a NAND gate, struck-at 1 fault in the second input line cannot be detected if the output Q is reset prior to applying the test sequence.
This set of VLSI Multiple Choice Questions & Answers focuses on “Guidelines for Testability -1”.
1. Practical guidelines for testability aims at
a) facilitating test generation
b) facilitating test application
c) avoiding timing problems
d) all of the mentioned
Answer: d
Explanation: Practical guidelines for testability should aim to facilitate test process in three main ways – facilitate test generation, facilitate test application and avoid timing problems.
2. When a node is difficult to access
a) sub nodes are formed
b) internal pads are added
c) external pads are added
d) circuit is sub divided
Answer: b
Explanation: When a node is difficult to access from primary input or output pads, then a very effective method is to add additional internal pads to access the desired point.
3. The additional pads are accessed using
a) probers
b) selectors
c) multiplexers
d) buffers
Answer: a
Explanation: The additional pads which are added for the access of nodes, can be accessed using probers.
4. Which provides links between blocks of a circuit?
a) combiners
b) wires
c) pads
d) nodes
Answer: d
Explanation: A node provides the link between blocks of a circuit and the attributes provide the control of the blocks.
5. To improve controllability and observability ______ is used.
a) three pads
b) eight transistors
c) three pads and eight transistors
d) four pads and eight transistors
Answer: c
Explanation: In CMOS environment, three pads and eight transistors are required to improve controllability and observability.
6. The addition of ______ improves the observability.
a) adders
b) multiplexers
c) multipliers
d) demultiplexers
Answer: d
Explanation: The addition of demultiplexers also improves observability. This arrangement allows bypassing of blocks.
7. How to reduce test time?
a) by reducing multiplexers
b) by reducing adders
c) by dividing circuit into subcircuits
d) by using the whole circuit as a single system
Answer: c
Explanation: Partitioning large circuits into smaller subcircuits is an effective way of reducing test generation complexity and test time.
8. Test generation effort for n gate circuit is proportional to
a) n
b) n 2
c) n 3
d) n 2 and n 3
Answer: d
Explanation: Test generation effort for a n gate general purpose logic circuit is proportional to n 2 and n 3 .
9. Patitioning should be made on a
a) logical basis
b) functional basis
c) time basis
d) structural basis
Answer: a
Explanation: Partitioning should be made on logical basis into recognizable and sensible subfunctions and can be done physically by incorporating clock line isolation and power supply lines.
10. Isolation and control is achieved using
a) adders
b) buffers
c) multiplexers
d) multipliers
Answer: c
Explanation: Isolation and control are better and readily achieved through the use of multiplexers.
This set of VLSI Quiz focuses on “Guidelines for Testability -2”.
1. _______ is used to start the initial sequence correctly.
a) preset
b) clear
c) preset and clear
d) clock
Answer: c
Explanation: The sequential logic testing arises at power-up time. To solve this problem and to start the initial sequence correctly, preset and clear are used.
2. Preset and clear is used to
a) initialize only first sequence
b) correct first two sequences
c) correct first and last sequence
d) correct alternative sequences
Answer: a
Explanation: Preset and clear is used to initialize only the first sequence as these are very space consuming.
3. How can over-riding the normal initialization state be achieved?
a) by adding preset
b) by adding reset
c) by adding gating in initialize control line
d) by adding sourcing in initialize control line
Answer: c
Explanation: The tester should be able to over-ride the normal initialization state of the logic and this can be achieved by the addition of gating in initialize control line.
4. Asynchronous logic is driven by
a) clock
b) gating circuit
c) self-clock
d) self timing
Answer: d
Explanation: Asynchronous logic is driven by self-timing state transition in response to changes of the primary input.
5. Which is better in terms of memory storage?
a) synchronous circuits
b) asynchronous circuits
c) sequential circuits
d) clocked circuits
Answer: a
Explanation: Synchronous circuits are better when compared to memory storage. Asynchronous circuits have a timing problems and also memory effects and problems.
6. Which circuits are faster?
a) synchronous circuits
b) asynchronous circuits
c) sequential circuits
d) clocked circuits
Answer: b
Explanation: Asynchronous circuits are inherently faster than clocked logic but it has other disadvantages like difficult testing, non deterministic behaviour, prones to races, etc.
7. Which is more sensitive logic?
a) synchronous circuits
b) asynchronous circuits
c) sequential circuits
d) clocked circuits
Answer: b
Explanation: Asynchronous circuits are more sensitive to tester skews and it is also prone to races and other hazards.
8. Which logic are difficult to design?
a) synchronous circuits
b) asynchronous circuits
c) sequential circuits
d) clocked circuits
Answer: b
Explanation: Asynchronous circuit designs are difficult than synchronous logic and must be approached with care, taking the account of critical race and other hazard-generating conditions.
9. Automatic test pattern generators depend on
a) map design
b) layout design
c) logic domain
d) testing domain
Answer: c
Explanation: Automatic test pattern generators work in logic domain and view delay-dependent logic as redundant combinational logic.
10. When a clock signal is gated with another signal like load signal, output is not affected.
a) true
b) false
Answer: b
Explanation: When a clock signal is gated with another signal such as load signal, then any skew on that signal can cause the erroneous output from associated logic.
This set of VLSI Mcqs focuses on “Guidelines for Testability -3”.
1. Counters are
a) sequential circuits
b) synchronous circuits
c) asynchronous circuits
d) buffer circuits
Answer: a
Explanation: Counters are sequential circuits and need a large number of input vectors to be fully tested.
2. Wrong readings are recorded due to reset input being
a) dependent of clock signal
b) independent of clock signal
c) dependent of gate signal
d) independent of gate signal
Answer: b
Explanation: Since reset input is independent of system clock signal, erroneous readings are being read by the tester.
3. To avoid self resetting, the tester can be over ridden by adding
a) an AND gate
b) an OR gate
c) an EX-OR gate
d) shift registers
Answer: b
Explanation: Self resetting can be avoided by adding an OR gate which over rides the tester.
4. Partitioning technique is not suitable for microprocessor like circuits.
a) true
b) false
Answer: b
Explanation: Partitioning technique is very widely used for microprocessor like circuits and using bus structures is related to partitioning technique.
5. The fast rise and fall times give cross-talk problems if
a) they are in close proximity
b) if they are far away
c) it always gives rise to croo-talk problems
d) does not allow croo-talk problems
Answer: a
Explanation: The fast rise and fall times of digital signals can give rise to croo-talk problems in analog signal lines if they are in close proximity.
6. To route digital signals near analog signals _______ must be done.
a) balancing
b) shielding digital signals
c) balancing and shielding
d) crossing
Answer: c
Explanation: To route digital signals near analog signals, balancing and shielding of digital signals must be done.
7. To access directly another system ______ is done.
a) skipping
b) alternating
c) by-passing
d) by-setting
Answer: c
Explanation: To directly access another sub-system to be tested from one subsystem, by-passing must be performed.
8. With partitioning, bypassing is performed using
a) buffers
b) multiplexers
c) multipliers
d) dividers
Answer: b
Explanation: With partitioning, to directly access a sub-system for testing, bypassing must be done and this is achieved using multiplexers.
9. Bypassing technique works well with
a) dividers
b) counters
c) RAM
d) all of the mentioned
Answer: d
Explanation: Bypassing technique works well with counters, dividers, RAM, ROM, PLAs, sequential blocks, analog circuits and internal clocks.
10. In the bypassing approach, subsystem can be tested
a) exhaustively
b) pseudo-exhaustively
c) repeatedly
d) selectively
Answer: a
Explanation: In the bypassing approach, subsystem can be tested exhaustively by controlling the multiplexers based interconnections in the system.
This set of VLSI Multiple Choice Questions & Answers focuses on “Scan Design Techniques-1”.
1. The major difficulty in sequential circuit testing is in
a) determining output
b) determining internal state
c) determining external state
d) determining input combinations
Answer: b
Explanation: The major difficulty in sequential circuit testing is in determining the internal state of the circuit.
2. The design technique helps in improving
a) controllability
b) observability
c) controllability and observability
d) overall performance
Answer: c
Explanation: The design technique are directed at improving the controllability and observability of the internal states.
3. A sequential circuit contains combinational logic and storage elements in
a) feedback path
b) output node
c) input node
d) non feedback path
Answer: a
Explanation: A sequential circuit contains combinational logic and storage elements in feedback path.
4. Storage elements in scan design technique is reconfigured to form
a) RAM
b) shift registers
c) buffers
d) amplifiers
Answer: b
Explanation: Storage elements in the scan design technique is reconfigured to form a shift register known as the scan path.
5. Storage elements used are
a) D flipflops
b) JK flipflops
c) RS flipflops
d) All of the mentioned
Answer: d
Explanation: Storage elements are usually D, JK and RS flipflop elements with the classical structure being modified by the addition of a two-way multiplexer on the data inputs.
6. The sequential circuit operates in _____ mode/modes of operation.
a) only one
b) two
c) three
d) four
Answer: b
Explanation: The sequential circuit containing the scan paths has two modes of operation a normal and a test mode.
7. The efficiency of the test pattern generation is improved by
a) adding buffers
b) adding multipliers
c) partitioning
d) adding power dividers
Answer: c
Explanation: The efficiency of the test pattern generation for the overall combinational logic circuit is improved by partitioning since its depth is reduced.
8. The scan path shift register is verified by
a) shifting in all zeroes first
b) shifting in all ones first
c) adding all ones
d) adding all zeroes
Answer: b
Explanation: Before applying test patterns, the scan path shift register is verified by shifting all ones then all zeroes.
9. In level sensitive aspect, when an input change occurs, the response in
a) dependent of components
b) dependent on wiring delays
c) independent of wiring delays
d) independent of input combinations
Answer: c
Explanation: In level sensitive aspect, when an input change occurs the response is independent of the component and wiring delays within the network.
10. In test mode, storage elements are connected as
a) parallel shift registers
b) serial shift register
c) combiners
d) buffers
Answer: b
Explanation: In the test mode, storage elements are connected as a long serial shift register.
11. Which has more number of I/O pins?
a) lssd
b) partial scan
c) scan/set
d) random access scan
Answer: d
Explanation: Random access scan method’s major disadvantage is that it has more number of I/O pins and no shift registers with flipflop are used.
12. Scan/set method has no interruption to normal operation.
a) true
b) false
Answer: a
Explanation: Scan/set method has separate shift registers and has no interruption to normal operation.
13. Which method has high over head cost?
a) lssd
b) partial scan
c) scan/set
d) random access scan
Answer: c
Explanation: Scan/set method has high overhead cost in terms of additional input/output pins.
This set of VLSI Multiple Choice Questions & Answers focuses on “Scan Design Techniques-2”.
1. The serial shift register is driven using
a) one over-lapping clock
b) two over-lapping clock
c) one non over-lapping clock
d) two non over-lapping clock
Answer: d
Explanation: The serial shift register is driven using two non over-lapping clocks which can be controlled by primary inputs of the circuit.
2. Which is used to control the scan path movement?
a) clock signals
b) input signals
c) output signals
d) delay signals
Answer: a
Explanation: Two clock signals are used to control the scan path movements through the shift register latches.
3. The circuit operation is independent of
a) rise time
b) fall time
c) propagation delays
d) all of the mentioned
Answer: d
Explanation: The circuit operation is independent of dynamic characteristics of the logic elements like rise time, fall time and propagation delays.
4. Which is not the function of LSSD method?
a) eliminates hazards
b) eliminates races
c) simplifies fault generation
d) stores the data
Answer: d
Explanation: The advantages of LSSD are that it eliminates races and hazards, simplifies fault generation and fault simulation.
5. Boundary scan test is used to test
a) pins
b) multipliers
c) boards
d) wires
Answer: c
Explanation: Boundary scan test involves scan path and self-testing to resolve the problems associated with boards carrying VLSI circuits.
6. The boundary scan path is provided with
a) serial input pads
b) parallel input pads
c) parallel output pads
d) buffer pads
Answer: a
Explanation: The boundary scan path is provided with serial input and output pads and with appropriate clock pads.
7. The boundary scan path tests the
a) input nodes
b) output nodes
c) buffer nodes
d) interconnection points
Answer: d
Explanation: The boundary scan path test the interconnection between the various chips on the board.
8. Boundary scan method takes lesser time on test pattern generation.
a) true
b) false
Answer: a
Explanation: Boundary scan method takes lesser time on test pattern generation and application.
9. The disadvantage of boundary scan method is that the fault coverage is less.
a) true
b) false
Answer: b
Explanation: The boundary scan test method is simplified and efficient and also its fault coverage is increased.
10. Which occupies a lesser area?
a) lssd
b) boundary scan test
c) serial scan
d) partial scan
Answer: d
Explanation: Partial scan is derived from scan path technique and it consumes very less area.
11. The partial scan approach scan
a) all input node faults
b) all output node faults
c) faults not detected by designer functional vector
d) all faults
Answer: c
Explanation: The partial scan approach detects faults which are not detected by the designer’s functional vectors.
12. In scan/set method __________ is used to implement a scan path.
a) serial registers
b) storage elements
c) parallel registers
d) separate register
Answer: d
Explanation: In scan/set method, storage elements are not used to implement a scan path. A separate register is added to scan test data in and out.
This set of VLSI Multiple Choice Questions & Answers focuses on “Built-in Self Test”.
1. Built-in self test aims to
a) reduce test pattern generation cost
b) reduce volume of test data
c) reduce test time
d) all of the mentioned
Answer: d
Explanation: Built-in self test objectives are to reduce test pattern generation cost, to reduce volume of test data and to reduce test time.
2. In data compression technique, comparison is done on
a) test response
b) entire test data
c) data inputs
d) output sequences
Answer: a
Explanation: In data compression technique, comparison is made on compacted test response instead on entire test data.
3. Signature analysis performs
a) addition
b) multiplication
c) polynomial division
d) amplifies
Answer: c
Explanation: Signature analysis performs polynomial division that is division of data out of the device under test.
4. The signature analysis method can be represented mathematically as
a) R = P * C
b) R = P / C
c) R = C / P
d) R = C * P
Answer: b
Explanation: The signature analysis method is represented mathematically as R = P / C where R is the signature, C is characteristic polynomial.
5. Transition counting does the count of transition only in one specific direction at a time.
a) true
b) false
Answer: a
Explanation: Transition counting does the count of transition in specified direction .
6. BILBO uses only the signature analysis.
a) true
b) false
Answer: b
Explanation: Built-in logic block observer method uses signature analysis in conjunction with a scan path.
7. In which mode, storage elements are used independently?
a) normal mode
b) test 1 mode
c) test 2 mode
d) final mode
Answer: a
Explanation: In normal mode, storage elements are used independently and in this mode signal B1=B2=1.
8. Storage elements are connected as a serial shift register when
a) B1=B2=1
b) B1=B2=0
c) B1=0, B2=1
d) B1=1, B2=0
Answer: b
Explanation: When B1=B2=0 storage elements are configured as scan path, they are connected as serial shift register.
9. The circuit is configured as LFSR, when
a) B1=B2=1
b) B1=B2=0
c) B1=0, B2=1
d) B1=1, B2=0
Answer: d
Explanation: When B1=1 and B2=0 the circuit is configured as LFSR mode and can be used as either polynomial divider or random test pattern generator.
10. The BILBO is reset, when
a) B1=B2=1
b) B1=B2=0
c) B1=0, B2=1
d) B1=1, B2=0
Answer: c
Explanation: When B1=0 and B2=1 in the final mode, the BILBO is reset.
11. Self-checking technique consists of
a) supplying coded input data
b) receiving coded output data
c) supplying all possible input sequence
d) all of the mentioned
Answer: a
Explanation: Self-checking technique consists of supplying coded input data to the logic block under test and comparing the output.
12. The type of error in self-checking technique are
a) simple error
b) unidirectional error
c) multiple error
d) all of the mentioned
Answer: d
Explanation: The type of error in self-checking techniques are simple errors, unidirectional errors and multiple errors.
13. The parity check detection is done using
a) OR gate
b) AND gate
c) XOR gate
d) NOR gate
Answer: c
Explanation: The parity check detects simple errors using XOR gates and for each type of error, the approximate coding technique is used.
14. Which errors are detected using duplication codes?
a) single errors
b) unidirectional errors
c) bidirectional errors
d) multiple errors
Answer: d
Explanation: Multiple errors are detected using duplication codes which consist of duplicating the information.
This set of VLSI Multiple Choice Questions & Answers focuses on “LFSR-1”.
1. Linear feedback shift register occupies more area.
a) true
b) false
Answer: b
Explanation: Linear feedback shift register method is more area efficient than counters and other methods and requires less combinational logic.
2. In external feedback LFSR, shift registers and feedback paths are combined using
a) OR gates
b) AND gates
c) EX-OR gates
d) NAND gates
Answer: c
Explanation: In the external feedback linear feedback shift register method, the shift registers and the feedback path are linearly combined via EX-OR gates.
3. Which uses the highest operating frequency?
a) internal feedback LFSR
b) external feedback LFSR
c) both internal and external LFSR
d) counters
Answer: a
Explanation: Internal feedback LFSR provides implementation with highest operating frequency for use in high performance application.
4. Which method has more uniformity?
a) internal feedback LFSR
b) external feedback LFSR
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: External feedback LFSR has more uniformity of the shift register and this is its main advantage.
5. The initial state in LFSR must be initialized to zero.
a) true
b) false
Answer: b
Explanation: The initial state in LFSR must be initialized to any state other than zero so that it goes through all possible states except all 0’s before repeating the sequence.
6. For n-bit LFSR, the longest possible sequence is given by
a) 2 n
b) 2 n + 1
c) 2 n – 1
d) 1/2 n
Answer: c
Explanation: For n-bit LFSR, the longest possible sequence of patterns is given by 2 n -1.
7. ______ determines the position of EX-OR gate with respect to flip-flops.
a) maximal length sequence
b) value of n
c) number of flip-flops
d) characteristic equation
Answer: d
Explanation: The placement of EX-OR gates with respect to the flip-flops in LFSR is determined using the characteristic polynomial equation.
8. The zero coefficient terms determines the number of EX-OR gates to be used.
a) true
b) false
Answer: b
Explanation: The non-zero coefficient in the characteristic polynomial expresses the EX-OR gate in the feedback network.
9. LFSR has ______
a) EX-OR gates
b) AND gates
c) OR gates
d) EX-OR and AND gates
Answer: a
Explanation: LFSR has flip-flops and EX-OR gates and counters has one EX-OR gate and AND gate per flip-flop.
10. Primitive polynomials are those
a) which has intial state zero
b) which gives maximal length sequence
c) which does not give maximal length sequence
d) which has AND gate per flip-flop
Answer: b
Explanation: Primitive polynomials are those which give maximal length sequence and those which do not give maximal length sequence are called as non-primitive polynomial.
11. In LFSR, the test patterns are repeatable.
a) true
b) false
Answer: a
Explanation: In linear feedback shift register used to produce pseudo random patterns, the patterns are deterministically generated and are repeatable.
This set of VLSI online test focuses on “LFSR-2”.
1. Primitive polynomial should have a minimum number of zero coefficient.
a) true
b) false
Answer: a
Explanation: Primitive polynomials with a minimum number of zero coefficients are the desired characteristic polynomial for the LFSR.
2. The minimum number of EX-OR gates used is in between
a) 0 to 2
b) 1 to 3
c) 2 to 5
d) 3 to 7
Answer: b
Explanation: The minimum number of EX-OR gates used for the linear feedback shift register is in between 1 and 3.
3. The LFSR takes reasonable time if the n value is
a) below 50
b) below 100
c) below 10
d) below 25
Answer: d
Explanation: The LFSR’s degree value is limited to 22 to 25 for producing maximal length sequence in reasonable amount of time.
4. Which is used to initialize the LFSRs?
a) zeroes
b) ones
c) preset of flip-flop
d) EX-OR gate
Answer: c
Explanation: The preset of each flip-flop in LFSR to used to initialize the LFSRs and initial non-zero coefficient or state ensures maximal length sequence is obtained.
5. The beginning and end of the maximal length sequence can be determined using
a) AND gate
b) NAND gate
c) AND or NAND gate
d) Both AND and NAND gate
Answer: c
Explanation: The beginning and end of the maximal length sequence of the LFSR can be determined using AND gate or NAND gate.
6. Preloading different starting value for the LFSR is called as
a) seeding
b) reseeding
c) deseeding
d) pre-seeding
Answer: b
Explanation: Initializing with a specific value to the LFSR is called as seeding and preloading different starting value is called as reseeding.
7. The primitive polynomial has a property according to which the runs of 1s ______ to runs of 0s.
a) equal
b) greater
c) lesser
d) not related
Answer: a
Explanation: The primitive polynomial has a property of randomness according to which the runs of 1s equal to runs of 0s.
8. The total number of runs is given mathematically as
a) 2 n
b) 2
c) 2
d) 2 n -1
Answer: b
Explanation: The total number of runs is given as 2 which is the total number of transitions from 1 to 0 or from 0 to 1.
9. ______ of the runs will have a length of 1.
a) one third
b) one fourth
c) half
d) one eight
Answer: c
Explanation: The length of the runs are distributed as – half of the runs have length 1, quarter with length 2, a eight length 3 and a sixteenth length 4 and so on.
10. The length of the runs is dependent on whether the LFSR is internal or external feedback.
a) true
b) false
Answer: b
Explanation: The length of the run is independent of whether the LFSR is internal or external feedback and LFSR is also known as pseudo random pattern generator.
11. Which process is used to develop the LFSR method?
a) random method
b) gaussian method
c) deterministic method
d) bernoulli method
Answer: d
Explanation: Bernoulli method is used in modelling the linear feedback shift register testing method and this is called as random pattern generation method.
This set of VLSI Multiple Choice Questions & Answers focuses on “Cellular Automata”.
1. Cellular automata produce
a) exhaustive patterns
b) exhaustive pseudo random patterns
c) random patterns
d) pseudo random patterns
Answer: d
Explanation: Cellular automata is similar to linear feedback shift register and it generates pseudo-random patterns.
2. In which method the effect of bit shifting is not observed or visible?
a) internal feedback LFSR
b) external feedback LFSR
c) cellular automata
d) counters
Answer: c
Explanation: The effect of bit shifting is not observed in cellular automata as it is done in linear feedback shift register.
3. The patterns produced using ______ is less random.
a) LFSR
b) Cellular automata
c) NAND gates
d) Shift registers
Answer: a
Explanation: The patterns produced by cellular automata is more random in nature than those produced using LFSR.
4. Which method needs more number of EX-OR gates?
a) internal feedback LFSR
b) counters
c) external feedback LFSR
d) cellular automata
Answer: d
Explanation: The construction of cellular automata is not as simple as LFSR and thus cellular automata needs more number of EX-OR gates.
5. The construction of CA register is based on
a) logical relationship of flip-flop
b) EX-OR gate
c) primitive polynomial
d) degree of the polynomial
Answer: a
Explanation: The construction of cellular automata is based on the logical relationship of each flip-flop to its two neighbours.
6. The next state for rule 150 is obtained by
a) x
b) x+x+x
c) x+x
d) x+x
Answer: b
Explanation: The next state for rule 150 is obtained by exploring three current state values – itself, previous flip-flop and next flip-flop.
7. The next state for rule 90 is obtained by
a) x
b) x+x+x
c) x+x
d) x+x
Answer: c
Explanation: The next state for rule 90 is obtained by exploring two current values – the state value of previous and the next flip-flop.
8. Which occupies lesser area?
a) internal feedback LFSR
b) external feedback LFSR
c) null condition CA
d) cyclic boundary CA
Answer: d
Explanation: The area occupied by null boundary cellular automata is comparatively lesser than that used by cyclic boundary CA.
9. The maximal length sequence is given by
a) 2 n
b) 2 n + 1
c) 2 n – 1
d) 2n
Answer: c
Explanation: The maximal length sequence is given by 2 n – 1 in null condition boundary cellular automata.
10. Rule 90 CA minimizes area when compared to rule 150.
a) true
b) false
Answer: a
Explanation: Maximizing the use of rule 90 cellular automata minimizes area overhead when compared to using rule 150 cellular automata.
This set of VLSI Multiple Choice Questions & Answers focuses on “Test Patterns”.
1. Which method is used to determine structural defects?
a) deterministic test pattern
b) algorithmic test pattern
c) random test pattern
d) exhaustive test pattern
Answer: a
Explanation: Deterministic test patterns are used to detect specific faults or structural faults for a circuit under test.
2. Which is known as the stored test pattern method?
a) deterministic test pattern
b) algorithmic test pattern
c) random test pattern
d) exhaustive test pattern
Answer: a
Explanation: Deterministic test pattern method is also known as stored test pattern method in the context of BIST applications.
3. Which method uses finite state machine for developing the test pattern?
a) deterministic test pattern
b) algorithmic test pattern
c) random test pattern
d) exhaustive test pattern
Answer: b
Explanation: Algorithmic test pattern method uses the hardware finite state machine for generating algorithmic test vectors for the circuit under test.
4. A n-bit counter produces ______ number of total input combinations.
a) 2
b) 2
c) 2 n
d) 2n
Answer: c
Explanation: A n-bit counter produces totally 2 n number of all possible input combinations for testing the circuit under test and it is called as exhaustive test pattern method.
5. Exhaustive test pattern determines
a) gate level faults
b) logic level faults
c) functional faults
d) structural faults
Answer: a
Explanation: Exhaustive test pattern method detects all gate level struck-at fault and also bridging fault.
6. Exhaustive test pattern also detects delay faults.
a) true
b) false
Answer: b
Explanation: Exhaustive test pattern method does not detect all transistor level faults or delay faults since those faults needs specific ordering.
7. Which is not suitable for circuits having large N values?
a) exhaustive test pattern method
b) pseudo-exhaustive test pattern method
c) random test pattern method
d) deterministic test pattern method
Answer: a
Explanation: Exhaustive test pattern method is not suitable for circuit having large N values since there is a limit for fault coverage.
8. Which method needs fault simulation?
a) exhaustive test pattern method
b) pseudo-exhaustive test pattern method
c) random test pattern method
d) deterministic test pattern method
Answer: a
Explanation: Exhaustive test pattern method needs fault simulation for determining fault coverage where as pseudo-exhaustive test pattern method does not need fault simulation.
9. In which method sequences are repeatable?
a) exhaustive test pattern method
b) pseudo-exhaustive test pattern method
c) random test pattern method
d) pseudo-random test pattern method
Answer: d
Explanation: Pseudo-random test pattern method have properties similar to random pattern sequence but the sequence are repeatable.
10. Which method is used for external functional testing?
a) exhaustive test pattern method
b) pseudo-exhaustive test pattern method
c) random test pattern method
d) pseudo-random test pattern method
Answer: c
Explanation: Random test pattern method is used for external functional testing of microprocessors as well as in ATPG software.
This set of VLSI Multiple Choice Questions & Answers focuses on “Counters and Finite State Machines”.
1. Counters detect only bridging faults.
a) true
b) false
Answer: b
Explanation: Counters detect gate level struck-at faults and bridging faults of the circuit under test.
2. How many test patterns are required to test the circuit using counters?
a) 2 n
b) 2
c) 2 n – 1
d) 2 n + 1
Answer: a
Explanation: A n-bit counter, generates 2 n possible test patterns which is sufficient to completely test n-bit combinational logic circuit with no feedback.
3. The desired N value for counters is
a) less than 50
b) less than 10
c) less than 25
d) less than 70
Answer: c
Explanation: The testing using counter method is practical for lesser value of N such as within 22 to 25 since for higher values of N more number of clock cycles are necessary.
4. The least significant bit toggles for
a) every clock cycle
b) every alternate clock cycle
c) every two clock cycles
d) every four clock cycles
Answer: a
Explanation: The least significant bit toggles every clock cycle and the most significant bit toggles every half way through and at the end of the count sequence.
5. Finite state machines are used for
a) deterministic test patterns
b) algorithmic test patterns
c) random test patterns
d) pseudo random test patterns
Answer: b
Explanation: Finite state machines are used for algorithmic test pattern generation testing for the circuit under test.
6. Address ordering minimizes the logic of finite state machines.
a) true
b) false
Answer: a
Explanation: Address ordering either ascending or descending order in the first and last loop minimizes the logic of finite state machines.
7. In finite state machine the data in and data out are
a) in same ports
b) different ports
c) same register
d) different register
Answer: b
Explanation: In finite state machine, there are separate ports for DATA IN and DATA OUT and this is a typical RAM structure.
8. _______ is used to control the read and write operations.
a) active low synchronous reset
b) active high synchronous reset
c) active low synchronous preset
d) active high synchronous preset
Answer: b
Explanation: With the use of active high synchronous reset read and write operations in a finite state machine can be done.
9. Finite state machine will initially set to all zeroes.
a) true
b) false
Answer: a
Explanation: Finite state machine has initial state initialized with all 0’s whereas LFSR and CA has initial state with any state other than all 0’s.
10. Fault coverage is ______ in finite state machines.
a) less
b) more
c) equal
d) none of the mentioned
Answer: b
Explanation: The fault coverage and area overhead is better when the initial state is initialized to all 0’s in finite state machine.
This set of VLSI Multiple Choice Questions & Answers focuses on “Pseudo-Random Test Patterns-1”.
1. Which exhibits low fault coverage?
a) random test pattern
b) pseudo random test pattern
c) deterministic test pattern
d) algorithmic test pattern
Answer: b
Explanation: The circuit under test exhibits low fault coverage when tested with pseudo random test generation method.
2. Large AND function will produce _______ infrequently.
a) logic 0
b) logic 0 and logic 1
c) logic 1
d) neither logic 0 or 1
Answer: c
Explanation: Large AND function produces logic 1 infrequently due to its equally likelihood of more 0’s whereas large OR function produces logic 0 infrequently.
3. The circuit which incorporates _______ can be tested with weighted pseudo-random test pattern.
a) preset
b) reset
c) clear
d) break
Answer: a
Explanation: The circuit under test which incorporates global reset or preset can be tested with pseudo-random test pattern method.
4. Circuits with global reset have fault coverage in the range of
a) 5% to 10%
b) 11% to 15%
c) 15% to 20%
d) 6% to 8%
Answer: b
Explanation: The circuit under test with global reset has fault coverage as low as 11% to 15% due to its fault detection blocking effect.
5. The probability of given bit in LFSR being logic 0 is
a) 0
b) 1
c) 0.25
d) 0.5
Answer: d
Explanation: The probability of given bit in LFSR being logic 0 is approximately 0.5 and NANDing two bits of LFSR gives probability as 0.25.
6. Initialization of the test pattern generator to all 1’s generate
a) global reset
b) clear
c) toggle
d) buffer
Answer: a
Explanation: The initialization of the test pattern generator to all 1’s generates a global reset or preset during the first test vector for the initialization of circuit under test.
7. Reset signal weight is given as
a) 2 m
b) 2
c) 2m
d) 2
Answer: b
Explanation: The rule of thumb is to make the reset signal weight as 2 where m is chosen to be greater than the sequential depth of the circuit under test.
8. The sequential depth is the number of
a) OR gates
b) AND gates
c) flip flops
d) EX-OR gates
Answer: c
Explanation: The sequential depth of the circuit under test is the number of flip flops in the longest path between primary input and output.
9. AND gate is used to ensure whether the test patterns have sufficient clock cycles.
a) true
b) false
Answer: b
Explanation: NAND gate or NOR gate helps to ensure whether the test patterns have sufficient clock cycles to propagate through the circuit under test before reset occurs.
10. Which method has more area overhead?
a) random test pattern
b) pseudo random test pattern
c) algorithmic test pattern
d) deterministic test pattern
Answer: b
Explanation: The pseudo random test pattern method has more area overhead along with increased design time. These are the limitations of this method.
This set of VLSI online quiz focuses on “Pseudo-Random Test Patterns-2”.
1. Pseudo random testing can determine the test length.
a) true
b) false
Answer: a
Explanation: Pseudo ramdom testing can also determine the relationship between test confidence, fault coverage, fault detectability and test length can also be determined.
2. The pseudo-random testing has
a) high cost
b) less development time
c) low cost but more testing time
d) low cost and less testing time
Answer: b
Explanation: Pseudo random testing method has less development time and low development cost. This can be balanced with increased test length.
3. In pseudo-random testing, the test length should be ________ the exhaustive test.
a) lesser than
b) greater than
c) more than
d) none of the mentioned
Answer: a
Explanation: In pseudo-random testing, the test length should be less than that of the exhaustive test or the test length will be prohibited for most circuits. This makes the pseudo-random testing practical.
4. Pseudo-random testing method involves
a) homogeneous bernoulli process
b) non homogeneous bernoulli process
c) repeatable bernoulli process
d) non repeatable bernoulli process
Answer: b
Explanation: The most accurate method invlolved in test pattern generation is non homogeneous bernoulli process. This is called as pseudo random testing method.
5. Which method is more accurate?
a) pseudo-random testing
b) random testing
c) LFSR
d) cellular automata
Answer: a
Explanation: Pseudo-random testing method gives more accurate results than random testing method. Its test length estimation is smaller and test quality is better.
6. The fault coverage in a pseudo random test is determined using
a) fault detection
b) fault removal
c) fault simulation
d) fault distribution
Answer: c
Explanation: The fault coverage in a pseudo random test can be determined by using fault simulation. The fault coverage is the measure used to rate the algorithmically generated test set.
7. Faults causing largest loss of coverage is those with
a) smallest detectability
b) largest detectability
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: Faults causing largest loss of coverage is those with smallest detectability. These faults are counted in the initial nonzero elements of the detectability profile.
8. With a test sequence of length zero, fault coverage is
a) maximum
b) 1
c) 0
d) cannot be determined
Answer: c
Explanation: With test sequence of length zero, the fault coverage is 0 and each fault is responsible for fault coverage loss regardless of its detectability.
9. Upper bound fault is the fault with detectability
a) 0
b) 1
c) maximum
d) minimum
Answer: b
Explanation: Upper bound fault is the fault with detectability k=1 and it is used where the detectability profile of the circuit under test is unknown.
10. To reduce the size mismatch, test length is minimized.
a) true
b) false
Answer: a
Explanation: If the size of pseudo-random test generator does not match with the size of the circuit under test, size mismatch occurs. This can be compromised by reducing the test length.
This set of VLSI Multiple Choice Questions & Answers focuses on “Test Pattern Generators”.
1. The test pattern generator which uses a shift register along with LFSR is of __________ bits.
a) N
b) M
c) N+M
d) N*M
Answer: c
Explanation: The test pattern generator which uses a M-bit shift register with N-bit LFSR, the test pattern generator is of N+M bits.
2. The N+M bit test pattern generator has __________ different patterns produced.
a) 2
b) 2 N +M
c) 2N M
d) 2 M+N
Answer: b
Explanation: The N+M bit test pattern generator can produce a maximum of 2 N+M possible different patterns during its first cycle.
3. Which property can prevent high fault coverage?
a) fault limit
b) clock fault
c) linear interloading
d) linear dependencies
Answer: d
Explanation: The test pattern generated in this method will contain an additional property called linear dependencies that can prevent high fault coverage in some circuits.
4. __________ are used along with flip-flops to build accumulators.
a) adders
b) multipliers
c) buffers
d) AND gates
Answer: a
Explanation: Adders can be used in conjunction with the flip-flops to construct an accumulator that functions in test pattern generators.
5. What is the desirable constant value to be used with the initial values?
a) 0
b) 1
c) N
d) M
Answer: b
Explanation: The constant value 1 can always be used with any initial value for a register to ensure that the accumulator increments through all combinations of test patterns.
6. Which can be used to check the working of accumulator?
a) adder
b) shifter
c) multiplier
d) counter
Answer: d
Explanation: Counter would be more area efficient in testing whether accumulator increments through all combinations.
7. Test patterns produced by ________ have both high and least toggle rates.
a) random pattern generator
b) counters
c) LFSR
d) CA
Answer: b
Explanation: Test patterns generated by counters have least and high toogle rates of the least and most significant bits respectively.
8. Which method does not have carry out?
a) LFSR
b) CA
c) Counters
d) Random sequence generator
Answer: c
Explanation: The counter is a 8-bit binary up counter with active high count enable but with no carry out.
9. Which method is easiest to test?
a) LFSR
b) Counter
c) CA
d) Weighted LFSR
Answer: a
Explanation: LFSR method is the most area efficient method and is also the easiest method to test. This is its most important advantage.
10. Which requires more number of cycles for 100% fault coverage?
a) internal feedback LFSR
b) external feedback LFSR
c) weighted LFSR
d) ca
Answer: b
Explanation: External feedback LFSR takes more number of cycles for 100% fault coverage than internal feedback LFSR and CA methods.
11. The detectability profile can be determined using
a) D algorithm
b) Cellular automata
c) LFSR
d) Random testing
Answer: a
Explanation: The detectability of every fault in the circuit fault is needed for better testing. To determine this detectability profile, D algorithm is used which gives accurate results.
This set of VLSI Multiple Choice Questions & Answers focuses on “Automatic Test Pattern Generation”.
1. Automatic test pattern generator detects only the fault and not its cause.
a) true
b) false
Answer: b
Explanation: The test patterns generated using automatic test pattern generator is used to detect the faults and in some cases it assists in finding the cause of the failure too.
2. The automatic test pattern generator method has ________ phases.
a) two
b) three
c) four
d) five
Answer: a
Explanation: The automatic test pattern generator method has two phases – fault activation and fault propogation phase.
3. Faults which produce same faulty behaviour are known as
a) similar faults
b) equivalent faults
c) correlative faults
d) ambiguous faults
Answer: b
Explanation: Two or more faults may produce same faulty behaviour for all input patterns and these faults are known as equivalent faults.
4. The process of removing equivalent faults is called as
a) equivalent removing
b) bulk damaging
c) fault collapsing
d) fault reduction
Answer: c
Explanation: The process of removing equivalent faults from the entire set of faults is called as fault collapsing. Any single fault from the whole set of equivalent faults can represent it.
5. ‘n’ signal lines can potentially have _____ stuck-at faults.
a) n 2
b) 2n
c) n
d) n/2
Answer: b
Explanation: If a circuit has n signal lines, then potentially it can have 2n stuck-at faults defined on the circuit.
6. The stuck-at model is a _____ fault model.
a) recurring
b) equivalent
c) simple
d) logical
Answer: d
Explanation: The stuck-at model is a logical fault model because no delay information is associated with the fault definition.
7. Stuck-at fault is an example of ______ fault model.
a) transient
b) permanent
c) intermittent
d) simple
Answer: b
Explanation: Stuck-at fault model is also called a permanent fault model because the faulty effect is assumed to be permanent.
8. Transient faults does not depend on operating condition.
a) true
b) false
Answer: b
Explanation: Transient faults occur sporadically depending on operating condition and on the data values on surrounding signal lines.
9. The _________ between two signal is called as bridging fault.
a) open circuit
b) break
c) connection
d) short circuit
Answer: d
Explanation: A short circuit between two signal lines is called as bridging fault and it is similar to stuck-at fault model.
10. The sum of all propagation delays along a single path is given as
a) gate delay fault
b) transition fault
c) path delay fault
d) propagation fault
Answer: c
Explanation: Path delay fault is given as the sum of all propagation faults along a single path. This fault shows that delay of one or more path exceeds the clock period.
11. Which method is more complex?
a) stuck at fault
b) CA
c) combinational ATPG
d) sequential ATPG
Answer: d
Explanation: Sequential automatic test pattern generation method is more complex and remains a complex task for large highly sequential circuits.
This set of VLSI Multiple Choice Questions & Answers focuses on “Fault Models”.
1. Which are processing faults?
a) missing contact window
b) parasitic transistor
c) oxide breakdown
d) all of the mentioned
Answer: d
Explanation: Some of the real defects in chip such as processing faults are missing contact window, parasitic transistor and oxide breakdown.
2. Surface impurities occurs due to ion migration.
a) true
b) false
Answer: a
Explanation: Some of the material defects are bulk defects and surface impurities. Bulk defects are cracks and crystal imperfection and surface impurities occurs due to ion migration.
3. Electromigration is a
a) processing fault
b) material defects
c) time dependent failure
d) packaging fault
Answer: c
Explanation: Different types of real defects in chips are processing fault, material defects, time dependent failure and packaging fault. Time dependent failures are dielectric breakdown and electromigration.
4. Which relation is correct?
a) failure – error – fault
b) fault – error – failure
c) error – fault – failure
d) error – failure – fault
Answer: b
Explanation: The relation fault – error – failure is correct. Error is caused by faults and failure which is a deviation of the circuit is caused by error.
5. For a circuit with k lines __________ single stuck-at fault is possible.
a) k
b) 2k
c) k/2
d) k 2
Answer: b
Explanation: For a circuit with k lines, 2k single stuck-at faults are possible and 3^k – 1 multiple stuck-at faults are possible.
6. Single stuck-at fault is technology independent.
a) true
b) false
Answer: a
Explanation: Single stuck-at fault is technology independent. It can be applied to TTL, CMOS etc. It is also design style independent.
7. For a n signal lines circuit _____________ bridging faults are possible.
a) n
b) 2n
c) n 2
d) n/2
Answer: c
Explanation: For circuit with n lines, n 2 bridging faults are possible. Bridging fault occurs when two lines are connected when they should not be connected. It leads to wired AND or wired OR.
8. IDDQ fault occurs when there is
a) increased voltage
b) increased quiescent current
c) increased power supply
d) increased discharge
Answer: b
Explanation: When input is low, both P and N transistors are conducting causing increase in quiescent current which leads to IDDQ fault.
9. Which fault causes output floating?
a) stuck-open
b) stuck-at
c) stuck-on
d) IDDQ
Answer: a
Explanation: Transistor with stuck-open fault causes output floating. Stuck-open faults requires two vector tests.
10. Data retention time comes under __________ fault.
a) functional fault
b) memory fault
c) parametric fault
d) structural fault
Answer: c
Explanation: One of the memory faults is a parametric fault. Some of the parametric faults are noise margin, data retention time, power consumption, output levels, etc.
11. In PLA, missing cross point in OR-array leads to
a) OR fault
b) growth fault
c) missing fault
d) disappearance fault
Answer: d
Explanation: In PLA, missing cross point in AND array leads to growth fault and missing cross point in OR-array leads to disappearance fault.
12. In PLA, extra crosspoint in AND-array leads to
a) OR fault
b) growth fault
c) missing fault
d) disappearance fault
Answer: d
Explanation: In PLA, extra crosspoint in AND-array leads to shrinkage or disappearance fault whereas extra crosspoint in OR-array leads to appearance fault.
13. The number of paths ___________ with number of gates.
a) increases exponentially
b) decreases exponentially
c) remains the same
d) increases rapidly
Answer: a
Explanation: The number of paths increases exponentially with number of gates. Propagation delay of the path exceeds the clock interval.
14. The quality of the test set is measured by
a) fault margin
b) fault detection
c) fault correction
d) fault coverage
Answer: d
Explanation: The quality of a test set is measured by its fault coverage. It gives the fraction of fault that are detected by the test set.
This set of VLSI Multiple Choice Questions & Answers focuses on “Design for Testability”.
1. Design for testability is considered in production for chips because:
a) Manufactured chips are faulty and are required to be tested
b) The design of chips are required to be tested
c) Many chips are required to be tested within short interval of time which yields timely delivery for the customers
d) All of the mentioned
Answer: c
Explanation: Design for testability is considered in production for chips because many chips are required to be tested within short interval of time which yields timely delivery for the customers.
2. The functions performed during chip testing are:
a) Detect faults in fabrication
b) Detect faults in design
c) Failures in functionality
d) All of the mentioned
Answer: d
Explanation: The functions performed during chip testing are detecting faults in fabrication and design failures in functionality.
3. ATPG stands for:
a) Attenuated Transverse wave Pattern Generation
b) Automatic Test Pattern Generator
c) Aligned Test Parity Generator
d) None of the mentioned
Answer: b
Explanation: ATPG is an Automatic Test Pattern Generator.
4. Delay fault is considered as:
a) Electrical fault
b) Logical fault
c) Physical defect
d) None of the Mentioned
Answer: b
Explanation: Delay fault is considered a logical fault.
5. A metallic blob present between drain and the ground of the n-MOSFET inverter acts as:
a) Physical defect
b) Logical fault as output is stuck on 0
c) Electrical fault as resistor short
d) All of the mentioned
Answer: d
Explanation: A metallic blob present between drain and the ground of the n-MOSFET inverter acts as Physical defect, Logical fault as output is stuck on 0, Electrical fault as resistor short.
6. High resistance short present between drain and ground of n-MOSFET inverter acts as:
a) Pull up delay error
b) Logical fault as output is stuck at 1
c) Electrical fault as transistor stuck on
d) All of the mentioned
Answer: a
Explanation: High resistance short present between drain and ground of n-MOSFET inverter acts as Pull up delay error.
7. The defect present in the following MOSFET is:
vlsi-questions-answers-design-testability-q7
a) Logical stuck at 1
b) Logical stuck at 0
c) Physical defect
d) Electrical Transistor stuck open
Answer: d
Explanation: The dimensions of the gate is less than the distance between source and drain.
8. The fault simulation detects faults by:
a) Test generation
b) Construction of fault Dictionaries
c) Design analysis under faults
d) All of the mentioned
Answer: d
Explanation: None.
9. The ease with which the controller establishes specific signal value at each node by setting input values is known as:
a) Testability
b) Observability
c) Controllability
d) Manufacturability
Answer: c
Explanation: Controllability is defined as the ease with which the controller establishes specific signal value at each node by setting input values.
10. The ease with which the controller determines signal value at any node by setting input values is known as:
a) Testability
b) Observability
c) Controllability
d) Manufacturability
Answer: b
Explanation: Observability is defined as the ease with which the controller determines signal value at any node by setting input values.
11. The poor controllability circuits are:
a) Decoders
b) Clock generators
c) Circuits with feedback
d) All of the mentioned
Answer: d
Explanation: None.
12. The circuits with poor observability are:
a) ROM
b) PLA
c) Sequential circuits with long feedback loops
d) All of the mentioned
Answer: c
Explanation: None.
13. Large number of input vectors are used to set a particular node or , to propagate an error at the node to output makes the circuit low on:
a) Testability
b) Observability
c) Controllability
d) All of the mentioned
Answer: a
Explanation: The circuit is said to be low on Testability if large number of input vectors are used to set a particular node or , to propagate an error at the node to output.
14. Divide and Conquer approach to large and complex circuits for testing is found in:
a) Partition and Mux Technique
b) Simplified automatic test pattern generation technique
c) Scan based technique
d) All of the mentioned
Answer: a
Explanation: Divide and Conquer approach to large and complex circuits for testing is found in the partition and Mux technique.
15. LSSD stands for:
a) Linear system synchronous detection
b) Level sensitive system detection
c) Level sensitive scan design
d) Level sensitive scan detection
Answer: c
Explanation: None.
This set of VLSI Multiple Choice Questions & Answers focuses on “Submicron CMOS”.
1. Submicron CMOS technology is
a) faster
b) slower
c) large
d) slow and large
Answer: a
Explanation: Submicron CMOS technology is faster small and device dimensions are closely interrelated.
2. In CMOS devices, which has slower performance?
a) n-transistor
b) p-transistor
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: In CMOS devices, p-transistors have inherently slower performance than similar n-transistors and this is due to lower mobility of holes compared with that of the electrons.
3. As the channel length is scaled down, influence of mobility
a) increases
b) decreases
c) remains the same
d) does not affect
Answer: b
Explanation: As the channel lengths are scaled down, the influence of mobility starts to diminish as the effects of velocity saturation begin to be felt.
4. Current drive is ______ to mobility.
a) directly proportional
b) inversely proportional
c) logarithmically proportional
d) exponentially proportional
Answer: a
Explanation: Current drive is directly proportional to mobility and inversely proportional to the channel length L.
5. When velocity saturation occurs, Idsat is ______ to Vsat.
a) inversely proportional
b) directly proportional
c) logarithmically proportional
d) not related
Answer: b
Explanation: When velocity saturation occurs, drive current saturation Idsat is directly related to saturation velocity. It is given as Idsat = W*Cox*Vsat*.
6. Current is dependent on ________ when saturation velocity occurs.
a) mobility
b) channel length
c) saturation velocity
d) transconductance
Answer: c
Explanation: When saturation velocity occurs, current becomes independent of mobility and the channel length and it is dependent on only saturation velocity.
7. Transconductance is independent of
a) channel width
b) channel length
c) material
d) channel depth
Answer: b
Explanation: Transconductance is a constant and it independent of the channel length. Current is independent of mobility and channel length.
8. Velocity saturation occurs at
a) lower electric field strength in n-devices
b) higher electric field strength
c) intermittent electric field strength
d) lower electric field strength in p-devices
Answer: a
Explanation: Velocity saturation occurs at lower electric field strengths in n-devices owing to their higher mobility when compared with p-devices.
9. When dimensions are scaled down ______ tends to a constant value.
a) current drive from p-transistors
b) current drive from n-transistors
c) voltage drive from p-transistors
d) voltage drive from n-transistors
Answer: b
Explanation: When dimensions are scaled down, current drive from n-transistors tends to a constant value independent of channel length.
10. At ______ length, the holes start to run into velocity saturation.
a) shorter
b) larger
c) all of the mentioned
d) none of the mentioned
Answer: a
Explanation: At shorter length, the holes start to run into velocity saturation and the current drive from p-transistors does not tend to a constant value.
11. ______ technology is used to provide for faster devices.
a) silicon based FET technology
b) silicon based MOS technology
c) gallium arsenide based MOS technology
d) gallium arsenide based VLSI technology
Answer: d
Explanation: Gallium arsenide based VLSI technology is used to provide for the faster devices which will be required as the sophistication of our system design capabilities.
12. Silicon logic is faster than gallium arsenide.
a) true
b) false
Answer: b
Explanation: Silicon logic has speed limitations that are becoming apparent in the state-of-the-art fast digital system design.
13. ________ is used with silicon to satisfy the need for very high speed integrated technology.
a) gallium oxide
b) gallium arsenide
c) silicon dioxide
d) aluminium
Answer: b
Explanation: Gallium arsenide is used in conjunction with silicon to satisfy the need for very high speed integrated technology in many new systems.
This set of VLSI Multiple Choice Questions & Answers focuses on “Gallium Arsenide VLSI”.
1. Gallium arsenide has _______ electron mobility.
a) high speed
b) low speed
c) smaller
d) larger
Answer: a
Explanation: The high speed electron mobility of gallium arsenide with respect to silicon is better for innovative systems.
2. Which technology has semi-insulating substrate?
a) silicon
b) silicon nitride
c) gallium oxide
d) gallium arsenide
Answer: d
Explanation: Gallium arsenide has semi-insulating substrate with consequent lower parasitics which improves its opto-electrical properties.
3. Gallium is produced as a byproduct of
a) aluminium production process
b) sulphur production process
c) nitrogen production process
d) oxygen production process
Answer: a
Explanation: Gallium which is a toxic material is produced as a byproduct of zinc production process and aluminium production processes.
4. Arsenic is produced from
a) AsS3
b) As2S3
c) As2S
d) As2S3 or As2S4
Answer: d
Explanation: Arsenic which is also very toxic material is produced from the ores such as As2S3 or As2S4.
5. The first process involved in the production of arsenic is
a) reduction
b) oxidation
c) combination
d) diffusion
Answer: b
Explanation: Firstly, the ores go through the oxidation process and then reduction with carbon is done to produce arsenic.
6. Gallium has a
a) positively charged nucleus +31
b) positively charged nucleus +33
c) negatively charged nucleus -31
d) negatively charged nucleus -33
Answer: a
Explanation: Gallium has a positively charged nucleus of +31 whereas arsenic has positively charged nucleus of +33.
7. Energy level of electrons are dictated by
a) electron’s charges
b) electron’s momentum
c) electron’s mass
d) electron’s weight
Answer: b
Explanation: Each electron in its relationship with its parent nucleus exhibits an energy value. This energy is dictated by electron’s momentum and its physical proximity to the nucleus.
8. The energy is greater as closer the electron is to the nucleus.
a) true
b) false
Answer: a
Explanation: The closer the electron is to the nucleus the greater is the holding influence of the nucleus and greater is the energy required for the electron to break loose and become free.
9. Which are more stronger?
a) outer orbit electrons
b) outer orbit protons
c) inner orbit electrons
d) inner orbit protons
Answer: a
Explanation: Outer orbit electrons are said to be stronger than inner orbit electrons because of their ability to break loose from the parent atom. These are called as valence electrons.
10. Gallium arsenide is made up of
a) single element
b) compound of two elements
c) compound of three elements
d) compound of four elements
Answer: b
Explanation: Gallium arsenide is a compound semiconductor that is defined as a compound of two elements whereas silicon is a single element semiconductor.
11. Gallium has ______ valence electrons.
a) two
b) three
c) four
d) five
Answer: b
Explanation: Gallium has three valence electrons and arsenic has five valence electrons. These two are combined to form gallium arsenide.
12. Gallium arsenide is a
a) binary semiconductor
b) trinary semiconductor
c) ternary semiconductor
d) unary semiconductor
Answer: a
Explanation: Gallium arsenide is a binary semiconductor and high temperatures should be avoided which might result in dissociation of the surface.
This set of VLSI Multiple Choice Questions & Answers focuses on “Doping Process of GA-1”.
1. Addition of impurities is essential for creating switching devices.
a) true
b) false
Answer: a
Explanation: It is necessary to introduce impurities into the semi-insulating GaAs to facilitate the creating of switching devices.
2. The behaviour of the switching element is decided by
a) selection of impurity
b) concentration density
c) selection of impurity & concentration density
d) none of the mentioned
Answer: c
Explanation: Selection of the impurity and its concentration density determines the behaviour of the switching element.
3. ______ elements can act as either donors or acceptors.
a) group II
b) group III
c) group IV
d) group V
Answer: c
Explanation: Group IV elements such as silicon can act as either donor or as acceptors .
4. Which element is smaller?
a) arsenic
b) gallium
c) silicon
d) aluminium
Answer: a
Explanation: Arsenic is smaller than gallium and silicon. The covalent radius of Ga is 1.26 armstrong unit whereas for As is 1.18 armstrong unit.
5. ______ is used as the dopant for the formation of n-type material.
a) aluminum
b) arsenic
c) silicon
d) gallium
Answer: c
Explanation: Group IV impurities tend to occupy gallium sites. Silicon is used as the dopant for the formation of n-type material.
6. Increase in positive charge ___________ the effective nuclear charge.
a) increases
b) decreases
c) exponentially increases
d) does not affect
Answer: a
Explanation: Increase in positive charge of the nucleus results in an increase in the effective nuclear charge thereby increasing the effective atomic radius.
7. ___________ is used for the formation of p-type material.
a) beryllium
b) magnesium
c) beryllium and magnesium
d) aluminium
Answer: c
Explanation: Group II elements such as beryllium and magnesium can be used for the formation of p-type materials.
8. Which is the lightest p-type dopant?
a) beryllium
b) magnesium
c) silicon
d) arsenic
Answer: a
Explanation: Beryllium is the lightest p-type dopant for GaAs, deep implantation of the dopant atoms can be accomplished with less lattic damage.
9. _______ influences the properties of GaAs field affect transistor.
a) length dependency
b) structural dependency
c) material dependency
d) orientation dependency
Answer: d
Explanation: Orientation dependency influences the properties of GaAs field effect transistors. Factors like etching of the crystal, ion implantation and passivation introduces the concept of orientation dependency.
10. The ion is steered ________ of the lattice.
a) up the open directions
b) down the open directions
c) up the closed directions
d) down the closed directions
Answer: b
Explanation: When a high energy ion enters a single crystal lattice, the ion is steered down the open directions of the lattice. This steering is called axial channeling.
11. If equivalent direction is not used ______ will be increased.
a) ion concentration
b) steering angle
c) area coverage
d) depth distribution
Answer: d
Explanation: If a random equivalent direction is not used during ion implantation, the depth distribution will be greater than those predicted by range statistics which are used to establish penetration depth.
12. Electrons become hot in gallium arsenide when the energy of
a) lower valley electrons decreases
b) lower valley electrons rises
c) higher valley electrons decreases
d) higher valley electrons rises
Answer: b
Explanation: In gallium arsenide, when the energy of lower valley electrons rises sufficiently at a higher electric field, the electrons become hot.
13. When electrons become hot, drift velocity
a) increases
b) decreases
c) remains the same
d) does not depend on drift velocity
Answer: b
Explanation: When electrons becomes hot, there will be a reduction in the number of high mobility electrons and hence decrease in drift velocity.
This set of VLSI Question Bank focuses on “Doping Process of GA-2”.
1. ______ is a direct gap material with valence bond maximum.
a) silicon
b) gallium oxide
c) gallium arsenide
d) silicon arsenide
Answer: c
Explanation: Gallium arsenide is a direct gap material with valence bond maximum and conduction band minimum.
2. Narrow valleys correspond to
a) electrons with lower mass state
b) protons with lower mass state
c) electrons with higher mass state
d) protons with higher mass state
Answer: a
Explanation: Valleys with band structure that are narrow and sharply curved corresponds to electrons with low effective mass state while valleys that are wide are characterized by larger effective masses.
3. The curvature of ___________ determines the effective mass of electrons.
a) energy versus concentration
b) energy versus mass
c) energy versus momentum
d) energy versus structural design
Answer: c
Explanation: The curvature of energy versus electron momentum profile determines the effective mass of electrons travelling through the crystal.
4. Conduction band minimum occurs at
a) low momentum
b) high momentum
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: The minimum point of gallium arsenide’s conduction band is near the zero point of the crystal-lattice momentum. Conduction band minimum occurs at high momentum.
5. Mobility depends on
a) concentration of impurity
b) temperature
c) electron efficient mass
d) all of the mentioned
Answer: d
Explanation: Mobility depends on several factors such as concentration of impurity, temperature and is relatively related to electron efficient mass.
6. The effective mass of GaAs is _________ than the mass of a free electron.
a) 0.67 times greater
b) 0.67 times lesser
c) 0.067 times greater
d) 0.067 times lesser
Answer:c
Explanation: For GaAs, the effective mass of these electrons is 0.067 times the mass of a free electron.
7. Electrons travels faster in
a) silicon
b) gallium arsenide
c) aluminium
d) silicon oxide
Answer: b
Explanation: Electrons travel faster in gallium arsenide than in silicon as the result of their superior electron mobility brought out by the shapes of their conduction bands.
8. Electrons is low valley have high mass.
a) true
b) false
Answer: b
Explanation: Electrons in the higher valleys have high mass and strong intervalleys scattering and therefore exhibit very low mobility.
9. The probability of photon emission has energy which is _______ the band gap.
a) greater than
b) lesser than
c) equal to
d) does not depend on
Answer: c
Explanation: The probability of photon emission with energy nearly equal to the band gap is high, GaAs makes an excellent light-emitting diode.
10. Silicon can also be used as light-emitting device.
a) true
b) false
Answer: b
Explanation: Silicon cannot be used as light-emitting device. It is indirect-gap semiconductor with the conduction gap minimum separated in momentum from valence band minimum.
11. As the applied field increases
a) drift velocity increases
b) energy decreases
c) drift velocity remains constant
d) energy remains constant
Answer: a
Explanation: As long as the resultant balance is positive, the energy and drift velocity of the charge carriers increases with an increase in the applied field.
12. Saturation velocity is attained when
a) energy gained is greater than energy lost
b) energy lost is greater than energy gained
c) energy gained equals energy lost
d) energy is fully drained
Answer: c
Explanation: The energy gained from the field equals the energy lost as a result of collisions. At this point, drift velocity attains a limiting value called saturation velocity.
This set of VLSI Multiple Choice Questions & Answers focuses on “Technology Development in VLSI Structures-1 “.
1. The GaAs fabrication has _________ gate geometry.
a) less than one micron
b) less than two micron
c) more than one micron
d) more than two micron
Answer: a
Explanation: The GaAs fabrication has characteristics such as having less than on-micron gate geometry and less than two-micron metal pitch.
2. The GaAs structure has upto _______ metal.
a) two-layer
b) three-layer
c) four-layer
d) one-layer
Answer: c
Explanation: The GaAs fabrication has the feature of having four-layer metal and four-inch diameter wafer.
3. Electron mobility of gallium arsenide is _______ that of silicon.
a) greater than
b) lesser than
c) same as
d) does not depend on
Answer: a
Explanation: Electron mobility of gallium arsenide is six to seven times that of silicon resulting in very fast electron transit times.
4. Saturated drift velocity of gallium is _______ to that of silicon.
a) greater
b) lesser
c) approximately same
d) does not depend on
Answer: c
Explanation: Saturated drift velocity of gallium and silicon are approximately equal. For GaAs saturation velocity occurs at a lower threshold field than for silicon.
5. Larger energy bandgap _____ parasitic capacitances.
a) increases
b) decreases
c) maintains constant
d) does not affect
Answer: b
Explanation: Large energy bandgap offers bulk semi-insulating substrate and minimizes parasitic capacitances and allows easy electrical isolation.
6. In gallium arsenide, radiation resistance is
a) stronger
b) weaker
c) absent
d) very weak
Answer: a
Explanation: In gallium arsenide radiation resistance is stronger due to the absence of gate oxide to trap charges.
7. In gallium arsenide, wider operating temperature range is possible.
a) true
b) false
Answer: a
Explanation: In gallium arsenide, wider operating temperature range is possible due to the larger bandgap. GaAs devices are tolerant to wide temperature variations.
8. _______ can be used as light emitters.
a) forward biased pn junction
b) reverse biased pn junction
c) forward biased pnp junction
d) reverse biased pnp junction
Answer: a
Explanation: Direct bandgap of GaAs allows efficient radiative recombination of electrons and holes and thus forward biased pn junction can be used as light emitters.
9. In GaAs __________ has more intrinsic mobility.
a) electron
b) holes
c) proton
d) neutron
Answer: a
Explanation: In GaAs, electrons have intrinsic mobility of 8000 cm^2/V.sec whereas in silicon holes has more intrinsic mobility as 500 cm 2 /V.sec.
10. Which has greater intrinsic resistivity?
a) silicon
b) gallium arsenide
c) gallium
d) silicon and gallium
Answer: b
Explanation: Gallium arsenide has greater intrinsic resistivity of 1×10 8 ohm.cm whereas silicon has intrinsic resistivity of 2.2×10 5 ohm.cm.
11. Silicon has a greater density than GaAs.
a) true
b) false
Answer: b
Explanation: GaAs has greater density than silicon. Density of silicon is 2.33 gm/cm 3 whereas for GaAs it is 5.32 gm/cm 3 .
12. Which has low breakdown field?
a) silicon
b) GaAs
c) gallium
d) silicon and gallium
Answer: a
Explanation: Silicon has low breakdown field in the range of 3×10 5 V/cm whereas for GaAs it is 4×10 5 V/cm.
13. Which has greater effective electron mass?
a) silicon
b) GaAs
c) free electron
d) gallium
Answer: a
Explanation: Silicon has a greater effective electron mass than GaAs. Silicon has electron mass in the range of 0.97 times the mass of free electron.
This set of VLSI Questions and Answers for Entrance exams focuses on “Technology Development in VLSI Structures-2”.
1. Which has low power dissipation?
a) CMOS
b) bipolar
c) GaAs
d) NMOS
Answer: a
Explanation: CMOS has low power dissipation whereas bipolar has high and GaAs has medium power dissipation.
2. Which device has low input impedance?
a) CMOS
b) bipolar
c) GaAs
d) NMOS
Answer: b
Explanation: Bipolar transistor has low input impedance and high drive current whereas CMOS and GaAs has high input impedance.
3. Which device has low noise margin?
a) CMOS
b) bipolar
c) GaAs
d) NMOS
Answer: c
Explanation: GaAs has low noise margin whereas bipolar has medium noise margin. CMOS has high noise margin than the other two devices.
4. ______ has high packing density.
a) CMOS
b) bipolar
c) GaAs
d) CMOS and GaAs
Answer: d
Explanation: CMOS and GaAs has high packing density whereas bipolar transistors have low packing density than CMOS and GaAs.
5. Which has low delay sensitivity to load?
a) CMOS
b) bipolar
c) GaAs
d) CMOS and GaAs
Answer: b
Explanation: Bipolar transistors have low delay sensitivity to load and fan-out whereas CMOS and GaAs have high delay sensitivity to load, fan-in and fan-out.
6. Which is direct band-gap semiconductor?
a) CMOS
b) bipolar
c) GaAs
d) bipolar and GaAs
Answer: c
Explanation: GaAs is direct band-gap semiconductor and can be used as good light-emitter whereas CMOS and bipolar are indirect band-gap semiconductors.
7. Factors significant in high speed semiconductors are
a) carrier mobility
b) carrier saturation velocity
c) existence of semi-insulating substrate
d) all of the mentioned
Answer: d
Explanation: FOr very high speed operation in a semiconductor medium, three factors are significant – carrier mobility, carrier saturation velocity and existence of semi-insulating substrate.
8. MESFET is a gallium arsenide device.
a) true
b) false
Answer: a
Explanation: Depletion mode and enhancement mode metal semiconductor field-effect transistor are gallium arsenide devices.
9. Second generation gallium arsenide device are
a) high electron mobility transistor
b) heterojunction bipolar transistor
c) high electron mobility & heterojunction bipolar transistors
d) none of the mentioned
Answer: c
Explanation: High electron mobility transistor and heterojunction bipolar transistor are second generation gallium arsenide devices.
10. Switching delays of GaAs is in the range of
a) 40-50
b) 20-30
c) 100-120
d) 70-80
Answer: d
Explanation: GaAs exhibits switching delays as low as 70 to 80 psec for a low power dissipation.
11. Which device has very high speed?
a) CMOS
b) FET
c) GaAs
d) MESFET
Answer: c
Explanation: GaAs device has very high speed and low voltage swing. Bipolar device is faster than CMOS and bit slower when compared to GaAs.
12. Which has high output drive?
a) Bipolar
b) CMOS
c) FET
d) pnp
Answer: a
Explanation: Bipolar transistor has high output drive. Whereas CMOS and GaAs has lower output drive comparatively.
13. In bipolar device, the relationship of gm and Vin can be described as
a) directly related
b) exponentially related
c) inversely related
d) logarithmically related
Answer: b
Explanation: In bipolar device, gm is exponentially related to Vin. Mathematically it can be expressed as gm is proportional to e^.
14. Which is unidirectional device?
a) Bipolar
b) CMOS
c) FET
d) pnp
Answer: a
Explanation: Bipolar device is a unidirectional device whereas CMOS and GaAs devices are bidirectional devices.
This set of VLSI Multiple Choice Questions & Answers focuses on “MESFET”.
1. The gallium arsenide field effect transistor is ________ majority carrier device.
a) bulk current insulation
b) bulk current conduction
c) bulk voltage insulation
d) bulk voltage conduction
Answer: b
Explanation: The gallium arsenide field effect transistor is a bulk current-conduction majority carrier device and is fabricated from bulk gallium arsenide.
2. Method used for fabrication of GaAs FET is
a) ion implantation
b) disposition
c) diffusion
d) conduction
Answer: a
Explanation: The methods used for fabrication of gallium arsenide field effect transistors are high-resolution photolithography and ion implantation.
3. How many masking stages does fabrication of GaAs FET require?
a) five
b) four
c) ten
d) eight
Answer: d
Explanation: The fabrication of GaAs field effect transistor requires six to eight masking stages and processing is relatively simple.
4. Which region is heavily doped?
a) drain
b) gate
c) n-region
d) p-region
Answer: a
Explanation: In GaAs FET, a narrow metal Schottky barrier gate separates the more heavily doped drain and source.
5. Which MOSFET contains Schottky diode?
a) GaAs
b) Ga
c) Si
d) SiO2
Answer: a
Explanation: GaAs MOSFET differs from silicon MOSFET due to the presence of Schottky diode to separate two thin n-type regions.
6. D type and E type MESFETs operates by ________ of existing doped channel.
a) depletion
b) enhancement
c) e type MESFET
d) d type MESFET
Answer: a
Explanation: D type and E type MESFETs, that is ON and OFF devices operates by the depletion of an existing doped channel.
7. Which is ON device?
a) e type MESFET
b) d type MESFET
c) depletion
d) enhancement
Answer: b
Explanation: D-MESFET is normally ‘ON’ and its threshold voltage is negative and E-MESFET is ‘OFF’ and its threshold voltage is positive.
8. The threshold voltage cannot be determined using
a) concentration density
b) channel thickness
c) implanted impurity
d) channel depth
Answer: d
Explanation: The threshold voltage can be determined using concentration density, channel thickness and implanted impurity but cannot be determined using channel depth.
9. A highly doped thick channel exhibits _______ threshold voltage.
a) smaller negative
b) smaller positive
c) larger negative
d) larger positive
Answer: c
Explanation: A highly doped thick channel exhibits a large negative threshold voltage. By reducing channel thickness and concentration density, positive threshold in E-MESFET can be fabricated.
10. The MESFET has maximum
a) gate to drain voltage
b) gate to source voltage
c) source voltage
d) drain voltage
Answer: b
Explanation: The MESFET has a maximum gate to source voltage Vgs of about 0.7-0.8 volt owing to the diode action of schottky diode gate.
11. Schottky barrier is created due to the difference in
a) voltages
b) thickness
c) work function
d) density
Answer: c
Explanation: Schottky barrier is an electrostatic potential barrier created at the interface as a result of the difference in work function of the two materials.
12. As the separation between metal-semiconductor surface is reduced, induction charge
a) increases
b) decreases
c) remains constant
d) is not affected
Answer: a
Explanation: As the separation between metal-semiconductor surface is reduced, induction charge in the semiconductor increases and also the space charge layer widens.
13. In MESFET for gate _____ junction is used.
a) pnp junction
b) npn junction
c) schottky junction
d) n junction
Answer: c
Explanation: Metal semiconductor field effect transistor is similar to JFET. In this instead of using pn junction for gate, Schottky gate is used.
14. MESFET is constructed in
a) SiC
b) InP
c) GaAs
d) All of the mentioned
Answer: d
Explanation: MESFET is constructed in compound semiconductor technologies lacking high quality surface such as GaAs, InP and SiC.
This set of VLSI Multiple Choice Questions & Answers focuses on “GaAs Fabrication -1”.
1. Gallium arsenide crystals are grown from
a) boron oxide
b) silicon oxide
c) silicon nitride
d) boron nitride
Answer: d
Explanation: Growth of gallium arsenide crystals from high purity boron nitride cubicles is becoming the primary growth technique.
2. Wafers in GaAs fabrication are thermally unstable.
a) true
b) false
Answer: b
Explanation: The fabrication of GaAs includes production of round wafers and they are thermally stable and have superior semi-insulating properties.
3. The sequence of the steps followed in fabrication of GaAs is
i. lapping
ii. polishing
iii. grinding
iv. wafer scrubbing
a) ii, iii, i, iv
b) i, ii, iii, iv
c) iii, i, ii, iv
d) iv, i, ii, iii
Answer: c
Explanation: The steps followed in fabrication of GaAs are grinding the As-grown boules, wafering, edge rounding, lapping, polishing and then wafer scrubbing.
4. Which devices are fabricated using planar process?
a) enhancement mode MESFET
b) depletion mode MESFET
c) enhancement mode MOSFET
d) depletion mode MOSFET
Answer: b
Explanation: The depletion mode devices are fabricated using planar process where n-type dopants are directly implanted into semi-insulating GaAs.
5. Threshold voltage can be varied by
a) varying impurity concentration
b) varying doping level
c) varying channel length
d) varying source voltage
Answer: b
Explanation: Threshold voltage in GaAs can be varied by varying the channel thickness and the doping level of the active region.
6. Stable native oxide was produced by
a) oxidation of silicon
b) oxidation of gallium
c) oxidation of boron
d) oxidation of aluminium
Answer: a
Explanation: The driving force with siicon technology were brought about as the result of presence of stable native oxide which was readily produceded through oxidation of silicon.
7. In GaAs technology, deposited dielectric films brings about
a) passivation
b) combination
c) decomposition
d) diffusion
Answer: a
Explanation: In GaAs technology, due to the absence of a stable native oxide deposited dielectric films brings about passivation or encapsulation.
8. Formation of n-active layer is achieved by
a) indirent ion implantation
b) direct ion implantation
c) liquifying
d) wafering
Answer: b
Explanation: Formation of n-active layer is achieved by direct ion implantation into the GaAs semi-insulating substrate through the insulating layer.
9. Implantation of ________ is done for the formation of source and drain.
a) n- layer
b) n+ layer
c) p- layer
d) p+ layer
Answer: b
Explanation: Implantation of a deep low resistivity n+ layer is done for the formation of source and drain and n-layer for the formation of channel layer.
10. The channel resistance is high for
a) source contact
b) drain contact
c) gate contact
d) source and drain contacts
Answer: d
Explanation: The channel resistance is in the order of 1000 to 2500 ohm/square which is too high for source and drain contacts.
11. Stress at the interface cannot arise from
a) lattice mismatch
b) intrinsic stress
c) thermal mismatch
d) pressure mismatch
Answer: d
Explanation: Mechanical stability of thin film encapsulation layer depends upon stress at the interface and this can originate from lattice mismatch, intrinsic stress and thermal mismatch.
12. Which has the greatest mismatch?
a) Si
b) Ga
c) GaAs
d) SiO 2
Answer: d
Explanation: SiO 2 has the greatest mismatch and its cofficient of thermal expansion is 0.5×10 -6 /degree celsius.
13. Which was employed as the first level capping material?
a) SiO 2
b) SiO
c) Si3N4
d) Si2N4
Answer: a
Explanation: Si3N4 has a dielectric constant of 7 compared to 3.9 for silicondioxide and silicondioxide was initially employed as the first-level capping material.
This set of VLSI Questions and Answers for Campus interviews focuses on “GaAs Fabrication -2”.
1. The ohmic contacts are deposited by
a) decomposition
b) evaporation
c) deposition
d) mixing
Answer: b
Explanation: The ohmic contacts between the metal interconnect and the source and the drain are deposited by evaporation using E-beam technology.
2. Which has high parasitic gate resistance?
a) platinum
b) gold
c) titanium
d) aluminium
Answer: c
Explanation: Titanium provides a good, high barrier, Schottky contact and has a high parasitic gate resistance.
3. Which is used as the top layer?
a) gold
b) platinum
c) titanium
d) tungsten
Answer: a
Explanation: To reduce the parasitic resistance, gold is used as the top layer with platinum or tungsten as the intermediate layer.
4. First layer metallization is accomplished by plasma etching.
a) true
b) false
Answer: a
Explanation: First layer metallization is accomplished by delineating photoresist patterns, plasma etching, deposition of metal on GaAs wafer and photoresist lift-off.
5. Deposition rate is given as
a) width per unit time
b) thickness per unit time
c) sputtering rate per unit time
d) depositing rate per unit time
Answer: b
Explanation: Deposition rate is given as thickness per unit time. It depends upon the sticking coefficient of the depositing material and the nature of sputtering equipment.
6. Passivation is used to protect against contamination.
a) true
b) false
Answer: a
Explanation: The last step for fabrication in GaAs is passivation. This process is used to protest the device against contamination and moisture.
7. Plasma-enhanced chemical vapour deposition process is used for fabrication of
a) conducting films
b) insulating films
c) conducting & insulating films
d) none of the mentioned
Answer: c
Explanation: Plasma-enhanced chemical vapour deposition process is a chemical deposition technique used for the fabrication of both insulating and conducting films.
8. Which method uses plasma excitation?
a) PECVD
b) low pressure CVD
c) high pressure CVD
d) sputtering
Answer: a
Explanation: PECVD method uses plasma excitation in addition to usual thermal energy.
9. Which causes degradation of transconductance?
a) low source resistance
b) high source resistance
c) low drain resistance
d) high drain resistance
Answer: b
Explanation: The very thin undepleted n- layer causes high source resistance and this causes the degradation of the transconductance gm.
10. Cuts are not needed for
a) ohmic contacts
b) schottky barriers
c) interconnect metallizations
d) joining two layers
Answer: d
Explanation: Cuts are made in dielectric only where ohmic contacts, schottky barriers and interconnect metallizations are required and not for joining any two layers.
11. Which is the less costly material that can be used for first-level metal?
a) gold
b) platinum
c) aluminium
d) titanium
Answer: c
Explanation: Gold is the more costly material used for first-level and second-level metal layer whereas aluminium is the less costly material that can be used.
12. ________ is controlled by varying ion flux and velocity.
a) doping density
b) doping thickness
c) doping rate
d) doping material
Answer: a
Explanation: Doping density and dopants distribution in the semi-insulating material are controlled by varying the ion flux and velocity.
13. The extent of damage to crystal depends on
a) target mass
b) mass of the implanted ion
c) dose
d) all of the mentioned
Answer: d
Explanation: The extent of damage to the crystal depends on several factors such as mass of the implanted ion, target mass, energy associated with the ion, dose, temperature and displacement energies.
This set of VLSI Questions and Answers for Aptitude test focuses on “GaAs Fabrication -3”.
1. Which has a lightly doped channel?
a) E-MOSFET
b) D-MOSFET
c) E-JFET
d) CE-JFET
Answer: a
Explanation: The E-MOSFET structure is similar to that of D-MOSFET except for a shallower and more lightly doped channel.
2. To begin conduction, E-MOSFET requires
a) negative gate voltage
b) positive gate voltage
c) negative drain voltage
d) positive drain voltage
Answer: b
Explanation: In E-MOSFET channel is in pinch-off at zero gate voltage. A positive gate voltage is required for the channel to begin conduction.
3. Wafer preparation takes place in
a) first-level metal phase
b) second-level metal phase
c) encapsulation phase
d) ion implantation phase
Answer: c
Explanation: Encapsulation phase is the first phase and it includes wafer preparation. Encapsulation is a process of deposition of first-level insulator Si 3 N 4 .
4. Steps involved in ion implantation phase is
a) metallization
b) anneal
c) alignment mark mask
d) lift-off
Answer: b
Explanation: Anneal is a process involved in ion implantation phase along with other processes like si+ implant mask, channel implant, source drain mask, etc.
5. For the formation of E-MESFET _______ is used.
a) n- implantation
b) n+ implantation
c) p- implantation
d) p+ implantation
Answer: a
Explanation: A n- implantation is used for formation of E-MESFET and n+ implantation for the formation of D-MESFET.
6. To activate a dopant, _______ is necessary.
a) low temperature stable gate
b) low temperature stable drain
c) high temperature stable gate
d) high temperature stable drain
Answer: c
Explanation: The anneal cycle requires a stable temperature of 850 degree celcius to activate the dopants it is necessary to choose high temperature stable gate.
7. The voltage swing for schottky barrier gate should be
a) low
b) high
c) very high
d) very low
Answer: a
Explanation: Schottky barrier gates on GaAs cannot be forward biased above 0.7 to 0.8 volt, the permissible voltage swing should be relatively low.
8. The E-MESFET is defined by intersection of
a) red and yellow masks
b) green and red masks
c) brown and red masks
d) green and yellow masks
Answer: b
Explanation: E-MESFET is defined by intersection of green and red masks and D-MESFET is defined by intersection of green, red and yellow masks.
9. E-JFET technology has
a) low voltage swing
b) high current swing
c) high power requirements
d) high voltage swing
Answer: d
Explanation: E-JFET technology for ultra high speed VLSI has reduced power requirements with larger logic voltage swings.
10. In a CE-JFET, the ratio of electron mobility to hole mobility is equal to
a) 4
b) 10
c) 5
d) 20
Answer: b
Explanation: In a CE-JFET, the ratio of effective channel electron mobility of the n-channel device to hole mobility of the p-channel device is equal to 10.
11. Equal number of p and n devices in a device will consume
a) small area
b) large area
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: The circuits requiring equal numbers of p and n devices will consume large areas. Thus one must use other design methods such as precharge techniques.
12. In high electron mobility transistor, the electrons are
a) far apart
b) high mobility
c) near by and low mobility
d) far apart and high mobility
Answer: b
Explanation: The electrons in high electron mobility transistor are spacially separated from ionized donors and they exhibit high mobility.
This set of VLSI Multiple Choice Questions & Answers focuses on “Device Modelling and Performance Estimation -1”.
1. MESFETs are _______ modulation devices.
a) channel area
b) channel voltage
c) channel current
d) channel variation
Answer: a
Explanation: MESFETs are channel area modulation devices and they depend upon the capacitance of the schottky barrier.
2. Gallium arsenide have _____ regions of operation.
a) two
b) three
c) four
d) five
Answer: b
Explanation: Gallium arsenide devices have three regions of operation – cutoff, linear and saturation.
3. Drain to source current is due to
a) flow of majority carriers from drain to source
b) flow of minority carriers from drain to source
c) flow of majority carriers from source to drain
d) flow of majority carriers from drain to source
Answer: d
Explanation: The current Ids results due to the flow of electrons, the majority carrier from source to drain. Ids can be given as ratio of charge induced in channel to electron transit time.
4. Transit time can be given as the ratio of
a) channel length to velocity
b) electron distance to velocity
c) source length to velocity
d) drain length to velocity
Answer: a
Explanation: The transit time is given as the ratio of channel length to velocity and the carrier velocity can be further given as the product of electric field and electron mobility.
5. The average potential is given as
a) Vgs – Vt
b) 0.5
c) 0.25
d) 2
Answer: b
Explanation: The average potential difference between the gate and the channel owing to the shape of the depletion layer can be given as 0.5.
6. Average electric field is _______ to implant depth.
a) directly proportional
b) indirectly proportional
c) does not depend
d) exponentially dependent
Answer: b
Explanation: The average electric field is indirectly proportional to implant depth and this electric field can be given as /a.
7. The range of kp in MESFET is
a) 0.1 to 1 mA/V 2
b) 1 to 5 mA/V 2
c) 0.1 to 0.5 mA/V 2
d) 0 to 1 mA/V 2
Answer: c
Explanation: β is a common parameter used in MESFET and it is denoted by kp. Kp is in the order of 0.1 to 0.5 mA/V 2 .
8. The hyperbolic tangent function is used to describe the
a) channel conductance
b) channel length
c) channel strength
d) channel depth
Answer: a
Explanation: The hyperbolic tangent function tanh is used to describe the channel conductance at low drain to source voltage Vds.
9. The magnitude of the depletion region decreases when
a) Vgs decreases
b) Vgs increases
c) Vds increases
d) Vds decreases
Answer: b
Explanation: When the gate to source voltage Vgs increases, the magnitude of the depletion region beneath the gate decreases.
10. Current saturation occurs when
a) Vgs < Vt
b) Vgs > Vt
c) Vgs > Vds
d) Vgs = Vt
Answer: a
Explanation: When Vgs < Vt the increase in drain to source voltage above the saturation voltage leads to current saturation.
11. Velocity saturation occurs in
a) low electric field
b) high electric field
c) low magnetic field
d) high magnetic field
Answer: b
Explanation: The saturation of drain current with an increasing drain to source voltage is caused by velocity saturation which occurs in high electric field in the channel.
12. Knee voltage is the boundary between
a) active region and saturation region
b) linear and non linear region
c) linear and saturation region
d) linear and cutoff region
Answer: c
Explanation: The boundary between the linear and saturation regions defined by Vds=Vgs-Vt is referred to as the ‘knee voltage’.
This set of VLSI Assessment Questions and Answers focuses on “Device Modelling and Performance Estimation – 2”.
1. Depletion mode MESFET operates as
a) reverse biased
b) forward biased
c) both reverse and forward biased
d) none of the mentioned
Answer: a
Explanation: Depletion mode MESFET operates as reverse biased and enhancement mode MESFET operates as forward biased.
2. Pinch-off voltage is equal to
a) built-in potential
b) applied voltage
c) sum of built-in potential and applied voltage
d) difference of built-in potential and applied voltage
Answer: c
Explanation: Pinch-off voltage is the total voltage, both built-in potential and applied voltage necessary to completely deplete the channel of mobile charge carriers.
3. Pinch-off voltage is a function of
a) channel depth
b) channel thickness
c) channel length
d) channel density
Answer: b
Explanation: Pinch-off voltage is a function of both channel thickness ‘a’ and concentration density Nd and it is always positive.
4. The threshold voltage is sensitive to
a) channel length
b) channel depth
c) doping density
d) doping of the channel layer
Answer: d
Explanation: The threshold voltage Vt is very sensitive to both the channel thickness ‘a’ and the doping of the channel layer.
5. The dynamic switching energy must exceed the capacitive load.
a) true
b) false
Answer: a
Explanation: In logic structure, the dynamic switching energy must exceed the energy stored in the capacitive load.
6. To keep dynamic switching energy small
a) logic voltage swing must be large
b) logic current swing must be large
c) logic voltage swing must be small
d) logic current swing must be small
Answer: c
Explanation: To keep dynamic switching energy small, the logic voltage swing must be kept small. This requires proper control over threshold voltages.
7. Standard deviation of threshold voltage should be ______ of logic voltage swing.
a) less than 5%
b) more than 5%
c) less than 10%
d) more than 10%
Answer: a
Explanation: To achieve proper control over the threshold voltage, the standard deviation of threshold voltage should be maintained less than 5% of the logic voltage swing.
8. In D-MESFET, voltage swing is less than 1V.
a) true
b) false
Answer: b
Explanation: In D-MESFET, the logic voltage swing can be larger than 1V which means tolerance to higher threshold voltage variation can be accommodated.
9. Threshold voltage is ________ on implant depth.
a) proportionally dependent
b) inversely proportionally dependent
c) exponentially dependent
d) logarithmically dependent
Answer: c
Explanation: Threshold voltage is exponentially dependent on implant depth and there is the need for proper control of channel thickness.
10. The drain current is independent of
a) Vgs
b) Vds
c) Vt
d) Vs
Answer: a
Explanation: The drain current saturates at the same drain to source voltage Vds and is independent of gate to source voltage Vgs.
11. Impurity concentration should be
a) greater than 20%
b) lesser than 20%
c) greater than 10%
d) lesser than 10%
Answer: b
Explanation: The channel thickness should be controlled withint 20 armstrong and change is impurity concentration should be less than 20%.
12. Threshold voltage is independent of pinch-off voltage.
a) true
b) false
Answer: b
Explanation: Threshold voltage is dependent upon pinch-off voltage Vpo and barrier potential and this is given as the difference between the two.
13. Pinch-off voltage is ______ to channel concentration density.
a) directly related
b) inversely related
c) exponentially related
d) is not related
Answer: a
Explanation: Pinch-off voltage is directly related to the effective channel concentration density Nd.
This set of Basic VLSI Questions and Answers focuses on “Transconductance and Voltage Swing”.
1. Gain of MESFET is _______ to transconductance.
a) directly proportional
b) indirectly proportional
c) exponentially dependent
d) does not depend on
Answer: a
Explanation: The gain of the MESFET is directly dependent on the transconductance and output conductance of the device.
2. Transconductance gives the relationship of
a) Ids and Vds
b) Vds and Vgs
c) Ids and Vgs
d) Ids and d
Answer: c
Explanation: Transconductance describes the relationship between the output current Ids and the input control voltage Vgs.
3. Output conductance gives the slope of linear characteristics.
a) true
b) false
Answer: b
Explanation: Output conductance is also used to measure the gain of MESFET and it gives the slope of output characteristics.
4. The transconductance value in cut off region is
a) Vds
b) 1
c) cannot be determined
d) 0
Answer: d
Explanation: The transconductance value for cut off region is 0 and it is the relationship between Ids and Vgs.
5. GaAs device has
a) high bandwidth
b) high transconductance
c) low gate capacitance
d) all of the mentioned
Answer: d
Explanation: GaAs devices have high transconductance, very low gate capacitance, high gain and high bandwidth.
6. Transconductance is not influenced by transistor size.
a) true
b) false
Answer: b
Explanation: Transconductance is independent of process and slightly influenced by the transistor size. In GaAs transconductance is both process and size dependent.
7. Switching speed does not depend on
a) gate length
b) gate voltage
c) carrier mobility
d) doping level
Answer: d
Explanation: The switching speed of the device depends on gate length, gate voltage and carrier mobility in the channel but does not depend on the doping level.
8. The output conductance value in cut off region is
a) Vds
b) 1
c) cannot be determined
d) 0
Answer: d
Explanation: The output conductance value for cut off region is 0. This gives the slope of output characteristics.
9. To improve the switching speed
a) voltage swing should be increased
b) voltage swing should be decreased
c) gate length should be increased
d) gate thickness should be increased
Answer: a
Explanation: To improve the switching speed, the logic voltage swing should be increased and the gate length should be reduced. The increase in switching speed results in an increase in dissipation.
10. The device turns off when
a) Vlow > Vt
b) Vlow < Vt
c) Vhigh < Vt
d) Vhigh > Vt
Answer: b
Explanation: To establish the logic voltage swing and to turn off the device, Vlow the low logic voltage level must be less than the threshold voltage Vt.
11. For finding transconductance which is kept as constant?
a) Vss
b) Vdd
c) Vds
d) Vgs
Answer: c
Explanation: For finding transconductance, Vds is kept as constant and the ratio of the variation or change in Ids and Vgs is obtained.
12. Transconductance value is same in linear and saturation region.
a) true
b) false
Answer: a
Explanation: Transconductance value is same in case of linear and saturation region whereas it is 0 in cut-off region.
13. In bipolar transistor, transconductance is _______ to collector current.
a) directly related
b) inversely related
c) exponentially related
d) not related
Answer: a
Explanation: In bipolar transistor, transconductance is directly proportional to the collector current. It is given as gm = Ic.
14. Figure of merit does not depend on saturation velocity.
a) true
b) false
Answer: b
Explanation: Figure of merit is directly related to saturation velocity Vsat. It can be given as ft = Vsat/2.
This set of VLSI Multiple Choice Questions & Answers focuses on “FET Logic Inverter”.
1. Inverter uses D-MESFET as
a) load
b) switching device
c) controller
d) amplifier
Answer: a
Explanation: Direct-coupled FET logic inverter uses both depletion and enhancement type devices. E-MESFET is used as switching device and D-MESFET is used as load.
2. The allowable output voltage is limited by
a) load resistance
b) load capacitance
c) barrier height
d) material used for barrier
Answer: c
Explanation: The design of the inverter is similar to silicon nMOS circuitry and the allowable output voltage is limited by the barrier height of the Schottky gate diode.
3. For depletion mode transistor, gate is connected to
a) Vdd
b) source
c) ground
d) drain
Answer: b
Explanation: For the depletion mode transistor, the gate is connected to the source and it is always on and only the characteristic curve Vgs=0 is suitable.
4. In DCFL inverter, enhancement mode device is called as
a) pull down transistor
b) pull up transistor
c) buffer
d) combiner
Answer: a
Explanation: In direct-coupled FET logic inverter, depletion mode device is called the pull-up and enhancement mode device is called as pull-down transistor.
5. Maximum voltage across enhancement mode device corresponds to minimum voltage across depletion mode device.
a) true
b) false
Answer: a
Explanation: In direct-coupled FET logic inverter, maximum voltage across enhancement mode device corresponds to minimum voltage across the depletion mode transistor.
6. When current begins to flow, output voltage
a) increases
b) decreases
c) remains constant
d) does not get affected
Answer: b
Explanation: When Vin exceeds threshold voltage, current begins to flow. Then the output voltage Vout decreases and the transistor becomes resistive.
7. Inverter threshold voltage is the point where
a) Vin = Vt
b) Vout = Vt
c) Vin = Vout
d) Vout lesser than Vin
Answer: c
Explanation: The point at which Vout = Vin, is denoted as Vinv. The transfer characteristic and Vinv can be shifted by variation of the ratio of pull-up to pull-down resistances.
8. For equal margin, Vinv is set as ______ of logic voltage swing.
a) equal
b) half of
c) one third
d) twice
Answer: b
Explanation: Since the logic high level is limited by barrier potential then for equal margins Vinv is set to half of the logic voltage swing.
9. For E-MESFET, Vinv is set in midway between
a) Vdd and Vss
b) Vt and Vin
c) Vt and Vout
d) barrier potential and ground
Answer: d
Explanation: In pull-down device that is E-MESFET, the inverter threshold voltage Vinv is set midway between barrier potential and ground.
10. To improve packing density, gate length should be smaller.
a) true
b) false
Answer: b
Explanation: To improve packing density, gate length should be larger for the pull-up device. This will reduce drain to source saturation current.
11. The ratio of Zp.u./Zp.d. for E-MESFET is
a) 1/10
b) 10/1
c) 4/1
d) 1/4
Answer: b
Explanation: For E-MESFET, the Zp.u./Zp.d. ratio is 10/1. For MESFET with Lp.u.=Lp.d., Wp.u./Wp.d. is equal to 1/10.
12. In direct coupled logic, the input transistor base is connected to
a) base output
b) emitter output
c) collector output
d) ground
Answer: c
Explanation: In direct coupled logic, the input transistor base is directly connected to the collector output without any base resistors.
13. Direct-coupled logic is easy to design.
a) true
b) false
Answer: a
Explanation: Direct-coupled logic devices have fewer components, are economical and simpler to design and fabricate.
14. For cascade inverters, the relation suitable is
a) Vin = Vout > Vinv
b) Vin = Vout = Vinv
c) Vin < Vout > Vinv
d) Vin > Vout = Vinv
Answer: b
Explanation: For cascade inverters without degradation of levels, the relatio suitable and required is Vin = Vout = Vinv.
This set of VLSI Multiple Choice Questions & Answers focuses on “MESFET Design-1”.
1. MESFET circuits are formed on _____ layers.
a) two
b) three
c) four
d) five
Answer: a
Explanation: MESFET circuits are formed effectively on two layers – green implant layer and red gate-metal layer.
2. If gate-metal layer is in contact with the implant layer _____ is formed.
a) diode
b) transistor
c) switch
d) buffer
Answer: b
Explanation: If the gate-metal layer is in contact with the implant layer a transistor is formed. The implant layer and the gate-metal layer interact to form the Schottky gate where they cross one another.
3. When insulating layer is used in between the implant and gate-metal, it is used as
a) amplifier
b) transistor
c) switch
d) interconnect
Answer: d
Explanation: If an insulating layer is introduced in between the implant and gate-metal, there is no interaction between these layers and it can be used as interconnect.
4. The MESFET properties can be varied by varying the
a) implant
b) implant concentration
c) structure
d) length
Answer: b
Explanation: The basic properties of MESFET can be modified by varying the implant concentration density.
5. Complexity in MESFET design can be reduced by using
a) layout design
b) stick diagram
c) symbolic representation
d) transistor diagram
Answer: c
Explanation: Through color encoding and symbolic representation of layers, it is possible to remove much of the complexity associated with the design of MESFET.
6. _______ color is used to represent interconnections.
a) red
b) green
c) yellow
d) brown
Answer: a
Explanation: Red is used to represent Schottky gate and short interconnections.
7. Which color is used to represent first level metal?
a) brown
b) blue
c) dark blue
d) green
Answer: b
Explanation: Blue is used to represent first level metal and dark blue is used for second level metal.
8. The _______ mask identifies all active region.
a) blue layer
b) red layer
c) yellow layer
d) green layer
Answer: d
Explanation: The green layer mask identifies all active regions such as areas that eventually form E and D type devices, active loads and implant resistors.
9. ______ forms the more heavily doped channel of D-MESFET.
a) red inside yellow layer
b) green inside yellow layer
c) yellow inside green layer
d) green outside yellow layer
Answer: b
Explanation: The green region inside yellow layer mask form the more heavily doped channel of the D-MESFET.
10. _______ is used to represent the lightly doped channel of E-MESFET.
a) red inside yellow layer
b) green inside yellow layer
c) yellow inside green layer
d) green outside yellow layer
Answer: d
Explanation: Green regions outside the yellow layer form the lightly doped channel of the E type MESFET.
11. ______ is used to represent implant.
a) yellow
b) red
c) green
d) brown
Answer: c
Explanation: Green color is used to represent implant layer. Symbolically it is represented as E-MESFET and it is formed when crossed by gate-metal.
12. _____ is used to represent ohmic contact.
a) yellow
b) red
c) green
d) brown
Answer: d
Explanation: Brown is used to represent ohmic contact and it is used with source/drain contacts.
This set of VLSI Problems focuses on ” MESFET Design-2″.
1. In the ring diagram, green line is used to represent
a) E-MESFET
b) D-MESFET
c) Interconnection
d) Transistor
Answer: a
Explanation: In the ring diagram, green or dotted line represents E-MESFET while yellow or solid line represents D-MESFET.
2. E-type and D-type is joined together using
a) metal 1
b) metal 2
c) vias
d) interconnectors
Answer: a
Explanation: E-type and D-type features are joined together using blue color which represents metal 1 layer.
3. What is the intermediate stage in converting ring diagram to mask layout?
a) switch logic
b) transistor level diagram
c) symbolic diagram
d) stick diagram
Answer: c
Explanation: The ring diagrams can be turned into mask layout directly or through an intermediate symbolic representation stage.
4. In symbolic representation, rings are converted into
a) color codes
b) switches
c) sticks
d) circuit elements
Answer: d
Explanation: Symbolic representation is the intermediate stage when turning ring diagram to mask layout and here rings are represented as circuit elements.
5. For inverters color code used is
a) red followed by green paths
b) green followed by red paths
c) green followed by yellow paths
d) red followed by yellow paths
Answer: c
Explanation: The green followed by yellow paths are drawn for inverters and inverter based logic such as NOR gates.
6. In symbolic representation _________ is used to represent E-MESFET.
a) red transistor
b) green transistor
c) yellow transistor
d) blue transistor
Answer: b
Explanation: In symbolic representation, green transistor is used to represent E-MESFET and yellow transistor is used to represent D-MESFET.
7. Global control paths are run in
a) metal 2
b) metal 1
c) transistor
d) interconnects
Answer: a
Explanation: Long signal and global control paths are run in metal 2 parallel with the power rails.
8. _______ gives the instruction for the preparation of photomasks.
a) design layout
b) design rules
c) color codes
d) layout map
Answer: b
Explanation: Design rules are the prescription for the preparation of photomasks that are to be used in the fabrication of integrated circuits.
9. Design rule is not influenced by maturity of property line.
a) true
b) false
Answer: a
Explanation: Design rules can also be influenced by maturity of the process line. If the process is mature, then one can be assured of the process line capability allowing tighter design with fewer constraints.
10. The separation between implant is determined from
a) width of transistor
b) width of E-MESFET
c) width of D-MESFET
d) width of photoresist
Answer: d
Explanation: The separation between implant is determined from width of depletion region and width of photoresist.
11. MESFETs should be positioned
a) horizontally
b) vertically
c) diagonally
d) randomly
Answer: a
Explanation: All MESFETs should be positioned horizontally owing to its anisotropic nature of GaAs which influences the threshold voltage of the device.
12. Saturated resistor is a
a) FET with schottky gate
b) FET without schottky gate
c) MESFET with schottky gate
d) MESFET without schottky gate
Answer: d
Explanation: The saturated resistor is a MESFET with the schottky gate removed. The preferred direction for layout is vertical.
13. MIM capacitor uses
a) metal 1
b) metal 2
c) metal 1 and metal 2
d) schottky gate
Answer: c
Explanation: The metal-insulator-metal capacitor structure is simple using metal 1 and metal 2 as the plates of a parallel plate capacitor.
14. The mask is derived from the structural operation of masks.
a) true
b) false
Answer: b
Explanation: The mask is derived from the logical operation of the active layer masks. Some processes require isolation between devices to reduce their interaction.
This set of VLSI Multiple Choice Questions & Answers focuses on “GaAs MESFET Logics”.
1. Normally-on logic uses
a) depletion mode MESFET
b) enhancement mode MESFET
c) depletion mode FET
d) enhancement mode FET
Answer: b
Explanation: Normally-on logic uses depletion mode MESFETs which are ON devices and when used as switching elements are required to be turned OFF.
2. Which is the approach used for normally-off logic?
a) capacitor diode FET logic
b) buffered FET logic
c) direct-coupled FET logic
d) capacitor coupled FET logic
Answer: c
Explanation: The approaches used for normally-off logic are direct-coupled FET logic, buffered DCFL and source-follower DCFL.
3. __________ is needed to facilitate turn-off.
a) positive voltage
b) power supply rail
c) ground connection
d) negative voltage
Answer: d
Explanation: Since D-MESFETs are ON devices, negative voltage is needed at the gate to facilitate turn-off.
4. __________ supply rails are required for proper operation of normally-on logic devices.
a) one
b) two
c) three
d) four
Answer: b
Explanation: Two supply rails together with level shifting networks are necessary for proper circuit operation of normally-on logic gates.
5. In direct coupled FET logic, both depletion and enhancement mode devices are used.
a) true
b) false
Answer: a
Explanation: In direct-coupled FET logic both the depletion mode and enhancement mode transistors are used. Enhancement mode FET is used as switching element and depletion mode FET is used as load.
6. DCFL circuits have
a) large voltage swing
b) small voltage swing
c) large noise margins
d) more complexity
Answer: b
Explanation: In direct-coupled FET logic, only small voltage swings are possible and also relatively small noise margins.
7. Which circuits have weak load drive capability?
a) DCFL
b) DCFL with super buffers
c) FET logic
d) SDCFL
Answer: a
Explanation: DCFL circuits have weak load drive capability. This can be improved by the introduction of super buffers with expense of extra area.
8. Which logic is suitable for large loads?
a) DCFL
b) DCFL with super buffers
c) FET logic
d) SDCFL
Answer: b
Explanation: DCFL with super buffers are used for larger loads to be driven whereas DCFL circuits are used for light load conditions.
9. Which circuit has large noise margin?
a) DCFL
b) DCFL with super buffers
c) FET logic
d) SDCFL
Answer: d
Explanation: Source follower DCFL FET logic has power dissipation and also switching delay. This has a larger noise margin which is due to pull-up transistor being able to be turned off.
10. Which logic is suitable for And-OR-Invert function?
a) DCFL
b) DCFL with super buffers
c) FET logic
d) SDCFL
Answer: d
Explanation: The source-follower DCFL FET logic is most suitable for realization of And-OR-Invert function which usually assists in the optimization of logical functions.
This set of VLSI Multiple Choice Questions & Answers focuses on “FET”.
1. Field effect transistor uses ________ to control the shape.
a) electric field
b) magnetic field
c) current distribution
d) voltage distribution
Answer: a
Explanation: Field effect transistor uses electric field to control the shape and hence the electrical conductivity of the channel.
2. Field effect transistors are known as
a) unipolar device
b) bipolar device
c) tripolar device
d) multipolar device
Answer: a
Explanation: Field effect transistors are unipolar transistors as they involve single-carrier-type operation.
3. The FET has __________ input impedance.
a) low
b) high
c) all of the mentioned
d) none of the mentioned
Answer: b
Explanation: Field effect transistors have high input impedance. The conductivity of non-FET transistors are regulated by the input current thus it has low input impedance.
4. Field effect transistor’s conductivity is regulated by
a) input current
b) output current
c) terminal voltage
d) supply voltage
Answer: c
Explanation: Field effect transistor’s conductivity is regulated by the voltage applied to a terminal which is insulated from the device.
5. In FET, the current enters the channel through
a) source
b) drain
c) gate
d) nodes
Answer: a
Explanation: In field effect transistor, the current enters the channel through source and the current leaves the junction through drain.
6. Which terminal bias the transistor to operation?
a) source
b) drain
c) gate
d) base
Answer: d
Explanation: Other than the three terminals, source drain and gate, there is a fourth terminal called as body or base. This is used to bias the transistor to operation.
7. In FET, the width is greater than the length of the gate.
a) true
b) false
Answer: a
Explanation: In FET, the width is greater than the length of the gate. Length gives the distance between source and drain. Width is the extension of the transistor, in the direction perpendicular to cross section.
8. Which terminal controls the electron flow passage?
a) source
b) drain
c) gate
d) base
Answer: c
Explanation: Gate permits the electron to flow through or block their passage by creating or eliminating the channel between source and drain.
9. The expansion of depletion region in n-channel device makes the channel
a) narrow
b) wide
c) does not affect the channel
d) cannot be determined
Answer: a
Explanation: In n-channel depletion mode device, as the depletion region width expands, it encroaches the channel from the sides and the channel becomes narrow.
10. Which voltage increases the channel size?
a) negative Vgs
b) positive Vgs
c) negative Vds
d) positive Vds
Answer: b
Explanation: A positive gate to source voltage increases the channel size and allows the electrons to flow easily.
11. Which relation is correct?
a) Vgs greater than Vds
b) Vds greater than Vgs
c) Vds equal to Vgs
d) Vgs lesser than Vds
Answer: a
Explanation: In FET, for either depletion or enhancement mode device the drain to source voltage is much less than the gate to source voltage.
12. Which mode of operation of FET is used, when amplification is needed?
a) active
b) saturation
c) non saturation
d) linear
Answer: b
Explanation: Saturation mode, which is in between the ohmic and saturation region is used when amplification is needed.
This set of VLSI Multiple Choice Questions & Answers focuses on “Metal Oxide Semiconductor Transistor – 1”.
1. The conductivity of the pure silicon is raised by:
a) Introducing Dopants
b) Increasing Pressure
c) Decreasing Temperature
d) Deformation of Lattice
Answer: a
Explanation: By introducing Dopants free charge carriers increase further increasing the conductivity of silicon.
2. The n-type semiconductor have _______ as majority carriers.
a) Holes
b) Negative ions
c) Electrons
d) Positive ions
Answer: c
Explanation: In n-type semiconductor the majority charge carriers present are electrons.
3. The majority carriers of p-type semiconductor are:
a) Holes
b) Negative ions
c) Electrons
d) Positive ions
Answer: a
Explanation: The majority charge carriers of n-type semiconductors are holes.
4. The n-MOS transistor is made up of:
a) N-type source, n-type drain and p-type bulk
b) N-type source, p-type drain and p-type bulk
c) P-type source, n-type drain and n-type bulk
d) P- type source, p-type drain and n-type bulk
Answer: a
Explanation: n-MOS Transistor consists of n-type source, n-type drain and p-type bulk.
5. The correct representation of n-MOSFET is:
a) vlsi-questions-answers-metal-oxide-semiconductor-transistor-1-q5a
b) vlsi-questions-answers-metal-oxide-semiconductor-transistor-1-q5b
c) vlsi-questions-answers-cmos-logic-gates-q5c
d) None of the mentioned
Answer: c
Explanation: This is the correct representation of n-MOSFET : vlsi-questions-answers-cmos-logic-gates-q5c
6. The correct representation of p-MOSFET is:
a) vlsi-questions-answers-metal-oxide-semiconductor-transistor-1-q6a
b) vlsi-questions-answers-metal-oxide-semiconductor-transistor-1-q6b
c) vlsi-questions-answers-metal-oxide-semiconductor-transistor-1-q6c
d) vlsi-questions-answers-metal-oxide-semiconductor-transistor-1-q6d
Answer: b
Explanation: This is the correct representation of p-MOSFET: vlsi-questions-answers-metal-oxide-semiconductor-transistor-1-q6b
7. The oxide layer formed in the MOSFET is:
a) Metal oxide
b) Silicon dioxide
c) Poly Silicon oxide
d) Oxides of Non metals
Answer: b
Explanation: Silicon Dioxide is the insulating oxide layer formed in MOSFET.
8. The drain current is varied by:
a) Gate to source voltage
b) Gate current
c) Source Voltage
d) None of the mentioned
Answer: a
Explanation: The Gate to Source voltage acts as input which varies the drain current.
9. The low voltage on the gate of p-MOSFET forms:
a) Channel of negative carriers
b) Channel is not formed
c) Channel is clipped
d) Channel of positive carriers
Answer: d
Explanation: For a p-MOS low gate voltage forms a conducting channel of positive carriers.
10. The n-MOSFET is working as accumulation mode when:
a) Gate is applied with positive voltage
b) Gate is grounded
c) Gate is applied with negative voltage
d) Gate is connected to source
Answer: c
Explanation: When the negative voltage is applied to the gate, there develops a presence of negative charge on the gate. The mobile positively charged holes are attracted to the region beneath the gate. This explains the formation of accumulation mode.
This set of VLSI Multiple Choice Questions & Answers focuses on “Metal Oxide Semiconductor Transistor – 2”.
1. The current through the n-MOS transistor will flow when:
a) Vgs > Vtreshold, Vds=0
b) Vgd < Vtreshold, Vds=0
c) Vgs > Vtreshold, Vds>0
d) Vgd > Vtreshold, Vds<0
Answer: c
Explanation: The current flows through the n-MOS transistor when Vgs > Vtreshold, Vds>0.
2. The p-MOS Transistor is said to be in Saturation mode when:
a) Vdsp > Vgsp – Vtp
b) Vgsp < Vdsp –Vtp
c) Vgsp > Vtp
d) Vdsp < Vgsp – Vtp
Answer: d
Explanation: The pMOS transistor is in Saturation mode when Vdsp < Vgsp – Vtp and Vgsp < Vtp.
3. The Fermi potential of the p-type MOSFET is:
a) φfp = ln
b) φfp = ln
c) φfp = ln
d) φfp = ln
Answer: d
Explanation: The Fermi potential of the p-type semiconductor is φfp = ln where ni denotes the intrinsic carrier concentration of silicon, NA is acceptor concentration, ND is Donor Concentration.
4. The Fermi potential for the n-type MOSFET is:
a) φfp = ln
b) φfp = ln
c) φfp = ln
d) φfp = ln
Answer: c
Explanation: The Fermi potential of the p-type semiconductor is φfp = ln where ni denotes the intrinsic carrier concentration of silicon, NA is acceptor concentration, ND is Donor Concentration.
5. The principle of the MOSFET operation is:
a) Control the conduction of current between the source and the drain, using the potential difference applied at the gate voltage as a control variable
b) Control the current conduction between the source and the gate, using the electric field applied at the drain voltage as a control variable
c) Control the current conduction between the PN junction, using the electric field generated by the bias voltage as a control variable
d) Control the current conduction between the PN junctions, using the electric potential generated by the gate voltage as a control variable
Answer:a
Explanation: By varying the gate voltage the current between the source and drain are varied.
6. The conduction of current IDS depends on:
i) Gate to source voltage
ii) Drain to source voltage
iii) Bulk to source voltage
iv) Threshold voltage
v) Dimensions of MOSFET
a) Only i
b) Only i, ii and iii
c) Only v
d) All of the mentioned
Answer: d
Explanation: The current depends on Vgs, Vds, Vbs, Vt and dimensions of MOSFET.
7. The impedance at the input of n-MOS transistor circuit is:
a) Lesser than p-MOS transistor
b) Greater than BJT transistor
c) Lesser than JFET transistor
d) Zero
Answer: b
Explanation: The impedance at the input of n-MOS transistor is more than BJT transistor.
8. The depletion mode n-MOS differs from enhancement mode n-MOS in:
a) Threshold voltage
b) Channel Length
c) Switching time
d) None of the mentioned
Answer: a
Explanation: If n-MOS operates with negative threshold voltage then it is in depletion mode. If n-MOS operates with positive threshold voltage then it is in enhancement mode.
This set of VLSI Multiple Choice Questions & Answers focuses on “nMOS and Complementary MOS ”.
1. The n-MOS invertor is better than BJT in terms of:
a) Fast switching time
b) Low power loss
c) Smaller overall layout area
d) All the mentioned
Answer: d
Explanation: The n-MOS invertor is better than BJT invertor due to fast switching time, low power loss, smaller overall layout area.
2. The n-MOS invertor consists of n-MOS transistor as driven and
a) Resistor as a load
b) Depletion mode n-MOS as a load
c) Enhancement mode n-MOS as a load
d) Any of the mentioned
Answer: d
Explanation: The n-MOS inverter consists of n-MOS and resistor or depletion mode n-MOS or enhancement mode n-MOS at the pull up load.
3. If the n-MOS and p-MOS of the CMOS inverters are interchanged the output is measured at:
a) Source of both transistor
b) Drains of both transistor
c) Drain of n-MOS and source of p-MOS
d) Source of n-MOS and drain of p-MOS
Answer: a
Explanation: When the transistors are interchanged, The drain of n-MOS is connected to supply voltage, drain of p-MOS is connected to the ground. The output is measured at source of both the transistors.
4. What will be the effect on output voltage if the positions of n-MOS and p-MOS in CMOS inverter circuit are exchanged?
a) Output is same
b) Output is reversed
c) Output is always high
d) Output is always low
Answer: b
Explanation: When the input is low, p-MOS is ON and the output is pulled down to the ground. When the input is high, n-MOS is ON and the output is pulled up to the supply voltage.
5. The average power dissipated in resistive load n-MOS inverter is:
a) 0
b) VDD /R
c) VDD /2R
d) VDD /2R
Answer: c
Explanation: When the input voltage is equal to VOH on the other hand, both the driver MOSFET and the load resistor conduct a nonzero current. Since the output voltage in this case is equal to VOL, DC power consumption of the inverter can be estimated as VDD /2R.
6. The depletion mode n-MOS as an active load is better than enhancement load n-MOS in:
a) Sharp VTC transition and better noise margins
b) Single power supply
c) Smaller overall layout area
d) All of the mentioned
Answer: d
Explanation: The depletion mode n-MOS transistor as load requires single power supply, smaller overall layout area, and sharp VTC transition.
7. The enhancement mode n-MOS load inverter requires 2 different supply voltages to:
a) Keep load transistor in cutoff region
b) Keep load transistor in linear region
c) Keep load transistor in saturation region
d) None of the mentioned
Answer: b
Explanation: The enhancement mode n-MOS load inverter requires 2 different supply voltages to keep load transistor in linear region.
8. The CMOS inverter consists of:
a) Enhancement mode n-MOS transistor and depletion mode p-MOS transistor
b) Enhancement mode p-MOS transistor and depletion mode n-MOS transistor
c) Enhancement mode p-MOS transistor and enhancement mode p-MOS transistor
d) Enhancement mode p-MOS transistor and enhancement mode n-MOS transistor
Answer: d
Explanation: The CMOS inverter consist of enhancement mode p-MOS and enhancement mode n-MOS.
9. In the CMOS inverter the output voltage is measured across:
a) Drain of n-MOS transistor and ground
b) Source of p-MOS transistor and ground
c) Source of n-MOS transistor and source of p-MOS transistor
d) Gate of p-MOS transistor and Gate of n-MOS transistor
Answer: a
Explanation: In the CMOS inverter the output voltage is measured across Drain of n-MOS transistor and ground.
10. When the input of the CMOS inverter is equal to Inverter Threshold Voltage Vth, the transistors are operating in:
a) N-MOS is cutoff, p-MOS is in Saturation
b) P-MOS is cutoff, n-MOS is in Saturation
c) Both the transistors are in linear region
d) Both the transistors are in saturation region
Answer: d
Explanation: When the input of the CMOS inverter is equal to Inverter Threshold Voltage Vth, both the transistors are operating in saturation region
11. The switching threshold voltage VTH for an ideal inverter is equal to:
a) /2
b) VDD
c) /2
d) 0
Answer: c
Explanation: The switching threshold voltage VTH for an ideal inverter is equal to /2.
12. Which of these invertors is more efficient?
vlsi-questions-answers-nmos-cmos-q12
a) Depletion mode n-MOS inverter
vlsi-questions-answers-nmos-cmos-q12a
b) pMOS inverter
vlsi-questions-answers-nmos-cmos-q12b
c) CMOS inverter
vlsi-questions-answers-nmos-cmos-q12c
d) Resistive load nMOS inverter
Answer: c
Explanation: The power loss in CMOS inverter is very small and the I-V characteristics is approximately equal to ideal inverter. Therefore the CMOS inverter is most efficient.
This set of VLSI Multiple Choice Questions & Answers focuses on “MOS Transistor Threshold Voltage”.
1. The electrical equivalent component for MOS structure is:
a) Resistor
b) Capacitor
c) Inductor
d) Switch
Answer: b
Explanation: The MOS structure acts as a capacitor with a metal gate and semiconductor acting as parallel plate conductors and oxide as dielectric between them.
2. The Fermi potential is the function of:
a) Temperature
b) Doping concentration
c) Difference between Fermi level and intrinsic Fermi level
d) All of the mentioned
Answer: d
Explanation: The Fermi potential, which is a function of temperature and doping, denotes the difference between the intrinsic Fermi level and the Fermi level.
3. The direction of electric field when the gate voltage is zero:
a) Metal to semiconductor
b) Semiconductor to metal
c) No electric field exists
d) None of the mentioned
Answer: a
Explanation: Metal being more positive compared to semiconductor. The electric field exists from metal to semiconductor.
4. Consider a MOS structure with equilibrium Fermi potential of the doped silicon substrate is given as 0.3eV. Electron affinity of Si is 4.15eV and metal is 4.1eV. Find the built in potential of the MOS system.
a) -0.8eV
b) 0.8eV
c) 0.9eV
d) -0.9eV
Answer: d
Explanation: Surface potential: qΦs = 4.15eV + 0.55eV + 0.3eV = 5.0eV
qΦm-qΦs = 4.1eV – 5.0eV = -0.9eV.
5. When gate voltage is negative for enhancement mode n-MOS, the direction of electric field will be:
a) Metal to semiconductor
b) Semiconductor to metal
c) No field exists
d) None of the mentioned
Answer: b
Explanation: When gate voltage is negative, holes in substrate are attracted towards surface creating electric field from semiconductor to metal.
6. At threshold Voltage, the surface potential is:
a) – Fermi potential
b) Fermi potential
c) 2 Fermi potential
d) -2 Fermi potential
Answer: a
Explanation: When surface potential reaches –fermi potential, the surface inversion occurs. The gate voltage which brings these changes is known as threshold voltage.
7. Surface inversion occurs when gate voltage is:
a) Less than zero
b) Less than threshold voltage
c) Equal to threshold voltage
d) Greater than threshold voltage
Answer: c
Explanation: Surface inversion occurs when gate voltage is equal to threshold voltage.
8. The energy band diagram of the MOS system when gate voltage is zero is:
a) vlsi-questions-answers-mos-threshold-voltage-q8a
b) vlsi-questions-answers-mos-threshold-voltage-q8b
c) vlsi-questions-answers-mos-threshold-voltage-q8c
d) vlsi-questions-answers-mos-threshold-voltage-q8d
Answer: a
Explanation: The energy band diagram of enhancement mode nMOSFET when gate voltage is zero is : vlsi-questions-answers-mos-threshold-voltage-q8a
9. For enhancement mode n-MOSFET, the threshold voltage is:
a) Equal to 0
b) Greater than zero or Positive quantity
c) Negative voltage or lesser than zero
d) All of the mentioned
Answer: b
Explanation: For enhancement mode n-MOSFET, the threshold voltage is positive quantity.
10. The threshold voltage depends on:
a) The workfunction difference between gate and channel
b) The gate voltage component to change surface potential
c) The gate voltage component to offset the depletion charge and fixed charges in gate oxide
d) All of the mentioned
Answer: d
Explanation: The threshold voltage depends on: The workfunction difference between gate and channel, The gate voltage component to change surface potential, The gate voltage component to offset the depletion charge and fixed charges in gate oxide
11. The Energy band diagram of MOS system when gate voltage is equal to threshold voltage is:
a) vlsi-questions-answers-mos-threshold-voltage-q11a
b) vlsi-questions-answers-mos-threshold-voltage-q11b
c) vlsi-questions-answers-mos-threshold-voltage-q11c
d) vlsi-questions-answers-mos-threshold-voltage-q11d
Answer: c
Explanation: The Energy band diagram of MOS system when gate voltage is equal to threshold voltage is vlsi-questions-answers-mos-threshold-voltage-q11c
12. The expression for threshold voltage for the enhancement mode nMOSFET is:
a) Φgc-2ϕf-Qbo/Cox-Qox/Cox
b) Φgc+ϕf-Qbo/Cox
c) Φgc-ϕf-Qbo/Cox+Qox/Cox
d) Φgc+2ϕf-Qbo/Cox-Qox/Cox
Answer: a
Explanation: The expression for threshold voltage for the enhancement mode nMOSFET is Φgc-2ϕf-Qbo/Cox-Qox/Cox.
This set of VLSI Multiple Choice Questions & Answers focuses on “Noise Margin”.
1. Noise Margin is:
a) Amount of noise the logic circuit can withstand
b) Difference between VOH and VIH
c) Difference between VIL and VOL
d) All of the Mentioned
Answer: d
Explanation: Noise Margin is defined as the amount of noise the logic circuit can withstand, it is given by the difference between VOH and VIH or VIL and VOL.
2. The VIL is found from transfer characteristic of inverter by:
a) The point where the straight line at VOH ends
b) The slope of the transition at a point at which the slope is equal to -1
c) The midpoint of the transition line
d) All of the mentioned
Answer: b
Explanation: The VIL is the input voltage at which the slope of the transition will be equal to -1.
3. The VIH is found from transfer characteristic of inverter by:
a) The point where straight line at VOH ends
b) The slope of the transition at a point at which the slope is equal to -1
c) The midpoint of the transition line
d) All of the mentioned
Answer: b
Explanation: The VIH is the input voltage at which the slope of the transition will be equal to -1. In Transfer characteristics at 2 points we will find the slope to be -1.
4. The relation between threshold voltage and Noise Margin is:
a) Vth = sqrt
b) Vth = NMH – NML
c) Vth = /2
d) None of the metioned
Answer: d
Explanation: None.
5. The Lower Noise Margin is given by:
a) VOL – VIL
b) VIL – VOL
c) VIL ~ VOL
d) All of the Mentioned
Answer: b
Explanation: Noise margin = VIL-VOL.
6. The Higher Noise Margin is given by:
a) VOH – VIH
b) VIH – VOH
c) VIH ~ VOH
d) All of the mentioned
Answer: a
Explanation: Noise margin = VOH – VIH.
7. The Uncertain or transition region is between:
a) VIH and VOH
b) VIL and VOL
c) VIH and VIL
d) VOH and VOL
Answer: c
Explanation: In Input the uncertain region is VIH and VIL.
8. The noise immunity ____________ with noise margin.
a) Decreases
b) Increases
c) Constant
d) None of the Mentioned
Answer: b
Explanation: The noise immunity is directly proportional to noise margin.
9. If VIL of the 2nd gate is higher than VOL of the 1st gate, then logic output 0 from the 1st gate is considered as:
a) Logic input 1
b) Uncertain
c) Logic input 0
d) None of the mentioned
Answer: c
Explanation: Logic output 0 from first gate is considered as logic input 0 at second gate as it lies within the range.
10. If VIL of the 2nd gate is lower than VOL of the 1st gate, then logic output 0 from the 1st gate is considered as:
a) Logic input 1
b) Uncertain
c) Logic input 0
d) None of the mentioned
Answer: b
Explanation: The level of output signal from 1st gate is higher than the range for low input at 2nd gate. So it is uncertain.
11. Input Voltage between VIL and VOL is considered as:
a) Logic Input 1
b) Logic Input 0
c) Uncertain
d) None of the mentioned
Answer: b
Explanation: None.
12. If VIH of the 2nd gate is higher than VOH of the 1st gate, then logic output 0 from the 1st gate is considered as:
a) Logic input 1
b) Uncertain
c) Logic input 0
d) None of the mentioned
Answer: b
Explanation: The level of output signal from 1st gate is higher than the range for low input at 2nd gate. So it is uncertain.
13. Determine the Noise Margin for 5V TTL inverter gate:
vlsi-questions-answers-noise-margin-q13
a) NMH = 0.4V and NML =0.4V
b) NMH = 2.4V and NML = 0.4V
c) NMH = 2V and NML = 0.8V
d) NMH = 1.5V and NML = 0.4V
Answer: a
Explanation: None.
14. Determine the Noise Margin for 5V CMOS inverter gate:
vlsi-questions-answers-noise-margin-q14
a) NMH = 1V and NML = 1V
b) NMH = 3.7V and NML = 0.2V
c) NMH = 0.9V and NML = 1V
d) NMH = 0.2V and NML = 0.5V
Answer: c
Explanation: None.
15. Noise margin of CMOS is:
a) Better than TTL and ECL
b) Less than TTL and ECL
c) Equal to TTL and ECL
d) None of the Mentioned
Answer: a
Explanation: None.
This set of VLSI Multiple Choice Questions & Answers focuses on “Noise in MOS Devices”.
1. Noise in VLSI circuits mean:
a) Unwanted signals that arise due to vibration in the passive circuits
b) Unknown signal that limits the minimum signal level that a circuit can process with acceptable quality
c) Signal which undergoes distortion
d) All of the mentioned
Answer: b
Explanation: In VLSI circuits noise limits the minimum signal level that a circuit process with acceptable quality.
2. In probability Noise is described as:
a) Random function
b) Random process
c) Deterministic function
d) Deterministic process
Answer: b
Explanation: Noise is a Random Process.
3. Noise generated by independent devices are:
a) Correlated
b) Uncorrelated
c) Equal
d) None of the mentioned
Answer: b
Explanation: Noise generated by independent devices are uncorrelated, eg: noise generated from resistor is not similar to noise generated from transistor.
4. The 2 types of noise that the analog systems face during signal processing are:
a) Device electronic noise and environmental noise
b) Noise due to Vibration and electronic noise
c) Passive and active noise
d) None of the mentioned
Answer: a
Explanation: Device electronic noise and environmental noise affects signal processing of analog signals.
5. Thermal noise is generated from:
a) Resistor
b) Capacitor
c) Inductor
d) All of the mentioned
Answer: a
Explanation: Thermal noise is due to random motion of electrons in a conductor.
6. Thermal noise is generated from MOSFET by:
a) Conduction of charge carriers in the channel
b) Electric field across the gate and channel
c) Capacitance of the gate oxide
d) Substrate bias effect
Answer: a
Explanation: Thermal noise is generated due to conduction of charge carriers in the channel.
7. Thermal noise current in the MOSFET is proportional to:
a) Transconductance
b) Resistance
c) Gate voltage
d) None of the mentioned
Answer: a
Explanation: Noise current I^2 = 4kTygm.
8. Flicker noise is found in MOSFET at:
a) Gate and oxide interface
b) Gate oxide and silicon interface
c) Source and substrate interface
d) Drain and substrate interface
Answer: b
Explanation: The interface between Gate oxide and silicon substrate generates flicker noise.
9. Flicker noise originates due to:
a) Conduction in channel
b) Drain to Source voltage
c) Reduction in channel length
d) Dangling bonds
Answer: d
Explanation: Dangling bonds generate flicker noise.
10. The average power of flicker noise depends on:
a) Thickness of oxide
b) Cleanness of the oxide silicon interface
c) Voltage on oxide
d) Length of channel
Answer: b
Explanation: Depending on the Cleanness of oxide silicon interface flicker noise varies.
11. In the following graph the fc is called as:
vlsi-questions-answers-mos-noise-concept-q11
a) Cutoff frequency
b) Threshold frequency
c) Corner frequency
d) None of the mentioned
Answer: c
Explanation: None.
12. The following graph is a spectrum of which noise:
vlsi-questions-answers-mos-noise-concept-q12
a) Thermal noise
b) Gaussian Noise
c) Flicker noise
d) None of the mentioned
Answer: d
Explanation: None.
13. If VIH of the 2nd gate is lower than VOH of the 1st gate, then logic output 0 from the 1st gate is considered as:
a) Logic input 1
b) Uncertain
c) Logic input 0
d) None of the mentioned
Answer: a
Explanation: Logic output 1 from first gate is considered as logic input 1 at second gate as it lies within the range.
14. Input Voltage between VIH and VOH is considered as:
a) Logic Input 1
b) Logic Input 0
c) Uncertain
d) None of the mentioned
Answer: a
Explanation: None.
