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1) Which operations are performed by the bit manipulating instructions of boolean processor?
a.Complement bit
b.Set bit
c.Clear bit
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: All of the above Explanation:
No explanation is available for this question!
2) Which data memory control and handle the operation of several peripherals by assigning them in th category of special function registers?
a.Internal on-chip RAM
b.External off-chip RAM
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Internal on-chip RAM Explanation:
No explanation is available for this question!
3) Why is the speed accessibility of external data memory slower than internal on-chip RAM?
a.Due to multiplexing of lower order byte of address-data bus
b.Due to multiplexing of higher order byte of address-data bus
c.Due to demultiplexing of lower order byte of address-data bus
d.Due to demultiplexing of higher order byte of address-data bus
Answer
ExplanationRelated Ques
ANSWER: Due to multiplexing of lower order byte of address-data bus
Explanation:
No explanation is available for this question!
4) Which control signal/s is/are generated by timing and control unit of 8051 microcontroller in order t the off-chip devices apart from the internal timings?
a.ALE
b.PSEN
c.RD & WR
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: All of the above Explanation:
No explanation is available for this question!
5) Which register usually store the output generated by ALU in several arithmetic and logical operatio
a.Accumulator
b.Special Function Register
c.Timer Register
d.Stack Pointer
Answer
ExplanationRelated Ques
ANSWER: Accumulator Explanation:
No explanation is available for this question!
6) Why is CHMOS technology preferred over HMOS technology for designing the devices of MCS-51 fa
a.Due to higher noise immunity
b.Due to lower power consumption
c.Due to higher speed
d.All of the above
Answer
Explanation
Related Ques
ANSWER: All of the above Explanation:
No explanation is available for this question!
7) Which condition approve to prefer the EPROM/ROM versions for mass production in order to preve external memory connections?
a.size of code < size of on-chip program memory
b.size of code > size of on-chip program memory
c.size of code = size of on-chip program memory
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: size of code < size of on-chip program memory Explanation:
No explanation is available for this question!
8) Which among the below mentioned devices of MCS-51 family does not possess two 16 -bit timers/c
a. 8031
b. 8052
c. 8751
d. All of the above
Answer
ExplanationRelated Ques
ANSWER: 8052
Explanation:
No explanation is available for this question!
9) Which characteristic/s of accumulator is /are of greater significance in terms of its functionality?
a. Ability to store one of the operands before the execution of an instruction
b.Ability to store the result after the execution of an instruction
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Both a & b Explanation:
No explanation is available for this question!
10) Which general purpose register holds eight bit divisor and store the remainder especially after the execution of division operation?
a.A-Register
b.B-Register
c.Registers R0 through R7
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: B-Register Explanation:
No explanation is available for this question!
11) How many registers can be utilized to write the programs by an effective selection of register bank program status word (PSW)?
a.8
b.16
c.32
d.64
Answer
ExplanationRelated Ques
ANSWER: 32
Explanation:
No explanation is available for this question!
12) Which operations are performed by stack pointer during its incremental phase?
a.Push
b.Pop
c.Return
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: Push
Explanation:
No explanation is available for this question!
13) Which is the only register without internal on-chip RAM address in MCS-51?
a.Stack Pointer
b.Program Counter
c.Data Pointer
d.Timer Register
Answer
ExplanationRelated Ques
ANSWER: Program Counter Explanation:
No explanation is available for this question!
14) What kind of instructions usually affect the program counter?
a.Call & Jump
b.Call & Return
c.Push & Pop
d.Return & Jump
Answer
ExplanationRelated Ques
ANSWER: Call & Jump
Explanation:
No explanation is available for this question!
15) What is the default value of stack once after the system undergoes the reset condition?
a.07H
b.08H
c.09H
d.00H
Answer
ExplanationRelated Ques
ANSWER: 07H
Explanation:
No explanation is available for this question!
16) Which bit/s play/s a significant role in the selection of a bank register of Program Status Word (PS
a.RS1
b.RS0
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Both a & b Explanation:
No explanation is available for this question!
17) Which flags represent the least significant bit (LSB) and most significant bit (MSB) of Program Stat (PSW) respectively?
a.Parity Flag & Carry Flag
b.Parity Flag & Auxiliary Carry Flag
c.Carry Flag & Overflow Flag
d.Carry Flag & Auxiliary Carry Flag
Answer
Explanation
Related Ques
ANSWER: Parity Flag & Carry Flag Explanation:
No explanation is available for this question!
18) Which register bank is supposed to get selected if the values of register bank select bits RS1 & Rs detected to be '1' & '0' respectively?
a.Bank 0
b.Bank 1
c.Bank 2
d.Bank 3
Answer
ExplanationRelated Ques
ANSWER: Bank 2
Explanation:
No explanation is available for this question!
19) It is possible to set the auxiliary carry flag while performing addition or subtraction operations onl the carry exceeds
a.1st bit
b.2nd bit
c.3rd bit
d.4th bit
Answer
ExplanationRelated Ques
ANSWER: 3rd bit Explanation:
No explanation is available for this question!
20) Which locations of 128 bytes on-chip additional RAM are generally reserved for special functions?
a.80H to 0FFH
b.70H to 0FFH
c.90H to 0FFH
d.60H to 0FFH
Answer
ExplanationRelated Ques
ANSWER: 80H to 0FFH
Explanation:
No explanation is available for this question!
21) Which commands are used for addressing the off-chip data and associated codes respectively by pointer?
a.MOVX & MOVC
b.MOVY & MOVB
c.MOVZ & MOVA
d.MOVC & MOVY
Answer
ExplanationRelated Ques
ANSWER: MOVX & MOVC
Explanation:
No explanation is available for this question!
22) Which instruction find its utility in loading the data pointer with 16 bits immediate data?
a.MOV
b.INC
c.DEC
d.ADDC
Answer
ExplanationRelated Ques
ANSWER: MOV
Explanation:
No explanation is available for this question!
23) What is the maximum capability of addressing the off-chip data memory & off-chip program memo data pointer?
a.8K
b.16K
c.32K
d.64K
Answer
ExplanationRelated Ques
ANSWER: 64K
Explanation:
No explanation is available for this question!
24) Which among the below stated registers does not belong to the category of special function regist
a.TCON & TMOD
b.TH0 & TL0
c.P0 & P1
d.SP & PC
Answer
ExplanationRelated Ques
ANSWER: SP & PC
Explanation:
No explanation is available for this question!
25) Which timer is attributed to the register pair of RCAP2H & RCAP2L for capture mode operation?
a.Timer 0
b.Timer 1
c.Timer 2
d.Timer 3
Answer
ExplanationRelated Ques
ANSWER: Timer 2 Explanation:
No explanation is available for this question!
26) Which registers are supposed to get copied into RCAP2H & RCAP2L respectively due to the transi 8052 T2EX pin in the capture mode operation?
a.TH0 & TH1
b.TH1 & TH1
c.TH2 & TH2
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: TH2 & TH2
Explanation:
No explanation is available for this question!
27) Which mode of timer 2 allow to hold the reload values with an assistance of RCAP2H & RCAP2L re pair?
a.8 bit auto-reload mode
b.16 bit auto reload mode
c.8 bit capture mode
d.16 bit capture mode
Answer
ExplanationRelated Ques
ANSWER: 16 bit auto reload mode Explanation:
No explanation is available for this question!
28) Where should the pin 19 (XTAL1), acting as an input of inverting amplifier as well as part of an osci circuit, be connected under the application of external clock?
a.to XTAL2
b.to Vcc
c.to GND
d.to ALE
Answer
ExplanationRelated Ques
ANSWER: to GND
Explanation:
No explanation is available for this question!
29) Which port does not represent quasi-bidirectional nature of I/O ports in accordance to the pin conf of 8051 microcontroller?
a.Port 0 (Pins 32-39)
b.Port 1 (Pins 1-8)
c.Port 2 (Pins 21-28)
d.Port 3 (Pins 10-17)
Answer
ExplanationRelated Ques
ANSWER: Port 0 (Pins 32-39)
Explanation:
No explanation is available for this question!
30) What is the required baud rate for an efficient operation of serial port devices in 8051 microcontrol
a. 1200
b. 2400
c. 4800
d. 9600
Answer
ExplanationRelated Ques
ANSWER: 9600
Explanation:
No explanation is available for this question!
a.External Interrupts
b.Internal Interrupts
c.Serial Ports
d.Read / Write Control signals
Answer
ExplanationRelated Ques
ANSWER: Internal Interrupts Explanation:
No explanation is available for this question!
2) What is the constant activation rate of ALE that is optimized periodically in terms of an oscillator fre
a. 1 / 8
b. 1 / 6
c. 1 / 4
d. 1 / 2
Answer
ExplanationRelated Ques
ANSWER: 1 / 6
Explanation:
No explanation is available for this question!
3) Which output control signal is activated after every six oscillator periods while fetching the external program memory and almost remains high during internal program execution?
a.ALE
b.PSEN
c.EA
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: PSEN
Explanation:
No explanation is available for this question!
4) Which memory allow the execution of instructions till the address limit of 0FFFH especially when th External Access (EA) pin is held high?
a.Internal Program Memory
b.External Program Memory
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Internal Program Memory Explanation:
No explanation is available for this question!
5) Which value of disc capacitors is preferred or recommended especially when the quartz crystal is c externally in an oscillator circuit of 8051?
a.10 pF
b.20 pF
c.30 pF
d.40 pF
Answer
ExplanationRelated Ques
ANSWER: 30 pF
Explanation:
No explanation is available for this question!
6) Why are the resonators not preferred for an oscillator circuit of 8051?
a.Because they do not avail for 12 MHz higher order frequencies
b.Because they are unstable as compared to quartz crystals
c.Because cost reduction due to its utility is almost negligible in comparison to total cost of microcontroller boar
d.All of the above
Answer
Explanation
Related Ques
ANSWER: All of the above Explanation:
No explanation is available for this question!
7) Which version of MCS-51 requires the necessary connection of external clock source to XTAL2 in a to the XTAL1 connectivity to ground level?
a.HMOS
b.CHMOS
c.CMOS
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: HMOS
Explanation:
No explanation is available for this question!
8) Which signal from CPU has an ability to respond the clocking value of D- flipflop (bit latch) from the bus?
a.Write-to-Read Signal
b.Write-to-Latch Signal
c.Read-to-Write Signal
d.Read-to-Latch Signal
Answer
ExplanationRelated Ques
ANSWER: Write-to-Latch Signal Explanation:
No explanation is available for this question!
9) Which among the below mentioned statements are precisely related to quasi-bidirectional port?
a. Fixed high pull-up resistors are internally connected
b.Configuration in the form of input pulls the port at higher position whereas they get pulled lower whe configured as a source current
c.It is possible to drive the pin as output at any duration when FET gets turned OFF for an input functio
d.Upper pull-up FET is always OFF with the provision of 'open-drain' output pin for normal operation of
a.A, B, C, D
b.A, B & C
c.A & B
d.C & D
Answer
ExplanationRelated Ques
ANSWER: A, B & C
Explanation:
No explanation is available for this question!
10) What happens when the pins of port 0 & port 2 are switched to internal ADDR and ADDR / DATA bu respectively while accessing an external memory?
a.Ports cannot be used as general-purpose Inputs/Outputs
b.Ports start sinking more current than sourcing
c.Ports cannot be further used as high impedance input
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: Ports cannot be used as general-purpose Inputs/Outputs Explanation:
No explanation is available for this question!
11) The upper 128 bytes of an internal data memory from 80H through FFH usually represent.
a.general-purpose registers
b.special function registers
c.stack pointers
d.program counters
Answer
ExplanationRelated Ques
ANSWER: special function registers Explanation:
No explanation is available for this question!
12) What is the bit addressing range of addressable individual bits over the on-chip RAM?
a.00H to FFH
b.01H to 7FH
c.00H to 7FH
d.80H to FFH
Answer
ExplanationRelated Ques
ANSWER: 00H to 7FH
Explanation:
No explanation is available for this question!
13) What is the divisional range of program memory for internal and external memory portions respect when enable access pin is held high (unity)?
a.0000H - 0FFFH & 1000H - FFFFH
b.0000H - 1000H & 0FFFH - FFFFH
c.0001H - 0FFFH & 01FFH - FFFFH
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: 0000H - 0FFFH & 1000H - FFFFH
Explanation:
No explanation is available for this question!
14) Consider the following statements. Which of them is/are correct in case of program execution relat program memory?
a. External Program memory execution takes place from 1000H through 0FFFFH only when the status o is high (1)
b.External Program memory execution takes place from 0000H through 0FFFH only when the status of low (0)
c.Internal Program execution occurs from 0000H through 0FFFH only when the status of EA pin is held
d.Internal program memory execution occurs from 0000H through 0FFFH only when EA pin is held hig
a.A & C
b.B & D
c.A & B
d.Only A
Answer
ExplanationRelated Ques
ANSWER: B & D
Explanation:
No explanation is available for this question!
15) How does the processor respond to an occurrence of the interrupt?
a.By Interrupt Service Subroutine
b.By Interrupt Status Subroutine
c.By Interrupt Structure Subroutine
d.By Interrupt System Subroutine
Answer
ExplanationRelated Ques
ANSWER: By Interrupt Service Subroutine Explanation:
No explanation is available for this question!
16) Which address/location in the program memory is supposed to get occupied when CPU jump and instantaneously during the occurrence of an interrupt?
a.Scalar
b.Vector
c.Register
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: Vector Explanation:
No explanation is available for this question!
17) Which location specify the storage/loading of vector address during the interrupt generation?
a.Stack Pointer
b.Program Counter
c.Data Pointer
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: Program Counter Explanation:
No explanation is available for this question!
18) Match the following :
a.ISS-------------------------- -- 1. Monitors the status of interrupt pin
b.IER-------------------------- -- 2. Allows the termination of ISS
c.RETI------------------------ -- 3. MCS-51 Interrupts Initialization
d.INTO----------------------- -- 4. Occurrence of high to low transition level
a. A-1, B-2, C-3, D-4
b. A-3, B-2, C-4, D-1
c. A-1, B-3, C-2, D-4
d. A-4, B-3, C-2, D-1
Answer
ExplanationRelated Ques
ANSWER: A-1, B-3, C-2, D-4
Explanation:
No explanation is available for this question!
19) What kind of triggering configuration of external interrupt intimate the signal to stay low until the generation of subsequent interrupt?
a.Edge-Triggering
b.Level Triggering
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Level Triggering Explanation:
No explanation is available for this question!
20) Which among the below mentioned reasons is/are responsible for the generation of Serial Port Inte
a.Overflow of timer/counter 1
b.High to low transition on pin INT1
c.High to low transition on pin INT0
d.Setting of either TI or RI flag
a.A & B
b.Only B
c.C & D
d.Only D
Answer
ExplanationRelated Ques
ANSWER: Only D
Explanation:
No explanation is available for this question!
21) What is the counting rate of a machine cycle in correlation to the oscillator frequency for timers?
a. 1 / 10
b. 1 / 12
c. 1 / 15
d. 1 / 20
Answer
ExplanationRelated Ques
ANSWER: 1 / 12
Explanation:
No explanation is available for this question!
22) Which special function register play a vital role in the timer/counter mode selection process by allo the bits in it?
a.TMOD
b.TCON
c.SCON
d.PCON
Answer
ExplanationRelated Ques
ANSWER: TMOD
Explanation:
No explanation is available for this question!
23) How many machine cycle/s is/are executed by the counters in 8051 in order to detect '1' to '0' trans the external pin?
a.One
b.Two
c.Four
d.Eight
Answer
ExplanationRelated Ques
ANSWER: Two
Explanation:
No explanation is available for this question!
24) Which bit must be set in TCON register in order to start the 'Timer 0' while operating in 'Mode 0'?
a.TR0
b.TF0
c.IT0
d.IE0
Answer
ExplanationRelated Ques
ANSWER: TR0
Explanation:
No explanation is available for this question!
25) Which among the following control/s the timer1 especially when it is configured as a timer in mode where gate and TR1 bits are attributed to be '1” in TMOD register?
a.TR1
b.External input at (INT1)
c.TF1
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: External input at (INT1) Explanation:
No explanation is available for this question!
26) Which timer mode exhibit the necessity to generate the interrupt by setting EA bit in IE enhancing program counter to jump to another vector location?
a.Mode 0
b.Mode 1
c.Mode 2
d.Mode 3
Answer
ExplanationRelated Ques
ANSWER: Mode 1
Explanation:
No explanation is available for this question!
27) Consider the below generated program segment for initializing Timer 1 in Mode 1 operation :
MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C SET C ET1
SETC TR0 SJMP $
Which among the below mentioned program segments represent the correct code?
a.MOV SP, # 54 H
MOV TCON ,# 0010 0000 C SETC ET1
SETC TR0 SJMP $
b.MOV SP, # 54H
MOV TMOD ,# 0010 0000 C SETC ET0
SETC TR0 SJMP $
c.MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C SETC ET1
SETC TR1 SETC EA SJMP $
d.MOV SP, # 54 H
MOV TMOD ,# 0010 0000 C SETC ET0
SETC TR1
SETC EA SJMP $
Answer
ExplanationRelated Ques
ANSWER: MOV SP, # 54 H MOV TMOD ,# 0010 0000 C SETC ET1
SETC TR1 SETC EA SJMP $
Explanation:
No explanation is available for this question!
28) What is the maximum delay generated by the 12 MHz clock frequency in accordance to an auto-rel mode (Mode 2) operation of the timer?
a.125 μs
b.250 μs
c.256 μs
d.1200 μs
Answer
ExplanationRelated Ques
ANSWER: 256 μs
Explanation:
No explanation is available for this question!
29) Which among the below mentioned sequence of program instructions represent the correct chron order for the generation of 2kHz square wave frequency?
1. MOV TMOD, 0000 0010 B
2.MOV TL0, # 06H
3.MOV TH0, # 06H
4.SETB TR0
5.CPL p1.0
6.ORG 0000H a. 6, 5, 2, 4, 1, 3
b. 6, 1, 3, 2, 4, 5
c. 6, 5, 4, 3, 2, 1
d. 6, 2, 4, 5, 1, 3
Answer
ExplanationRelated Ques
ANSWER: 6, 1, 3, 2, 4, 5
Explanation:
No explanation is available for this question!
30) Why is it not necessary to specify the baud rate to be equal to the number of bits per second?
a.Because each bit is preceded by a start bit & followed by one stop bit
b.Because each byte is preceded by a start byte & followed by one stop byte
c.Because each byte is preceded by a start bit & followed by one stop bit
d.Because each bit is preceded by a start byte &followed by one stop byte
Answer
ExplanationRelated Ques
ANSWER: Because each byte is preceded by a start bit & followed by one stop bit Explanation:
No explanation is available for this question!
c. Status of Parity bits
d. All of the above
Answer
ExplanationRelated Ques
ANSWER: All of the above Explanation:
No explanation is available for this question!
2) Which bits exhibit and signify the termination phase of the character transmission and reception in special function register?
a.Control bits
b.Status bits
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Status bits Explanation:
No explanation is available for this question!
3) Which two bits are supposed to be analyzed/tested for unity value (1) in SCON for the reception of b mode 1 serial communication?
a.RI & TI
b.REN & RB8
c.RI & REN
d.TI & RB8
Answer
ExplanationRelated Ques
ANSWER: RI & REN
Explanation:
No explanation is available for this question!
4) What is the bit transmitting or receiving capability of mode 1 in serial communication?
a.8 bits
b.10 bits
c.11 bits
d.12 bits
Answer
ExplanationRelated Ques
ANSWER: 10 bits Explanation:
No explanation is available for this question!
5) Which pin in the shift register mode (Mode 0) of serial communication allow the data transmission a reception?
a.TXD
b.RXD
c.RB8
d.REN
Answer
ExplanationRelated Ques
ANSWER: RXD
Explanation:
No explanation is available for this question!
6) How is the baud rate determined on the basis of system clock frequency (fsc) in accordance to mode serial communication?
a.(oscillator frequency) / 12
b.[2SMOD / 32] x (oscillator frequency) / [12 x (256 – (TH1)]
c.[2SMOD / 64] x (oscillator frequency)
d.2SMOD/ 32 x (Timer 1 overflow rate)
Answer
ExplanationRelated Ques
ANSWER: (oscillator frequency) / 12
Explanation:
No explanation is available for this question!
7) Which serial modes possess the potential to support the multi-processor type of communication?
a.Modes 0 & 1
b.Modes 1 & 2
c.Modes 2 & 3
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: Modes 2 & 3 Explanation:
No explanation is available for this question!
8) How does it become possible for 9th bit to differentiate the address byte from the data byte during th transmission process in multiprocessor communication?
a.By recognizing 9th bit as '1' for address byte & '0' for data byte
b.By recognizing 9th bit as '0' for address byte & '1' for data byte
c.By recognizing 9th bit as '1' for address as well as data bytes
d.By recognizing 9th bit as '0' for address as well as data bytes
Answer
ExplanationRelated Ques
ANSWER: By recognizing 9th bit as '1' for address byte & '0' for data byte Explanation:
No explanation is available for this question!
9) Which byte has the capability to interrupt the slave when SM2 bit is assigned to be '1' after the initia process in the multiprocessor mode of communication?
a.Address byte
b.Data byte
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Address byte Explanation:
No explanation is available for this question!
10) Which bits of opcode specify the type of registers to be used in the register addressing mode?
a.LSB
b.MSB
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: LSB
Explanation:
No explanation is available for this question!
11) Which base-register is preferred for address calculation of a byte that is to be accessed from prog memory by base-register plus register-indirect addressing mode?
a.DPTR
b.PSW
c.PCON
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: DPTR
Explanation:
No explanation is available for this question!
12) What does the symbol '#' represent in the instruction MOV A, #55H?
a.Direct datatype
b.Indirect datatype
c.Immediate datatype
d.Indexed datatype
Answer
ExplanationRelated Ques
ANSWER: Immediate datatype Explanation:
No explanation is available for this question!
13) How many single byte, two-byte and three-byte instructions are supported by MCS-51 from the ove instruction set?
a.55 - single byte, 35 two-byte & 21 three-byte instructions
b.50 - single byte, 30 two-byte & 31 three-byte instructions
c.42 - single byte, 45 two-byte & 24 three-byte instructions
d.45 - single byte, 45 two-byte & 17 three-byte instructions
Answer
ExplanationRelated Ques
14) What kind of PSW flags remain unaffected by the data transfer instructions?
a.Auxillary Carry Flags
b.Overflow Flags
c.Parity Flags
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: All of the above Explanation:
No explanation is available for this question!
15) Which instruction should be adopted for moving an accumulator to the register from the below me mnemonics?
a.MOV A, Rn
b.MOV A, @ Ri
c.MOV Rn, A
d.MOV direct, A
Answer
ExplanationRelated Ques
ANSWER: MOV Rn, A
Explanation:
No explanation is available for this question!
16) What does the instruction XCHD A, @Ri signify during the data transfer in the program execution?
a.Exchange of register with an accumulator
b.Exchange of direct byte with an accumulator
c.Exchange of indirect RAM with an accumulator
d.Exchange of low order digit indirect RAM with an accumulator
Answer
ExplanationRelated Ques
ANSWER: Exchange of low order digit indirect RAM with an accumulator Explanation:
No explanation is available for this question!
17) Which flag allow to carry out the signed as well as unsigned addition and subtraction operations?
a.CY
b.OV
c.AC
d.F0
Answer
ExplanationRelated Ques
ANSWER: OV
Explanation:
No explanation is available for this question!
18) How many bytes are supposed to get occupied while subtracting indirect RAM from an accumulato with borrow under the execution of SUBB A, @Ri?
a.1
b.2
c.3
d.4
Answer
ExplanationRelated Ques
ANSWER: 1
Explanation:
No explanation is available for this question!
19) What can be the oscillator period for the multiplication operation of A & B in accordance to 16-bit especially in B:A registers?
a.12
b.24
c.36
d.48
Answer
ExplanationRelated Ques
ANSWER: 48
Explanation:
No explanation is available for this question!
20) Which form of instructions also belong to the category of logical instructions in addition to bitwise instructions?
a.Single-operand instructions
b.Rotate instructions
c.Swap instructions
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: All of the above Explanation:
No explanation is available for this question!
21) Which rotate instruction/s has an ability to modify CY flag by moving the bit-7 & bit-0 respectively accumulator?
a.RR & RL
b.RLC & RRC
c.RR & RRC
d.RL & RLC
Answer
ExplanationRelated Ques
ANSWER: RLC & RRC
Explanation:
No explanation is available for this question!
22) Which among the single operand instructions complement the accumulator without affecting any o flags?
a.CLR
b.SETB
c.CPL
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: CPL
Explanation:
No explanation is available for this question!
23) Match the following
a.JC rel----------------- -- 1. Jump if direct bit is set & clear bit
b.JNC rel---------------- -- 2. Jump if direct bit is set
c.JB bit, rel------------- -- 3. Jump if direct bit is not set
d.JBC bit, rel---------- -- 4. Jump if carry is set
e.JNB bit, rel----------- -- 5. Jump if carry is not set
a. A-3, B-2, C-1, D-4, E-5
b. A-5, B-2, C-4, D-1, E-3
c. A-5, B-4, C-3, D-2, E-1
d. A-4, B-5, C-2, D-1, E-3
Answer
ExplanationRelated Ques
ANSWER: A-4, B-5, C-2, D-1, E-3
Explanation:
No explanation is available for this question!
24) What is the possible range of transfer control for 8-bit relative address especially in 2's compleme with respect to the first byte of preceding instruction?
a.-115 to 132 bytes
b.-130 to 132 bytes
c.-128 to 127 bytes
d.-115 to 127 bytes
Answer
ExplanationRelated Ques
ANSWER: -128 to 127 bytes Explanation:
No explanation is available for this question!
25) Which among the category of program branching instructions allow 16 bit address to be specified jump anywhere within 64K block of program memory?
a.Long jumps (LJMP)
b.Short jumps (SJMP)
c.Absolute jumps (AJMP)
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: Long jumps (LJMP) Explanation:
No explanation is available for this question!
26) Consider the below mentioned statements. Which among them is /are approved to be incorrect in c calling instructions of program branching?
a.Absolute Calls instructions specify 11-bit address and calling subroutine within 2K program memory
b.Long call instructions specify 16-bit address and subroutine anywhere within 64K program memory
c.Short call instructions specify 16-bit address and subroutine within 4K program memory block
d.All long call and short call instructions specify 11 bit address and the calling subroutine within 16K p memory block
a.Only A
b.B & D
c.A & C
d.C & D
Answer
ExplanationRelated Ques
ANSWER: C & D
Explanation:
No explanation is available for this question!
27) Match the following instruction mnemonics with their description.
a.CJNE A,direct,rel---------- -- 1. Compare immediate to indirect and Jump if not equal
b.CJNE A,#data,rel---------- -- 2. Compare direct byte to accumulator and Jump if not equal
c.CJNE @Ri, #data,rel----- -- 3. Compare immediate to register and Jump if not equal
d.CJNE Rn, # data rel------ -- 4. Compare immediate to accumulator and Jump if not equal
a. A-1, B-2, C-3, D-4
b. A-2, B-4, C-1, D-3
c. A-4, B-3, C-2, D-1
d. A-2, B-4, C-3, D-1
Answer
Explanation
Related Ques
ANSWER: A-2, B-4, C-1, D-3
Explanation:
No explanation is available for this question!
28) What is the correct chronological order of the following steps involved in the LCALL operation?
1.Load the value of 16-bit destination address to program counter
2.Increment of the program counter by value '3'
3.Storage of the higher byte of program counter on the stack
4.Increment of the stack pointer by value'1'
5.Storage of the lower byte of program counter on the stack
6.Increment in the value of stack pointer
a. 5, 3, 1, 6, 2, 4
b. 1, 3, 2, 5, 4, 6
c. 2, 4, 5, 6, 3, 1
d. 5, 3, 6, 2, 4, 1
Answer
ExplanationRelated Ques
ANSWER: 2, 4, 5, 6, 3, 1
Explanation:
No explanation is available for this question!
29) What is the status of stack pointer for the execution of PUSH and POP operations?
a.It gets post-decremented for PUSH & pre-incremented for POP
b.It gets pre-incremented for PUSH & post-decremented for POP
c.It gets pre-incremented for PUSH as well as POP
d.It gets post-decremented for PUSH as well as POP
Answer
ExplanationRelated Ques
ANSWER: It gets pre-incremented for PUSH & post-decremented for POP
Explanation:
No explanation is available for this question!
30) What does the following pictorial representation of PUSH operation in the stack pointer indicate a below stated conclusions/inferences?
Stack Pointer is incremented by 2
Location 55H in on-chip stack memory gets loaded with 44H
Stack Pointer gets initialized by 56H
Data Pointer gets loaded with an immediate data 44H which ultimately leads to initialization of stack
Only A
Only B
B & D
Related Ques
Explanation
C & D
Answer
ANSWER: C & D
Explanation:
No explanation is available for this question!
31) Which instructions contribute to an effective adoption or utilization of stack memory which usually crucial role in storage of intermediate results?
a.ACALL
b.RETI
c.PUSH & POP
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: All of the above Explanation:
No explanation is available for this question!
1) Which functioning element of microcontroller generate and transmit the address of instructions to through internal bus?
a.Instruction Decoding Unit
b.Timing and Control Unit
c.Program Counter
d.Arithmetic Logic Unit
Answer
ExplanationRelated Ques
ANSWER: Program Counter Explanation:
No explanation is available for this question!
2) How does the microcontroller communicate with the external peripherals/memory?
a.via I/O ports
b.via register arrays
c.via memory
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: via I/O ports
Explanation:
No explanation is available for this question!
3) Why do the microprocessors possess very few bit manipulating instructions?
a.Because they mostly operate on bits/ word data
b.Because they mostly operate on byte/word data
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Because they mostly operate on byte/word data Explanation:
No explanation is available for this question!
4) Which minimum mode signal is used for demultiplexing the data and address lines with the assista external latch in a microprocessor while accessing memory segment?
a.INTA
b.DTE
c.HOLD
d.ALE
Answer
ExplanationRelated Ques
ANSWER: ALE
Explanation:
No explanation is available for this question!
5) Which word size is approved to be of greater importance for performing the small computational tas with its storage usability feature adopted by ASCII code?
a.4-bit
b.8-bit
c.16-bit
d.32-bit
Answer
Explanation
Related Ques
ANSWER: 8-bit
Explanation:
No explanation is available for this question!
6) Which among the below stated statements does not exhibit the characteristic feature of 16-bit microcontroller?
a.Large program & data memory spaces
b.High speed
c.I/O Flexibility
d.Limited Control Applications
Answer
ExplanationRelated Ques
ANSWER: Limited Control Applications Explanation:
No explanation is available for this question!
7) Which microcontrollers offer the provisional and salient software features of fault handling capabilit interrupt vector efficiency and versatile addressing?
a.TMS 1000 (4 bit)
b.TMS 7500 (8 bit)
c.Intel 8096 (16 bit)
d.Intel 80960 (32 bit)
Answer
ExplanationRelated Ques
ANSWER: Intel 80960 (32 bit)
Explanation:
No explanation is available for this question!
8) Which category of microcontrollers acquire the complete hardware configuration on its chip so as t particular application?
a.Embedded Memory Microcontrollers
b.External Memory Microcontrollers
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Embedded Memory Microcontrollers Explanation:
No explanation is available for this question!
9) External Memory Microcontrollers can overcome the limitations of insufficient in-built program and memory by allowing the connections of external memory using
a.Serial Port Pins as address and data lines
b.Parallel Port Pins as address and data lines
c.Parallel Port Pins as address and control lines
d.Serial Port Pins as address and control lines
Answer
ExplanationRelated Ques
ANSWER: Parallel Port Pins as address and data lines Explanation:
No explanation is available for this question!
10) How are the address and data buses removed in external memory type of microcontrollers?
a.Through demultiplexing by external latch & ALE signal
b.Through demultiplexing by external latch & DLE signal
c.Through multiplexing by external latch & DLE signal
d.Through multiplexing by external latch & ALE signal
Answer
ExplanationRelated Ques
ANSWER: Through multiplexing by external latch & ALE signal Explanation:
No explanation is available for this question!
11) What are the significant designing issues/factors taken into consideration for RISC Processors?
a.Simplicity in Instruction Set
b.Pipeline Instruction Optimization
c.Register Usage Optimization
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: All of the above Explanation:
No explanation is available for this question!
12) What does the compact and uniform nature of instructions in RISC processors facilitate to?
a.Compiler optimization
b.Pipelining
c.Large memory footprints
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Pipelining Explanation:
No explanation is available for this question!
13) Which register of current procedure resemble physically similar to the parameter register of called procedure during register to register operation in an overlapping window of RISC Processors?
a.Local Register
b.Temporary Register
c.Parameter Register
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: Temporary Register Explanation:
No explanation is available for this question!
14) Which architectural scheme has a provision of two sets for address & data buses between CPU an memory?
a.Harvard architecture
b.Von-Neumann architecture
c.Princeton architecture
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: Harvard architecture Explanation:
No explanation is available for this question!
15) Which factors/parameters contribute to an effective utilization or adoption of Harvard architecture of the DSPs for streaming data?
a.Greater memory bandwidth
b.Predictable nature of bandwidth
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Both a & b Explanation:
No explanation is available for this question!
16) Which kind of multiplexing scheme is adopted by Von-Newman architecture especially for program data fetching purposes?
a.Time Division Multiplexing
b.Frequency Division Multiplexing
c.Statistical Time Division Multiplexing
d.Code Division Multiplexing
Answer
ExplanationRelated Ques
ANSWER: Time Division Multiplexing Explanation:
No explanation is available for this question!
17) Which feature deals with the fetching of next instruction during the execution of current instructio irrespective of the memory access?
a.Fetching
b.Pre-fetching
c.Fetch & Decoding
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: Pre-fetching Explanation:
No explanation is available for this question!
18) What are the essential tight constraint/s related to the design metrics of an embedded system?
a.Ability to fit on a single chip
b.Low power consumption
c.Fast data processing for real-time operations
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: All of the above Explanation:
No explanation is available for this question!
19) Which abstraction level undergo the compilation process by converting a sequential program into state machine and register transfers while designing an embedded system?
a.System
b.Behaviour
c. RT
d. Logic
Answer
ExplanationRelated Ques
ANSWER: Behaviour Explanation:
No explanation is available for this question!
20) Which characteristics of an embedded system exhibit the responsiveness to the assortments or va in system's environment by computing specific results for real-time applications without any kind of postponement?
a.Single-functioned Characteristics
b.Tightly-constraint Characteristics
c.Reactive & Real time Characteristics
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: Reactive & Real time Characteristics Explanation:
No explanation is available for this question!
21) Which lines are utilized during the enable state of hardware flow control in DTE and DCE devices o RS232?
a.CD & IR
b.DSR & DTR
c.RTS & CTS
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: RTS & CTS
Explanation:
No explanation is available for this question!
22) Which among the below stated lines represent the handshaking variant usually and only controlled software in the handshaking process?
a.XON/ XOFF
b.DCD & GND
c.TxD & RxD
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: XON/ XOFF
Explanation:
No explanation is available for this question!
23) Match the following registers with their functions :
a.Line Status Register------------------ -- 1. Set Up the communication parameters
b.Line Control Register---------------- -- 2. Sharing of similar addresses
c.Transmit & Receive Buffers------- -- 3. Status Determination of Tx & Rr
a. A-2, B-1, C-3
b. A-1, B-2, C-3
c. A-3, B-1, C-2
d. A-3, B-2, C-1
Answer
ExplanationRelated Ques
ANSWER: A-3, B-1, C-2
Explanation:
No explanation is available for this question!
24) Which protocol standard of serial communication specify the bi-directional and half-duplex form o transmission by allowing various numbers of drivers and receivers in bus configuration?
a.RS232
b.RS2485
c. RS422
d. RS423
Answer
ExplanationRelated Ques
ANSWER: RS2485
Explanation:
No explanation is available for this question!
25) What is the maximum device handling capacity of serial standard protocol RS485 in terms of drive receivers on a single line?
a.8
b.10
c.16
d.32
Answer
ExplanationRelated Ques
ANSWER: 32
Explanation:
No explanation is available for this question!
26) Which mechanism automates the enabling of RS485 transceiver with an elimination of hardware h line during each time of the data transmission?
a.RTS Control
b.Send Data Control
c.Tri-State Control
d.Bit-wise Enable Timing Control
Answer
ExplanationRelated Ques
ANSWER: Send Data Control Explanation:
No explanation is available for this question!
27) What does an IC that initiate or enable the data transfer on bus can be regarded as, in accordance protocol specifications?
a.Bus Master
b.Bus Slaves
c.Bus Drivers
d.Bus Data Carriers
Answer
ExplanationRelated Ques
ANSWER: Bus Master Explanation:
No explanation is available for this question!
28) What is the directional nature of two active wires SDA & SCL usually adopted in I2C Bus for carryi information between the devices?
a.Uni-directional
b.Bi-directional
c.Multi-directional
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Bi-directional Explanation:
No explanation is available for this question!
29) Which potential mode of operation indicate the frequent sending of byte to the slave correspondin reception of an acknowledge signal when it becomes desirable for the master to write to the slave durin transmission in I2C bus?
a.Master in master-transmit mode & Slave in slave-receive mode
b.Slave in slave-transmit mode & Master in master-receive mode
c.Master in master-transmit mode as well as master-receive mode
d.Slave in slave-transmit mode as well as slave-receive mode
Answer
ExplanationRelated Ques
ANSWER: Master in master-transmit mode & Slave in slave-receive mode Explanation:
No explanation is available for this question!
30) Which processor has the necessity of manual optimization for the generation of assembly languag especially for the embedded systems?
a.RISC
b.CISC
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: CISC
Explanation:
No explanation is available for this question!
1) Which among the below stated salient feature/s of SPI contribute to the wide range of its applicabilit
a.Simple hardware interfacing
b.Full duplex communication
c.Low power requirement
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: All of the above Explanation:
No explanation is available for this question!
2) Which characteristic/s of two-wire interface (TWI) make it equally valuable in comparison to serial-p interface (SPI)?
a.Less number of pins on IC packages than SPI
b.It possesses formal standard unlike SPI
c. Slave Addressing before communication & better hardware control
d. All of the above
Answer
Explanation
ANSWER: All of the above Explanation:
No explanation is available for this question!
3) What is the maximum speed of operating frequency exhibited by SPI as compared to that of TWI?
a.Less than 10 MHz
b.Greater than 10 MHz
c.Equal to 10 MHz
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Greater than 10 MHz Explanation:
No explanation is available for this question!
4) Which development tool/program has the potential to allocate the specific addresses so as to load t object code into memory?
a.Loader
b.Locator
c.Library
d.Linker
Answer
ExplanationRelated Ques
ANSWER: Locator Explanation:
No explanation is available for this question!
5) The assembler list file generated by an assembler mainly includes
a.binary codes
b.assembly language statements
c.offset for each instruction
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: All of the above Explanation:
No explanation is available for this question!
6) Which kind of assembler do not generate the programs in similar language as that used by micro-co by developing the program in high-level languages making them as machine independent?
a.Macro Assembler
b.Cross Assembler
c.Meta Assembler
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: Cross Assembler Explanation:
No explanation is available for this question!
7) What kind of address/es is /are usually assigned to program by the linker adopted in an execution o assembler?
a.Absolute Address
b.Relative Address starting from unity
c.Relative Addresss starting from zero
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Relative Addresss starting from zero Explanation:
No explanation is available for this question!
8) What are the major form of functionalities associated to high-level language compilers?
a.Generation of an application program
b.Conversion of generated code from higher level language to machine-level language
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Both a & b Explanation:
No explanation is available for this question!
9) Which development tool can facilitate the creation and modification of source programs in addition assembly and higher -level languages?
a.Editor
b.Assembler
c.Debugger
d.High-level language Compiler
Answer
ExplanationRelated Ques
ANSWER: Editor Explanation:
No explanation is available for this question!
10) EPROM Programming versions are of greater significance to designers for
a.Debugging of hardware prototype
b.Debugging of software prototype
c.Loading the programs in microcontrollers
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: All of the above
Explanation:
No explanation is available for this question!
11) It is a characteristic provision of some debuggers to stop the execution after each instruction because
a.it facilitates to analyze or vary the contents of memory and register
b.it facilitates to move the break point to a later point
c.it facilitates to rerun the program
d.it facilitates to load the object code program to system memory
Answer
ExplanationRelated Ques
ANSWER: it facilitates to analyze or vary the contents of memory and register Explanation:
No explanation is available for this question!
12) Which component is replaced by an in-circuit emulator on the development board for testing purp
a.RAM
b.I/O Ports
c.Micro-controller IC
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: Micro-controller IC Explanation:
No explanation is available for this question!
13) It is feasible for an in-circuit emulator to terminate at the middle of the program execution so as to the contents of
a.memory
b.registers
c.Both a & b
d.
Answer
Explanation
Related Ques
ANSWER: Both a & b Explanation:
No explanation is available for this question!
14) Which operations are not feasible to perform by simulator programs in accordance to real time programming?
a.Memory Operations
b.I/O Operations
c.Register Operations
d.Debugging Operations
Answer
ExplanationRelated Ques
ANSWER: I/O Operations Explanation:
No explanation is available for this question!
15) What is/are the possible way/s of displaying the data by logic analyzer?
a.Logic state format
b.Hexadecimal & Map format
c.Timing diagram format
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: All of the above Explanation:
No explanation is available for this question!
16) Which type of triggering allow the trigger qualifier circuit to compare the input data word with the programmed by the user in logic analyzer?
a.Triggering from external input
b.Programmable Triggering
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Programmable Triggering Explanation:
No explanation is available for this question!
17) Which mandatory contents can be visualized by the hexadecimal display format of a logic analyzer
a.Data Bus
b.Address Bus
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Both a & b Explanation:
No explanation is available for this question!
18) How many samples can be displayed before and after the trigger respectively if the trigger-pulse is by center-trigger mode to display 1024 bit counts?
a.512 & 512 samples respectively
b.512 & 1024 samples respectively
c.1024 & 512 samples respectively
d.1024 & 1024 samples respectively
Answer
ExplanationRelated Ques
ANSWER: 1024 & 1024 samples respectively Explanation:
No explanation is available for this question!
19) What is/are the consequences of driving the LED in the form of an output function?
a.Pin sources the current when made low without glowing LED
b.Pin sinks the current when made high without glowing LED
c.Pin sources the current when made high by glowing LED
d.Pin sinks the current when made low by glowing LED
Answer
ExplanationRelated Ques
ANSWER: Pin sinks the current when made low by glowing LED Explanation:
No explanation is available for this question!
20) What is the possible range of current limiting resistor essential for lightening the LED in certain applications after pressing the push-button?
a. 25-55 Ω
b. 55-110 Ω
c. 110-220 Ω
d. 220-330 Ω
Answer
ExplanationRelated Ques
ANSWER: 220-330 Ω
Explanation:
No explanation is available for this question!
21) Which among the below given assertions exhibits the dependency of LED status over them, espec LED and push button connection?
a.Closure of pushbutton
b.Low Output pin driven by microcontroller
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Both a & b
Explanation:
No explanation is available for this question!
22) What does the availability of LCD in 16 x 2 typical value indicate?
a.16 lines per character with 2 such lines
b.16 characters per line with 2 such lines
c.16 pixels per line with 2 such sets
d.16 lines per pixel with two such sets
Answer
ExplanationRelated Ques
ANSWER: 16 characters per line with 2 such lines Explanation:
No explanation is available for this question!
23) Which control line/s act/s as an initiator by apprising LCD about the inception of data transmission microcontroller?
a.Enable (EN)
b.Register Select (RS)
c.Read/Write (RW)
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: Enable (EN)
Explanation:
No explanation is available for this question!
24) The display operations in LCD are undertaken on EN line with
a.0 to 1 transitions
b.1 to 0 transitions
c.Both a & b
d.
Answer
Explanation
Related Ques
ANSWER: 1 to 0 transitions Explanation:
No explanation is available for this question!
25) When can a LCD display the text form of data?
a.only when RS line is high
b.only when RW line is high
c.only when RS line is low
d.only when RW line is low
Answer
ExplanationRelated Ques
ANSWER: only when RS line is high Explanation:
No explanation is available for this question!
26) How does the instruction execute for read command 'Get LCD Status' in LCD?
a.By allowing EN line to go from low to high
b.By allowing EN line to go from high to low
c.By maintaining EN line to be stable
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: By allowing EN line to go from high to low Explanation:
No explanation is available for this question!
27) Match the HEX codes of LCD with their associated functions
a.10H----------------- 1) Shifting of cursor position to right
b.14H----------------- 2) Shifting of cursor position to left
c. 18H----------------- 3) 2 lines & 5 x 7 character font
d. 38H----------------- 4) Shifting of an entire display to the left
a. A-4, B–1, C-2, D-3
b. A-3, B–2, C-1, D-4
c. A-2, B-1, C-4, D-3
d. A-1, B–2, C-3, D-4
Answer
ExplanationRelated Ques
ANSWER: A-2, B-1, C-4, D-3
Explanation:
No explanation is available for this question!
28) How much delay is necessarily provided after the power-on-reset condition in order to overcome t predicaments related to valid power supply levels assigned to microcontroller and LCD?
a.10 ms
b.12 ms
c.15 ms
d.25 ms
Answer
ExplanationRelated Ques
ANSWER: 15 ms
Explanation:
No explanation is available for this question!
29) On which factors do the delay between two characters depend for display purposes in LCD?
a.Clock frequency
b.Display module
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Both a & b
Explanation:
No explanation is available for this question!
30) How many data lines are essential in addition to RS, EN and RW control lines for interfacing LCD w Atmel 89C51 microcontroller?
a.3
b.5
c.8
d.10
Answer
ExplanationRelated Ques
ANSWER: 8
Explanation:
No explanation is available for this question
1) Which is the an alternative mechanism of preventing the software to be dependent on several delay along with an optimum time proficiency of checking LCD status at the interfacing level?
a.Polling of DB7 bit of the data bus
b.Updating the faster display in less time
c.Generalization of clock frequency and display module
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: Polling of DB7 bit of the data bus Explanation:
No explanation is available for this question!
2) What is the purpose of using Schmitt Trigger in the hardware circuit for key debouncing?
a.Noise Elimination
b.Improvement in Noise Immunity
c.Increase in Noise Figure
d.Reduction in Noise Temperature
Answer
Explanation
Related Ques
ANSWER: Improvement in Noise Immunity Explanation:
No explanation is available for this question!
3) Which lines are driven low under the software control during interfacing HEX keyboard with PIC 16F
a.Scan Lines
b.Return Lines
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Scan Lines Explanation:
No explanation is available for this question!
4) Which keys are encoded for scan lines with '1101' value (RB1 low) condition?
a. 0, 4, 8, C
b. 1, 5, 9, D
c. 2, 6, A, E
d. 3, 7, B, F
Answer
ExplanationRelated Ques
ANSWER: 2, 6, A, E
Explanation:
No explanation is available for this question!
5) What value of 'B' should be loaded in the TRISB register if return lines (RB7:RB4) and RB3:RB0 are supposed to be inputs and outputs respectively after the PORT B initialization?
a. 11000100
b. 11110011
c. 11110001
d. 11110000
Answer
ExplanationRelated Ques
ANSWER: 11110000
Explanation:
No explanation is available for this question!
6) Which pin should be set low along with the program counter contents more than 0FFFH for accessi external program memory?
a.EA
b.ALE
c.PSEN
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: EA
Explanation:
No explanation is available for this question!
7) Which essential operation should be performed while reading the external program byte on the data
a.Latching of lower address byte
b.Latching of higher address byte
c.Latching of any addressable byte irrespective of priority level
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Latching of lower address byte Explanation:
No explanation is available for this question!
8) Which bus/es acquire/s the potential of liberally receiving the code byte after addressing the lower address byte?
a.Data bus
b.Address bus
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Data bus Explanation:
No explanation is available for this question!
9) What happens when the RD signal becomes low during the read cycle?
a.Data byte gets loaded from external data memory to data bus
b.Address byte gets loaded from external data memory to address bus
c.Data byte gets loaded from external program memory to data bus
d.Address byte gets loaded from external program memory to address bus
Answer
ExplanationRelated Ques
10) Which among the below mentioned memory components possessess the potential of generating a signal for the latching purpose of lower address byte in an external data memory?
a.CPU
b.Data Bus
c.Port 0
d.Port 1
Answer
ExplanationRelated Ques
ANSWER: CPU
Explanation:
No explanation is available for this question!
11) Which ports assist in addressing lower order and higher address bytes into the data bus simultane while accessing the external data memory?
a.Port 0 & Port 1 respectively
b.Port 1 & Port 2 respectively
c.Port 0 & Port 2 respectively
d.Port 2 & Port 3 respectively
Answer
ExplanationRelated Ques
ANSWER: Port 0 & Port 2 respectively Explanation:
No explanation is available for this question!
12) What happens when the latch is kept open once after the execution of the latch operation by allowi digital data byte to appear at the output?
a.Variation in an input digital data
b.Output data remains constant despite changing input digital data
c.Variation in an output data with respect to input data variation
d.Cannot predict
Answer
ExplanationRelated Ques
ANSWER: Output data remains constant despite changing input digital data Explanation:
No explanation is available for this question!
13) How is the latch interfacing with the microcontroller related to the number of digital output functio
a.It increases the number of digital output functions in a time multiplexed manner
b.It decreases the number of digital output functions in a time multiplexed manner
c. It increases the number of digital output functions in a frequency multiplexed manner
d. It decreases the number of digital output functions in a frequency multiplexed manner
Answer
ExplanationRelated Ques
ANSWER: It increases the number of digital output functions in a time multiplexed manner Explanation:
No explanation is available for this question!
14) What is the correct chronological order/sequence of steps associated with the latch operations giv below?
a.Loading the data on output port
b.Increment in the digital output functions by using microcontroller pins
c.Application of latch enable signal to desired latch
a.A, B, C
b.A, C, B
c.C, A, B
d.B, A, C
Answer
ExplanationRelated Ques
ANSWER: A, C, B
Explanation:
No explanation is available for this question!
15) In an electromechanical relay, the necessity of connecting an external base resistance arises only
a.in the presence of an internal pull-up resistor
b.in the absence of an internal pull-up resistor
c.in the absence of an internal push-up resistor
d.in the presence of an internal push-up resistor
Answer
ExplanationRelated Ques
ANSWER: in the absence of an internal pull-up resistor
Explanation:
No explanation is available for this question!
16) Which diodes are employed in the electromechanical relays since the inductor current cannot be r to zero?
a.Tunnel Diode
b.Shockley Diode
c.Freewheeling Diode
d.Zener Diode
Answer
ExplanationRelated Ques
ANSWER: Freewheeling Diode Explanation:
No explanation is available for this question!
17) Where do the power gets dissipated during the gradual decay of an inductor current (upto zero val turning OFF the transistor in an electromechanical relay?
a.Internal resistance of the coil
b.Internal Diode resistance
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Both a & b Explanation:
No explanation is available for this question!
18) Which factors indicate the necessity of sample and hold circuit in the process of analog-to-digital conversion?
a.Instantaneous variation in an input signal
b.Analog-to-digital conversion time
c. Both a & b
d. None of the above
Answer
ExplanationRelated Ques
ANSWER: Both a & b Explanation:
No explanation is available for this question!
19) Which pin/signal of ADC AD571 interfacing apprises about the accomplishment of data reading in microcontroller so as to indicate ADC to get ready for the next data sample?
a.BLANK /CONVERT (high)
b.BLANK/DR (low)
c.DATA READY (DR)
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: BLANK /CONVERT (high)
Explanation:
No explanation is available for this question!
20) Which errors are more likely to get generated by conversion time and ADC resolution respectively accordance to the digital signal processing?
a.Sampling & Quantization Errors
b.Systematic & Random Errors
c.Overload & Underload Errors
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: Sampling & Quantization Errors Explanation:
No explanation is available for this question!
21) What is the purpose of blanking (BI) associated with the 7-segment display operations?
a.To turn ON the display
b.To turn OFF the display
c.To pulse modulate the brightness of display
d.To pulse modulate the lightness of display
a.B & C
b.A & D
c.A & B
d.C & D
Answer
ExplanationRelated Ques
ANSWER: B & C
Explanation:
No explanation is available for this question!
22) How are the port pins of microcontroller calculated for time-multiplexing types of display?
a.4 + number of digits to be displayed
b.4 raised to the number of digits to be displayed
c.4 - number of digits to be displayed
d.4 x number of digits to be displayed
Answer
ExplanationRelated Ques
ANSWER: 4 + number of digits to be displayed Explanation:
No explanation is available for this question!
23) What does the RAM location at 44H indicates about the seven segment code?
a.7-segment code for the third character
b.7-segment code for the fourth character
c.Display of select code for third display
d.Display of select code for fourth display
Answer
Explanation
Related Ques
ANSWER: 7-segment code for the third character Explanation:
No explanation is available for this question!
1) Where does the comparison level occur for 16-bit contents in the compare mode operation?
a.Between CCPR1 register & TMR1
b.Between CCPR1 & CCPR2 registers
c.Between CCPR2 register & TMR1
d.Between CCPR2 register & TMR0
Answer
ExplanationRelated Ques
ANSWER: Between CCPR1 register & TMR1 Explanation:
No explanation is available for this question!
2) Why are the pulse width modulated outputs required in most of the applications?
a.To control average value of an input variables
b.To control average value of output variables
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: To control average value of output variables Explanation:
No explanation is available for this question!
3) What would be the resolution value if oscillator and PWM frequencies are 16MHz and 2 MHz respect
a.2
b.3
c. 4
d. 8
Answer
ExplanationRelated Ques
ANSWER: 3
Explanation:
No explanation is available for this question!
4) How do the variations in an average value get affected by PWM period?
a.Longer the PWM period, faster will be the variation in an average value
b.Shorter the PWM period, faster will be the variation in an average value
c.Shorter the PWM period, slower will be the variation in an average value
d.Longer the PWM period, slower will be the variation in an average value
Answer
ExplanationRelated Ques
ANSWER: Shorter the PWM period, faster will be the variation in an average value Explanation:
No explanation is available for this question!
5) Which among the below stated components should be filtered for determining the cut-off frequency corresponding to the PW period of low-pass filter?
a.Fundamental FPWM & higher harmonics
b.Resonant FPWM & higher harmonics
c.Slowly Varying DC components
d.Slowly Varying AC components
Answer
ExplanationRelated Ques
ANSWER: Fundamental FPWM & higher harmonics Explanation:
No explanation is available for this question!
6) Which among the below stated conditions are selected by the SSPCON & SSPSTAT control bits?
a.Slave Select mode in slave mode
b.Data input sample phase
c.Clock Rate in master mode
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: All of the above Explanation:
No explanation is available for this question!
7) Which bit of SSPCON must be necessarily set so as to enable the synchronization of serial port?
a.WCOL
b.SSPOV
c.CKP
d.SSPEN
Answer
ExplanationRelated Ques
ANSWER: SSPEN
Explanation:
No explanation is available for this question!
8) What should be the value of SSPM3:SSPM0 bits so that SPI can enter the slave mode by enabling S control?
a. 0000
b. 0100
c. 0010
d. 0001
Answer
ExplanationRelated Ques
ANSWER: 0100
Explanation:
No explanation is available for this question!
9) Which bits assist in determining the I2C bit rate during the initialization process of MSSP module in mode?
a.SSPADD
b.SSPBUF
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: SSPADD
Explanation:
No explanation is available for this question!
10) Which command/s should be essentially written for I2C input threshold selection and slew rate con operations?
a.SSPSTAT
b.SSPIF
c.ACKSTAT
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: SSPSTAT
Explanation:
No explanation is available for this question!
11) Where does the baud rate generation occur and begins to count the bits required to get transmitte an execution (set) of BF flag?
a.SCL line
b.SDA line
c. Both a & b
d. None of the above
Answer
ExplanationRelated Ques
ANSWER: SDA line
Explanation:
No explanation is available for this question!
12) How many upper bits of SSPSR are comparable to the address located in SSPADD especially after shifting of 8 bits into SSPSR under the execution of START condition?
a.7
b.8
c.16
d.32
Answer
ExplanationRelated Ques
ANSWER: 7
Explanation:
No explanation is available for this question!
13) Where should the value of TX9 bit be loaded during the 9 bit transmission in an asynchronous mo
a.TXSTA
b.RCSTA
c.SPBRG
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: TXSTA
Explanation:
No explanation is available for this question!
14) What is the purpose of a special function register SPBRG in USART?
a.To control the operation associated with baud rate generation
b.To control an oscillator frequency
c.To control or prevent the false bit transmission of 9th bit
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: To control the operation associated with baud rate generation Explanation:
No explanation is available for this question!
15) Why is the flag bit TXIF tested or examined in the PIR1 register after shifting all the data bits during initialization process of USART in asynchronous mode?
a.For ensuring the transmission of byte
b.For ensuring the reception of byte
c.For ensuring the on-chip baud rate generation
d.For ensuring the 9th bit as a parity
Answer
ExplanationRelated Ques
ANSWER: For ensuring the transmission of byte Explanation:
No explanation is available for this question!
16) How is the baud rate specified for high-speed (BRGH = 1) operation in an asynchronous mode?
a.FOSC / 8 (X + 1)
b.FOSC / 16 (X + 1)
c.FOSC / 32 (X + 1)
d.FOSC / 64 (X + 1)
Answer
ExplanationRelated Ques
ANSWER: FOSC / 16 (X + 1)
Explanation:
No explanation is available for this question!
17) What is the status of shift clock supply in an USART synchronous mode?
a.Master-internally, Slave-externally
b.Master-externally, Slave-internally
c.Master & Slave (both) - internally
d.Master & Slave (both) - externally
Answer
ExplanationRelated Ques
ANSWER: Master-internally, Slave-externally Explanation:
No explanation is available for this question!
18) Which bit plays a salient role in defining the master or slave mode in TXSTA register especially in synchronous mode?
a.RSRC
b.CSRC
c.SPEN
d.SYNC
Answer
ExplanationRelated Ques
ANSWER: CSRC
Explanation:
No explanation is available for this question!
19) Which register/s should set the SPEN bit in order to configure RC7/RX/DT pins as DT (data lines)?
a.TXSTA
b.RCSTA
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: RCSTA
Explanation:
No explanation is available for this question!
20) Which among the below assertions represent the salient features of PIC in C-18 compiler?
a.Transparent read/ write access to an external memory
b.Provision of supporting an inline assembly during the necessity of an overall control
c.Integration with MPLAB IDE for source-level debugging
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: All of the above Explanation:
No explanation is available for this question!
21) Which command-line option of compiler exhibits the banner comprising overall number of errors, messages, warnings and version number after an accomplishment of the compilation process?
a.help
b.verbose
c.overlay
d.char
Answer
ExplanationRelated Ques
ANSWER: verbose Explanation:
No explanation is available for this question!
22) In which aspects do the output functions specified in stdio.h differ from ANSI specified versions?
a.Provision of MPLAB specific extensions
b.Floating-point Format Support
c.Data in Program Memory
d.All of the above
Answer
ExplanationRelated Ques
ANSWER: All of the above
Explanation:
No explanation is available for this question!
23) What does the 'program idata' section of data memory contain in C-18 Compiler?
a.statically assigned/allocated initialized user variables
b.statically assigned /allocated uninitialized user variables
c.only executable instructions
d.variables as well as constants
Answer
ExplanationRelated Ques
ANSWER: statically assigned/allocated initialized user variables Explanation:
No explanation is available for this question!
24) Which instruction is applicable to set any bit while performing bitwise operation settings?
a.bcf
b.bsf
c.Both a & b
d.None of the above
Answer
ExplanationRelated Ques
ANSWER: bsf Explanation:
No explanation is available for this question!
25) Where is the result stored after an execution of increment and decrement operations over the spec purpose registers in PIC?
a.File Register
b.Working Register
c.Both a & b
d.
Answer
Explanation
Related Ques
ANSWER: Both a & b Explanation:
No explanation is available for this question!
26) Which flags of status register are most likely to get affected by the single-cycle increment and dec instructions?
a.P Flags
b.C Flags
c.OV Flags
d.Z Flags
Answer
ExplanationRelated Ques
ANSWER: Z Flags Explanation:
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